METHOD FOR PRODUCEING PASSAGE CONNECTIONS THROUGH A SUBSTRATE

Description

Domaine technique

[0001] This description relates generally to electronic devices, and more particularly to a device comprising a substrate crossed by conductive vias for connection between electronic circuits. Technique antérieure

[0002] An integrated circuit chip is defined by a substrate and by elements located on one side, called the front side, of the substrate. Among these elements, the chip includes electronic circuits formed by components such as transistors, resistors, diodes, capacitors, etc., and by electrically conductive connections between these components. One or more electronic chips may be arranged in an integrated circuit package. Such a package typically includes pins intended to be connected, for example soldered or welded, to a device such as a printed circuit board (PCB).

[0003] To electrically connect the electronic circuits of the chips to each other and / or to conductive structures such as the pins of the package, electrical connections can be provided by conductive vias passing through the substrate of the chips and / or conductive vias passing through one or more substrates other than those of the chips.

[0004] WO 2010 / 014465 describes a method of coating through-wafer vias for three-dimensional packaging.

[0005] Document US 2017 / 287728 describes a method of metallizing vias inside a substrate.

[0006] Document US 2015 / 235899 describes a method of forming a through-thread.

[0007] Document FR 2 930 840 describes a method for reconnecting a circuit illuminated from the rear face. Summary of the invention

[0008] There is a need for a method for producing a substrate crossed by vias having, compared to conventional substrates, a higher number of vias per unit area.

[0009] There is a need for a method for producing vias that is simpler to implement and / or faster than conventional methods.

[0010] One embodiment overcomes all or part of the drawbacks of known methods for producing vias.

[0011] One embodiment provides a manufacturing method according to claim 1.

[0012] According to one embodiment, the openings have a form factor greater than 10.

[0013] According to one embodiment, a first additional layer located between the support and the priming layer is adapted to cause a weaker adhesion of the priming layer with the support than with the substrate.

[0014] According to one embodiment, a first additional etch stop layer of the support is located between the support and the priming layer.

[0015] According to one embodiment, a second additional adhesion layer of the primer layer is located between the primer layer and the first additional layer.

[0016] According to one embodiment, the priming layer and the support are separated by an electrical insulator.

[0017] According to one embodiment, the walls of the opening are covered with an insulating layer.

[0018] According to one embodiment, said insulating layer is formed by thermal oxidation.

[0019] According to one embodiment, the method comprises a step of forming blind cavities in a wafer comprising the future substrate, and a step of removing a portion of the wafer comprising the bottoms of the cavities.

[0020] According to one embodiment, a portion of said insulating layer covering said bottoms of the cavities is left in place during the removal step, another insulating layer is deposited on another face of the substrate opposite said face, and said portion is then removed.

[0021] According to one embodiment, an additional priming layer in contact with said priming layer covers at least part of the walls of the openings.

[0022] According to one embodiment, the method comprises a step of forming another priming layer on said other insulating layer or on another face of the substrate opposite said face.

[0023] According to one embodiment, the electrodeposition step comprises forming a solder ball on the through-member. Brève description des dessins

[0024] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 is a schematic sectional view showing an example of a device to which the described embodiments apply; figure 2 is a schematic sectional view showing another example of a device to which the described embodiments apply; figure 3 is a schematic sectional view showing a step of an embodiment of a method of manufacturing one or more conductive elements passing through a substrate; the figure 4 is a schematic sectional view representing another step of the process; the figure 5 is a schematic sectional view representing another step of the process; the figure 6 is a partial and schematic sectional view, representing an exemplary embodiment of an element of the structure obtained at the stage of the figure 3 ; there figure 7 is a schematic sectional view showing a step of a first embodiment of the step of the figure 3 ; there figure 8 is a schematic sectional view showing another step of the first embodiment; the figure 9 is a schematic sectional view showing another step of the first embodiment; the figure 10 is a schematic sectional view showing a step of a second embodiment of the step of the figure 3 ; there figure 11 is a schematic sectional view showing another step of the second embodiment; figure 12 is a schematic sectional view showing another step of the second embodiment; figure 13 is a schematic sectional view showing another step of the second embodiment; figure 14 is a schematic sectional view showing another step of the second embodiment; figure 15 is a schematic sectional view showing a third embodiment of the step of the figure 3 ; there figure 16 is a schematic sectional view showing a step of a fourth embodiment of the step of the figure 3 ; there figure 17 is a schematic sectional view showing another step of the fourth embodiment; figure 18 is a schematic sectional view showing a step of a fifth embodiment of the step of the figure 3 ; there figure 19 is a schematic sectional view representing a step similar to that of the figure 4 after implementation of the fifth embodiment; and the figure 20 is a schematic sectional view showing a variant of the step of the figure 5 . Description des modes de réalisation

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, integrated circuit electronic chips and their electronic circuits are not described in detail, the described embodiments being compatible with conventional integrated circuit chips.

[0027] Unless otherwise specified, when two elements are referred to connected together, this means directly connected without intermediate elements other than conductors, and when two elements are referred to connected or coupled together, this means that these two elements can be connected or be connected or coupled through one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0030] There figure 1 is a schematic sectional view showing an example of a device 100 to which the described embodiments apply.

[0031] The device 100 comprises two electronic chips 110H and 110L located on two opposite faces of a connection structure 120. The connection structure 120 connects circuits of the chips together and ensures the mechanical maintenance of the chips.

[0032] The connection structure 120 comprises a substrate 122. Preferably, the substrate 122 has the shape of a plate or wafer having two main opposite faces 122H and 122L. The substrate 122 is preferably a portion of a semiconductor wafer, for example made of silicon. The substrate 122 may also be made of ceramic or for example glass, or may also comprise an organic material such as an epoxy resin, for example a mixture of epoxy resin and glass fibers. More generally, the substrate may be any plate, wafer or portion of wafer whose two main faces are adapted to be at least partly covered with conductive elements.

[0033] The substrate 122 is traversed by vias 124. Preferably, the vias 124 connect together electrically conductive regions 126L, 126H located on the opposite faces of the substrate 122. Two vias are shown as an example, but the connection structure 120 preferably comprises a number of vias greater than 2. Each of the vias 124 is defined by a conductive element passing through the substrate 122. Each via 124 electrically connects a conductive region 126L located on one of the opposite faces (122L) of the substrate, to a conductive region 126H located on the other of the opposite faces (122H) of the substrate. The conductive regions 126H and 126L are typically metallic regions. Vias 124 can have cylinder, ring, concentric ring, or straight trench filling shapes (wall shapes).The vias 124 typically have elongated shapes in the substrate thickness direction, i.e., each via has a larger dimension in the substrate thickness direction (longitudinal direction of the via) than in at least one transverse direction of the via.

[0034] Each chip 110H, 110L includes bonding pads 112. The bonding pads 112 are intended to connect electronic circuits (not shown) of the chip to other circuits external to the chip. Such bonding pads are typically metal regions located on the front face or on the back face of the chip.

[0035] The connection pads 112 of the chips 110H and 110L are respectively connected to the conductive regions 126H and 126L. More precisely, each connection pad 112 is in electrical contact with one of the conductive regions 126H and 126L, for example by means of a solder or brazing material 130 or by direct metal-to-metal bonding. For this, the positions of the conductive regions 126H and 126L correspond to those of the connection pads 112. Furthermore, the material 130 mechanically fixes the connection pads 112 on the conductive regions 126H and 126L, which makes it possible to ensure the mechanical retention of the chips on the connection structure 120. In the example shown, the connection pads 112 of the chips 110H and 110L are located in the extension of the vias 124 (i.e. above and below the vias), however, the connection pads of the chips are often located outside the extension of the vias.

[0036] Preferably, the conductive regions 126H and / or 126L comprise one or more connection pads 128 and tracks 129 connecting the connection pads 128 to the vias 124. A single connection pad 128 has been shown, but the connection structure preferably comprises several connection pads 128 located on one and / or the other of the opposite faces 122H and 122L of the substrate 122. In one example, the device 100 is intended to be arranged in a package provided with pins, and the connection pads 128 are intended to be connected to the pins. In another example, the connection pads 128 are intended to connect the device 100 to another device, not shown.

[0037] In one variant, the connection structure 120 is constituted by an electronic chip. The substrate is then preferably a portion of a semiconductor wafer, for example silicon.

[0038] There figure 2 is a schematic sectional view showing another example of a device 200 to which the described embodiments apply.

[0039] Device 200 of the figure 2 differs from device 100 of the figure 1 in that: the chip 110L is omitted and the conductive regions 126L are replaced by connection pads 128L intended to be connected for example to the pins of a package; a chip 110A is located on a part 220 devoid of vias of the connection structure 120, on the side of the face 122H; and the conductive regions 126H comprise tracks connecting the connection pads 112 of the chip 110A to the vias 124.

[0040] The devices 100 and 200 described above in relation to the figures 1 et 2 are particular examples, and the embodiments described below apply to any type of device comprising one or more chips connected to a connection structure 120 crossed by vias. More generally, the embodiments described below apply to any device comprising a substrate such as the substrate 122 crossed by conductive elements such as the vias 124.

[0041] THE figures 3 à 5 are schematic sectional views showing steps of one embodiment of a method of manufacturing one or more conductive elements passing through a substrate 322.

[0042] The substrate 322 may be of the type of the substrate 122 described above in relation to the figures 1 et 2 . However, preferably, the substrate 322 is a plate, more preferably a semiconductor wafer, intended to be cut into connection structures such as the structures 120 of the figures 1 et 2 and / or in individual chips and / or in any substrate of the type described in relation to the figures 1 et 2 .

[0043] The conductive elements that the process allows to form are preferably vias of the type of vias 124 of the figures 1 et 2 , or constitute at least a portion of the vias 124. More specifically, the described embodiments comprise a step of electrolytic deposition, or electrodeposition, of at least a portion of the conductive elements. The electrodeposited material is preferably copper, although the described embodiments also apply to any material usually used for producing vias and which can be electrolytically deposited, such as nickel, nickel and iron alloys, gold, antimony or silver.

[0044] At the stage of the figure 3 , we form a stack comprising successively (from bottom to top): a support 310, typically in the form of a plate; a conductive priming layer 315, sometimes called a nucleation layer, i.e. a layer adapted to form a cathode on which the material of the conductive elements can be formed by electrodeposition; and the substrate 322, crossed by openings 325 located at the locations of the future conductive elements.

[0045] The support 310 is preferably of the same nature as the substrate 322, or the support 310 has a coefficient of thermal expansion identical or substantially identical to that of the substrate 322. This makes it possible to avoid various problems of deformation of the stack during subsequent steps of the method. Such problems would be likely to appear following, for example, an increase in the temperature of the stack if the substrate and the support do not expand in the same way.

[0046] The openings 325 preferably extend orthogonally to the main faces 122H and 122L of the substrate 322, in other words, the openings have one side located on the side of the face 122H and another side located on the side of the face 122L. The openings 325 are formed at the locations of the future conductive elements such as vias. The openings 325 preferably have a form factor greater than 10. The form factor of an element such as the openings 325 or the vias is defined by the ratio between the dimension of the element in a longitudinal direction orthogonal to the main faces of the substrate and the smallest transverse dimension of the element.

[0047] In the stack, the substrate 322 and the openings 325 are located on the same side of the priming layer 315. In other words, the priming layer 315 has a face 317, facing the substrate, adapted to receive the material of the conductive elements. More precisely, for each of the openings 325, a portion 316 of the priming layer closes or blocks the opening on the side of the face of the substrate covered by the priming layer (face 122L).

[0048] Preferably, the layer 315 is a solid layer, i.e. one that does not have openings, more preferably uniform, i.e. one of constant thickness. Each portion 316 then completely closes the corresponding opening 325. The layer 315 makes it possible, compared to a layer that would be discontinuous and / or non-uniform, to improve the adhesion of the layer and the subsequent filling of the openings 325 with the electrodeposited material.

[0049] Preferably, the priming layer 315 is of planar shape, that is to say that the portions 316 are located in the extension of the priming layer 315. However, this is not limiting, and the portions 316 can be located at any position in and / or opposite (or plumb) the opening, on the side of the opening facing the support. The priming layer is for example made of the same material as that which will be deposited. For example, the priming layer is a layer of copper with a thickness of between 100 nm and 2 µm.

[0050] The embodiments described are compatible with any method of producing a stack such as that of the figure 3 . Preferably, the support 310 is previously covered with the priming layer 315. The openings 325 can be formed before or after placing the substrate on the priming layer 315 covering the support 310. Various examples of embodiments of the stack of the support 310, of the priming layer 315, and of the substrate 322 crossed by the openings 325, are described below in relation to the figures 6 à 18 .

[0051] Furthermore, although the entire substrate 322 and the priming layer 315 are located on a support, this is not limiting, and the support 310 could be omitted. However, providing the support 310 pre-covered with the priming layer 315 facilitates (or allows, in the case where the substrate is too thin to be handled) the placement and maintenance of the priming layer against the openings 325 and the face 122L of the substrate, compared to an embodiment in which the support 310 would be omitted.

[0052] Preferably, in a peripheral portion of the stack, the support 310 and the priming layer 315 extend laterally beyond the substrate 322. In other words, a peripheral portion 330 of the priming layer 315 and of the support 310 protrudes around the substrate 322. The face facing the substrate 322 of the priming layer 315 is thus accessible or clear in the peripheral portion 330, that is to say that this face is not covered by the substrate 322. For example, the peripheral portion 330 has a width of approximately 5 mm. Preferably, the substrate and the support are two circular-shaped plates having different diameters. For example, the substrate and the support are obtained from two identical circular plates, for example semiconductor wafers such as silicon wafers, and a peripheral portion of the plate intended to form the substrate 322 has been removed.

[0053] An electrical connection 350 is formed in contact with the priming layer 315 in the peripheral portion 330. The electrical connection 350 is provided to apply a cathode potential to the priming layer during the implementation of the electrodeposition. Although the electrical connection 350 is located on the peripheral portion 350, this is not limiting, the described embodiments being compatible with any electrical connection with the priming layer 315. In particular, the peripheral portion can be omitted. However, providing the electrical connection 350 in the peripheral portion facilitates the establishment of the electrical connection compared to a device without the peripheral portion 330. The support, in particular its size, is compatible with usual electrodeposition equipment.

[0054] At the stage of the figure 4 , the material of the conductive elements to be formed is deposited by electrodeposition in the openings 325. Preferably, the openings are completely filled, which makes it possible to obtain vias 124 passing through the substrate 322. Alternatively, only a portion of the openings is filled with the electrodeposited material, and the remainder of the opening can be filled with another conductive material by any conventional method.

[0055] Electrodeposition is carried out by passing a current flowing from an anode to the priming layer 315 via an electrolyte. The anode and the electrolyte are neither detailed nor shown, and the parameters of the electrolysis are not described here, the described embodiments being compatible with the usual electrodeposition methods. In particular, the described embodiments are compatible with the usual techniques used to improve the diffusion of chemical species in the electrolyte, such as stirring, adding an accelerating agent, etc.

[0056] Because the priming layer covers at least part of the face 122L, and because the portions 316 of the priming layer closing the openings 135 are located on the side of the face 122L, the current reaches exclusively the priming layer located at the bottom of the openings 325. At the start of the deposition, the metal ions located in the electrolyte are attracted by the portions 316 of the priming layer (brought to the cathode potential). Thus, the deposition grows from the bottom of the openings. In other words, the electrodeposition is carried out from the portions 316 of the priming layer 315 closing the openings 325. In particular, compared to a method which would use a priming layer covering the upper face 122H, the risk of the electrolytic deposit forming on the face 122H blocking the openings before complete filling is avoided. This makes it possible to easily obtain via form factors greater than 10, for example greater than 20.In one example, the substrate has a thickness (corresponding to a via height) greater than 200 µm and the vias have widths less than 10 µm. In another example, the via height is between 100 and 400 µm and the vias have diameters between 0.5 and 10 µm.

[0057] Increasing the via form factor allows, for a given substrate thickness, to increase the number of vias per unit area of ​​the substrate, or, for a given number of vias per unit area, to increase the thickness of the substrate. It is thus possible to increase the number of vias and / or mechanically strengthen the substrate.

[0058] According to one advantage, the vias obtained are blind, i.e. they completely block the openings 325. Such blind vias form better electrical connections (i.e. with lower electrical resistance) than vias which do not completely block the openings, for example vias whose conductive material covers the walls of the openings but leaves a passage in the center of the openings.

[0059] According to another advantage, it is possible to dispense with a priming layer on the walls of the openings 135. This avoids various problems of deposition of this layer when the openings have high form factors, for example greater than 10. In addition, the embodiments described are compatible with any method, compliant or non-compliant, of forming the priming layer on the support 310. For example, the priming layer is produced by chemical or physical vapor deposition CVD or PVD (Physical Vapor Deposition), or by ionized physical vapor deposition IPVD (Ionized Physical Vapor Deposition). The formation of the priming layer is therefore simpler than for a priming layer covering the interior walls of the openings 135.

[0060] At the stage of the figure 5 , 126H conductive regions are formed, as described in relation to the figure 1 , on the face 122H of the substrate 322. The conductive regions 126H are preferentially formed on an insulating layer, not shown in figure 5 , crossed by the vias 124. Preferably, on each via 124, one of the regions 126H covers the end of the via and extends over the substrate around the via. The embodiments described are compatible with the usual methods of forming metal regions on the faces of a substrate.

[0061] The substrate 310 is then removed. Preferably, the priming layer 315 remains on the face 122L of the substrate 322. Alternatively, the substrate 310 is removed before formation of the conductive regions 126H.

[0062] Conductive regions 126L are then formed. For example, the conductive regions 126L, as described in connection with the figure 1 , are formed on the face 122L. Preferably, the conductive regions 126L are parts of the seed layer 315 and of a possible additional conductive layer (not shown) deposited on the layer 315 after removal of the support 310. Alternatively, the additional layer is deposited on the support 310 before forming the seed layer 315. A part of the seed layer and of the possible additional layer is removed, for example by etching, so that the remaining parts constitute the conductive regions 126L. Preferably, for each of the vias 124, one of the regions 126L covers the lower end of the via and extends on the face 122L of the substrate around the via, and / or one of the regions 126H covers the upper end of the via and extends on the face 122H of the substrate around the via.

[0063] Besides the fact, mentioned previously in relation to the figures 1 et 2 , that the conductive regions 126H and 126L make it possible to form conductive tracks and connection pads, the conductive regions 126H and 126L extending on the substrate around the via make it possible to improve the mechanical strength of the via in place in the corresponding opening 235. Thus, the vias are mechanically held integral with the substrate. Alternatively, the vias are mechanically secured to the substrate without providing regions 126H and 126L extending on the substrate around each via, for example by adhesion in the openings.

[0064] For example, in a later step, the substrate 322 is cut along cutting paths 360 to divide the substrate 322 into individual substrates 122.

[0065] There figure 6 is a partial, schematic sectional view showing an exemplary embodiment of the support 310 covered with the priming layer 315, as described in relation to the figure 3 . More specifically, in this embodiment, additional layers 400, 410 and 420 are interposed, in this order from the support 310, between the support 310 and the seed layer 315.

[0066] The additional layer 400 is electrically insulating, for example the layer 400 is a layer of silicon oxide. The additional layer 400 is preferably in contact with the support 310. In the case of an electrically conductive or semiconductive support, for example made of silicon, the presence of this layer facilitates the electrolytic deposition, by preventing the support 310 from being brought to the cathode potential at the same time as the priming layer. However, the layer 400 may be omitted, in particular in the case where the support 310 is electrically insulating.

[0067] The additional layer 410 is adapted to cause a weaker adhesion of the priming layer with the support 310 than with the substrate 322. The layer 410 allows the support to be removed at the step of the figure 5 by exerting a separation force between the support and the substrate, so as to break the layer 410 or separate it from the layer 400 and / or the layer 420. In one embodiment, the layer 410 is for example made of a thermoplastic type polymer material, i.e. a temporary glue. The thickness of the layer 410 is preferably a few micrometers, for example between 5 µm and 10 µm. The layer 410 may be made of any material, for example metallic, whose adhesion energy with the layer 400 is sufficiently low to be able to separate the layers 400 and 410 while leaving the priming layer 315 on the substrate 322. This is not limiting, the embodiments described are compatible with any method of removing the support 310. Thus, in a variant, the support 310 is removed by etching, and the additional layer 410 is omitted or constitutes an etching stop layer.

[0068] Alternatively, the additional layers 400 and 410 are combined, that is to say that the additional layer 410, adapted to facilitate the removal of the support 310, constitutes an electrical insulation layer.

[0069] The additional layer 420 is made of a material suitable for facilitating the formation and / or adhesion of the priming layer to the layer 410. The layer 420 is, for example, made of titanium or titanium nitride. The thickness of the layer 420 is, for example, between 50 and 200 nm. Alternatively, the additional layer 420 is omitted.

[0070] THE figures 7 à 9 are schematic sectional views showing steps of a first embodiment of the step of the figure 3 . More specifically, in this embodiment, the openings 325 are formed after placing the substrate 322 on the support 310.

[0071] At the stage of the figure 7 , the substrate 322, for example a silicon wafer, is placed in place on the priming layer 315 covering the support 310. Preferably, the face 122L of the substrate has been previously covered with an electrically insulating layer 510L, for example made of silicon oxide. For this placement, preferably, a polishing, for example a chemical-mechanical polishing, of the face of the insulating layer 510L (or of the substrate 322 in the absence of a layer 510L) intended to be in contact with the priming layer, and / or of the face of the priming layer intended to be in contact with the insulating layer 510L (or with the substrate 322, face 122L) is carried out beforehand. Preferably, the surface conditions of the faces thus polished allow molecular bonding type adhesion between the priming layer and the insulating layer 510. Bonding is typically obtained by pressurizing and heating.

[0072] Preferably, the bonding obtained is sufficient to be waterproof, in particular with respect to the electrolyte used in the step of figure 4 , on at least 90% of the bonded surface. This is not limiting, and the substrate 322 and the priming layer 315 may, as a variant, be assembled in a non-sealed manner, for example the substrate may only be placed on the support. However, compared to such a variant, the sealed bonding makes it possible to facilitate the steps, subsequent to the electrodeposition, of removing the support and forming conductive regions on the face 122L from the priming layer 315.

[0073] Preferably, the face 122H of the substrate is covered with an insulating layer 510H. The insulating layer 510H is for example formed at the same time as the layer 510L, for example by thermal oxidation. Alternatively, the insulating layer is formed after the step of figure 8 . In this variant, it is possible to provide for thinning the substrate 322 before the step of the figure 8 .

[0074] At the stage of the figure 8 , a mask 520 is formed by lithography, crossed by openings 522 at the locations of the future openings 325. The openings 325 are then etched vertically in line with the openings 522, from the upper surface of the layer 510H to the level of the upper face of the priming layer 315, or to a level located in the priming layer 315. The openings 325 pass through the upper insulating layer 510H, the substrate 322, and the insulating layer 510L. The priming layer 315 has clear, or accessible, portions 316 located at the bottom of the openings 325. The described embodiments are compatible with the usual methods of directional etching of insulating and substrate layers.

[0075] At the stage of the figure 9 , the mask 520 is removed. The walls of the openings 325 are covered with a layer of electrical insulation 530, for example silicon oxide. The insulating layer 510H may be, in whole or in part, formed at this step.

[0076] The insulating layer 530 makes it possible to electrically insulate the substrate and the future vias formed in the openings from each other. In addition, the insulating layer makes it possible to prevent the material of the future vias from diffusing towards the substrate and degrading the properties of the substrate material. The insulating layers 510L and 510H make it possible to obtain electrical insulation between the substrate and the future conductive regions 126L and 126H ( figure 5 ) formed on its faces 122L and 122H.

[0077] According to a preferred embodiment, the electrical insulator 530 is deposited in a conformal manner, preferably by a CVD type process. The thermal budget of such a deposition makes it possible to provide an additional polymer layer, of the type of layer 410 ( figure 6 ), located between the support 310 and the priming layer 315. Furthermore, the thermal budget of such a deposition is compatible with the substrate 322 in the case where the latter is intended to be cut into individual chips, the substrate 322 then comprising elements of the electronic circuits of the chips. The embodiments described here are compatible with the usual methods of conformal deposition of insulating layers.

[0078] THE figures 10 à 14 are schematic sectional views showing steps of a second embodiment of the step of the figure 3 More precisely, the openings 325 are made partly before and partly after placing the substrate 322 on the support 310.

[0079] At the stage of the figure 10 , a wafer 622 is provided in which the future substrate 322 will be defined, for example a semiconductor wafer such as a silicon wafer.

[0080] Then, from one face of the silicon wafer intended to constitute the future lower face 122L of the future substrate (shown turned over), blind cavities 625 are formed, that is to say cavities not opening onto the face (face 622H) of the wafer 622 opposite the face 122L.

[0081] Preferably, a peripheral portion of the slice 622 (corresponding to the portion 330 in figure 3 ). Removal may be performed before or after the formation of the cavities 625.

[0082] After this, an insulating layer 630 is formed covering all the surfaces of the wafer 622, as well as the walls and bottoms of the cavities. Preferably, the insulating layer 630 is formed by thermal oxidation. Thermal oxidation has the advantage, compared to a deposition method, of facilitating the formation of the insulating layer on the walls of cavities having the high form factors defined above, in particular on the walls of cavities having very high form factors, for example greater than 15.

[0083] At the stage of the figure 11 , the wafer 622 is placed on the priming layer 315 covering the support 310. The part of the layer 630 covering the face 122L is brought into contact with the priming layer. The placement is preferably carried out in a manner similar to that described in relation to the figure 7 . In particular, molecular bonding is preferably carried out after polishing the surfaces to be bonded together. For example, the distance between the bottom of the cavities 625 and the face 622H is between 5 and 50 µm, preferably between 10 and 20 µm. This distance is, in the example shown, obtained at the step of figure 10 , however, this distance is preferentially obtained by a step, not shown, of thinning the slice 622 on the side of its face 622H.

[0084] At the stage of the figure 12 , a portion of the wafer comprising the bottoms of the cavities is removed, preferably first by mechanical polishing, then by etching. The remaining portion of the wafer constitutes the substrate 322. Each of the cavities 635 becomes an opening 325 passing through the substrate.

[0085] Preferably, the removal of the material from the wafer is selective with respect to the material of the insulating layer 630. Thus, a portion of the insulating layer 630 initially covering the bottoms of the cavities 625 is left in place at the removal step. Preferably, the removal is carried out so that portions 632 of the layer 630 initially located at the bottom of the cavities 625 are found above the upper surface of the substrate (face 122H). The level of the face 122H is preferably located at a height h of a few micrometers, for example between 2 µm and 10 µm, below the lower level of the portions 632 (i.e. the level of the faces of the portions 632 oriented towards the openings 325).

[0086] Alternatively, the portions 632 of the layer 630 are also removed, and the structure allowing the electrolysis of the step of the figure 4 This removal is carried out for example by chemical-mechanical polishing or by dry etching, so as not to damage the portions of the layer 630 covering the walls of the openings 325 and / or the portions 316 of the priming layer located under the openings 325.

[0087] At the stage of the figure 13 , another insulating layer (layer 640), for example made of silicon oxide, is deposited on the upper face 122H of the substrate. The portions of the layer 632 make it possible to prevent part of the material of the layer 640 from being deposited in the openings 325. Preferably, the thickness of the layer 640 is less than the height h between the face 122H and the lower level of the portions 632.

[0088] At the stage of the figure 14 , all elements located above the upper level of the layer 640 are removed, preferably by polishing. This removes the portions 632 of the insulating layer 630. The portions of the layer 640 located on the portion 632 are also removed. The difference in level h thus makes it possible to unblock the openings 325 by polishing, while avoiding damage to the portions of the layer 630 covering the walls of the openings 325 and / or the portions 316 of the priming layer located under the openings 325.

[0089] The structure obtained at the stage of the figure 14 can be used to carry out the electrolysis described in connection with the figure 4 The portions of the layer 630 located on the walls of the openings make it possible to electrically isolate the vias or the conductive elements formed in the openings, and also make it possible to prevent diffusion towards the substrate 322 of the material electrodeposited in the openings 325.

[0090] The 640 layer obtained will allow, in the structure obtained at the stage of the figure 5 , to obtain electrical insulation between the conductive regions 126H ( figure 5 ) and substrate 322.

[0091] There figure 15 is a schematic sectional view showing a third embodiment of the step of the figure 3 . More particularly, the openings 325 are formed before the substrate 322 is placed on the priming layer 315 covering the support 310 (support and priming layer not shown in figure 15 ).

[0092] At the stage of the figure 15 , the openings 325 are formed in the substrate 322. The substrate is preferably defined by a portion of semiconductor wafer, for example silicon. This embodiment is compatible with any conventional means of forming openings in a substrate, such as chemical or plasma etching, laser machining, mechanical machining, pressurized water machining, etc.

[0093] An insulating layer 730 is then formed covering all the surfaces of the substrate 322, and in particular the walls of the openings 325. The insulating layer 730 is preferably obtained by thermal oxidation, for example at a temperature of the order of 1000°C. As mentioned, thermal oxidation makes it possible to form the insulating layer on the walls of openings having high form factors more easily than conformal deposition methods.

[0094] In one variant, an insulating layer is formed on the upper face 122H and / or an insulating layer is formed on the lower face 122L prior to the formation of the openings 325. This or these insulating layers are then crossed by the openings. The presence of this layer makes it possible to limit the growth of the oxide on the faces 122H and 122L during thermal oxidation.

[0095] THE figures 16 And 17are schematic sectional views showing steps of a fourth embodiment of the step of the figure 3 .

[0096] At the stage of the figure 16 , the openings 325 passing through the substrate 322 are formed. A conductive layer 810 is then formed on the face 122L of the substrate (face intended to be covered by the priming layer 135). The conductive layer 810 is deposited so that a portion 812 of the layer 810 covers a portion of the walls of the openings 325 on the side of the face 122L. This can be obtained by an incompletely conformal deposition, in which the deposited material does not reach the parts of the openings 325 furthest from the face 122L, in particular due to a high form factor of the openings 325.

[0097] At the stage of the figure 17 , the substrate is placed on the support 310. More precisely, the layer 810 and the priming layer 315 are placed in contact with each other, preferably by molecular type bonding.

[0098] Preferably, the layer 810 is of the same material as the priming layer, or of another material on which the electrolytic deposition can be formed. The metal layer 810 thus constitutes an additional priming layer. The portions 812 of the priming layer 810 are in contact with the portions 316 of the priming layer 315 and make it easier to start the electrolytic deposition compared to an electrodeposition carried out without the portions 812.

[0099] Preferably, the layer 810 is formed on a bonding layer, not shown, for example made of titanium or titanium nitride. The bonding layer allows better adhesion of the metal, for example copper, of the layer 810. This ensures mechanical solidarity between the future via and the substrate 322. In addition, the bonding layer may have barrier properties making it possible to prevent the diffusion of the electrodeposited material towards the substrate, and therefore makes it possible to prevent the material of the substrate from being altered by this diffusion.

[0100] This embodiment can be combined with embodiments in which the openings or cavities are formed, or partially formed, before placing the substrate on the support, for example the embodiment of figures 10 à 14 or that of the figure 15 .

[0101] Alternatively, the layer 810 completely covers the walls of the openings 325.

[0102] There figure 18 is a schematic sectional view showing a step of a fifth embodiment of the step of the figure 3 . There figure 19 is a schematic sectional view representing a step similar to that of the figure 4 after implementation of the fifth embodiment.

[0103] At the stage of the figure 18 , another priming layer (layer 850) is formed on the upper face 122H of the substrate. Preferably, the priming layer 850 is formed after formation of the openings 325. The priming layer 850 can then, depending on the conformity of the deposition, cover the substrate 322 only around the openings or also cover at least part of the walls of the openings. Insulating portions 860 are then formed on the layer 850. The insulating portions 860 are preferably formed at the locations of the face 122H which will be, after implementation of the step of figure 5 , devoid of conductive regions 126H. For example, a photosensitive resin layer is formed, for example a DFR (Dry Film Resist) dry film resin so that the resin does not penetrate into the cavities 325. The portions of the resin at the locations of the future conductive regions 126H are then removed by lithography. The remaining portions of the resin layer constitute the insulating portions 860.

[0104] At the stage of the figure 19 , the vias 124 are formed by electrodeposition. At the end of the formation of the vias 124, these form an electrical contact with the seed layer 850, and the deposition continues on all the portions of seed layer not covered by the portions 860. The portions thus deposited will form the conductive regions 126H after removal, at the step of the figure 5 , portions of the priming layer 850 located under the portions 860.

[0105] As long as the vias being formed have not reached the seed layer 850, the deposit is formed only from the potions 316 of the seed layer 310 (from the bottom of the openings). It is thus possible to produce the vias 124 and the conductive regions 126H during the same electrolysis step, which simplifies the manufacturing process, while benefiting from the aforementioned advantages, in particular the advantage of producing vias having high form factors without the risk of blocking the upper parts of the cavities before having completely formed the vias.

[0106] In an alternative embodiment, the portions 860 are omitted. Electrodeposition is then carried out over the entire surface of the layer 850. At the stage of the figure 5 , the parts of the 850 layer located outside the 126H conductive regions are then etched.

[0107] The present embodiment is compatible with the previous embodiments, namely that the substrate 322 may correspond to the substrate obtained in the embodiments of figures 7 à 9 , of the figures 10 à 14 , of the figure 15 , and / or figures 16 And 17 . In particular, the seed layer 850 may be formed on an insulating layer such as the 510H layer ( figure 9 ), 640 ( figure 14 ) or 730 ( figure 15 ).

[0108] There figure 20 is a schematic sectional view showing a variant of the step of the figure 5 . In this variant, a solder pad 910 is formed by electrodeposition on each of the vias 124. For this, the electrodeposition of the material of the vias is continued by electrodeposition, preferably of a fusible alloy, for example a tin-based alloy. The alloy is then deposited only on the tops of the vias 124. This step can be followed by a melting step making it possible to give the connection pads 910 the shape of balls. This embodiment is compatible with those of figures 7 à 9 , 10 has 14, 15 , and / or 16 And 17 .

[0109] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. A method of manufacturing at least one element (124) crossing a substrate (322) assembled on a support (310), comprising a step of electrodeposition of at least a portion of said element in an opening (325) crossing the substrate (322) and on a portion (316) of a conductive seed layer (315) located between the substrate (322) and the support (310) on at least a portion of a surface (122L) of the substrate, said portion (316) of the seed layer being located on a same side of the opening (325) as said surface (122L) of the substrate, and the support (310) and the seed layer (315) extending laterally beyond the substrate (322).

2. The method according to claim 1, wherein the openings (325) have a form factor greater than 10.

3. The method according to claim 1 or 2, wherein a first additional layer (410) located between the support (310) and the seed layer (315) is capable of causing a lower adhesion of the seed layer (315) to the support (310) than to the substrate (322).

4. The method according to any of claims 1 to 3, wherein a first additional etch stop layer (410) of the support (310) is located between the support and the seed layer (315).

5. The method according to claim 3 or 4, wherein a second additional bonding layer (420) of the seed layer (315) is located between the seed later (315) and the first additional layer (410).

6. The method according to any of claims 3 to 5, wherein the seed layer (315) and the support (310) are separated by an electric insulator (400).

7. The method according to any of claims 1 to 6, wherein the walls of the opening (325) are covered with an insulating layer (530; 630; 730).

8. The method according to claim 7, wherein said insulating layer (530; 630; 730) is formed by thermal oxidation.

9. The method according to claim 6 or 7, comprising a step of forming of blind cavities (625) in a wafer (622) comprising the future substrate (322), and a step of removal of a portion of the wafer comprising the bottoms of the cavities.

10. The method according to claim 9, wherein a portion (632) of said insulating layer (630) covering said bottoms of the cavities (622) is left in place at the removal step, another insulating layer (640) is deposited on another surface (122H) of the substrate (322) opposite to said surface (122L), and said portion (632) is then removed.

11. The method according to any of claims 1 to 10, wherein an additional seed layer (810) in contact with said seed layer (315) covers at least a portion of the walls of the openings (325) .

12. The method according to any of claims 1 to 11, comprising a step of forming another seed layer (850) on said other insulating layer (640) or on another surface (122H) of the substrate (322) opposite to said surface (122L).

13. The method according to any of claims 1 to 12, wherein the electrodeposition step comprises the forming of a solder bump (910) on the crossing element (124).