METHOD FOR MANUFACTURING AN INTEGRATED PHOTON DEVICE

Description

Domaine technique

[0001] This description relates to a method for manufacturing an integrated photonic device. Technique antérieure

[0002] Known methods for manufacturing integrated photonic devices have several drawbacks.

[0003] It would be desirable to have a manufacturing process for an integrated photonic device, a process that overcomes all or some of the drawbacks of known processes. Documents US8213751, US2016 / 178861, US2014 / 254978, and US2015 / 030282 describe examples of the fabrication of integrated photonic circuits. Summary of the invention

[0004] The invention is defined by claim 1.

[0005] According to one embodiment, the step of forming photonic components in said at least a first and at least a second vignette is subsequent to the transfer step.

[0006] According to one embodiment, the process further comprises, after the transfer step, a collective thinning step of said at least a first and at least a second vignette, by mechanical grinding from their faces opposite the first substrate.

[0007] According to one embodiment, the process further comprises, after the transfer step, a step of removing, by chemical etching, from a growth substrate of said at least a first vignette, and a step of removing, by chemical etching, from a deposition substrate of said at least a second vignette.

[0008] According to one embodiment, during the transfer step, said at least a first and at least a second vignette are transferred simultaneously onto the photonic circuit by means of a temporary support substrate.

[0009] According to one embodiment, during the transfer step, said at least a first and at least a second vignette are fixed by molecular bonding on said face of the photonic circuit.

[0010] According to one embodiment, the molecular bonding implemented during the transfer step is a direct oxide-oxide bonding.

[0011] According to one embodiment, each second vignette comprises a stoichiometric Si 3 N 4 layer deposited by LPCVD.

[0012] According to one embodiment, the process includes, before the transfer step, a localized doping step of the first substrate for the realization of a PN junction of a component of the photonic circuit.

[0013] According to one embodiment, the first substrate is a silicon-on-insulator type substrate.

[0014] According to one embodiment, the temporary support substrate is a flexible film. Brève description des dessins

[0015] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1A illustrates a step in a manufacturing process for an integrated photonic device according to one embodiment; the figure 1B illustrates another step in a manufacturing process for an integrated photonic device according to one embodiment; the figure 1C illustrates another step in a manufacturing process for an integrated photonic device according to one embodiment; the figure 1D illustrates another step in a manufacturing process for an integrated photonic device according to one embodiment; the figure 1E illustrates another step in a manufacturing process for an integrated photonic device according to one embodiment; the figure 1F illustrates another step in a manufacturing process for an integrated photonic device according to one embodiment; and the figure 1G illustrates another step in a manufacturing process for an integrated photonic device according to one embodiment. Description des modes de réalisation

[0016] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0017] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, the various active or passive components that may be included in the photonic devices produced by the described processes have not been detailed, as the described embodiments are compatible with all or most of the common components of integrated photonic devices.

[0018] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0019] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0020] THE figures 1A à 1G are cross-sectional views schematically and partially illustrating steps in an example of an embodiment of a manufacturing process for an integrated photonic device.

[0021] For the sake of simplicity, we have represented on the figures 1A à 1G the realization of a single photonic device. In practice, a plurality of identical or similar photonic devices can be formed simultaneously in and on the same substrate, the substrate then being cut into a plurality of individual chips each containing a single photonic device.

[0022] There figure 1A This illustrates a structure obtained after the formation of a photonic circuit integrated into a first substrate 101, for example, a silicon-based substrate. The substrate 101 is, for example, a Silicon On Insulator (SOI) substrate, comprising a silicon support 101a, an insulating layer 101b, for example, of silicon oxide, disposed on and in contact with the upper surface of the support 101a, and a silicon layer 101c disposed on and in contact with the upper surface of the insulating layer 101b. The layers 101b and 101c each extend, for example, over substantially the entire surface of the support 101a. Active or passive photonic components 103 are formed in the upper silicon layer 101c of the substrate 101, forming a first photonic integrated circuit.Components 103 include, for example, waveguides, diffractive gratings, photodiodes, PN junction modulators, and / or any other photonic component that can be integrated into a SOI-type substrate. Alternatively, layer 101c may include regions of germanium or a silicon-germanium alloy, in which case components 103 may include germanium-based components.

[0023] There figure 1A It further illustrates a step subsequent to the formation of the components 103, of deposition of an insulating layer 105, for example a layer of silicon oxide, on the upper face of the substrate 101. The layer 105 extends for example continuously over the entire surface of the substrate 101. The thickness of the layer 105 is for example between 5 and 100 nm, for example between 70 and 80 nm.

[0024] There figure 1B illustrates a step of fixing, on the upper surface of a temporary support substrate 201, first vignettes 211 based on a III-V semiconductor material, and second vignettes 221 based on silicon nitride. On the figure 1B , only one vignette 211 and one vignette 221 were shown. The vignettes 211 and 221 are intended to be transferred onto the substrate 101 in order to form, above the photonic components 103 integrated into the substrate 101, photonic components based on the III-V semiconductor material, for example laser diodes, and photonic components based on silicon nitride, for example waveguides, intended to cooperate with the components 103 to form a photonic device.

[0025] The temporary support substrate 201, for example, has approximately the same surface area as the substrate 101. The arrangement of the vignettes 211 and 221 on the substrate 201 corresponds to the desired arrangement of the vignettes after transfer onto the substrate 101. As an example, one or more vignettes 211 and one or more vignettes 221 can be transferred to each photonic integrated circuit formed in the substrate 101. Each vignette 211 or 221 can have, in top view, a minimum dimension of between 1 and 10 mm, for example, between 1 and 5 mm. As an example, in top view, each vignette 211 or 221 has a surface area of ​​between 1 and 25 mm².

[0026] The vignettes 211 are formed by epitaxy from a growth substrate 213. Each vignette can comprise a stack consisting of, in order from the top face (in the orientation of the figure 1B ) of the substrate 213, a semiconductor layer 215a of a III-V material doped with a first type of conductivity, for example type P, an active layer 215b, and a semiconductor layer 215c of a III-V material doped with a second type of conductivity, for example type N. As an example, the substrate 213 and the semiconductor layers 215a and 215c are made of indium phosphide (InP). The active layer 215b may include confinement means corresponding to multiple quantum wells (a succession of quantum wells and barriers, surrounded by SCH confinement layers, from the English "Separate Confinement Heterostructure").For example, the active layer 215b comprises alternating layers of a first III-V material and layers of a second III-V material, each layer of the first material sandwiched between two layers of the second material, the first material having a narrower band gap than the second material. For example, the active layer 215b is disposed on and in contact with the top face of the layer 215a, and the layer 215c is disposed on and in contact with the top face of the active layer 215b. Each vignette 211 may further comprise a stack 217 of one or more buffer layers interfacing between the top face of the substrate 213 and the bottom face of the layer 215a.In the example shown, the stack 217 comprises, in order from the top face of the substrate 213, a first semiconductor layer 217a disposed on and in contact with the top face of the substrate 213, a second semiconductor layer 217b disposed on and in contact with the top face of layer 217a, and a third semiconductor layer 217c disposed on and in contact with the top face of layer 217b. In this example, the top face of layer 217c is in contact with the bottom face of layer 215a. Layer 217a is intended to form a first etching stop layer during a subsequent step of removing substrate 213. Layer 217a is, for example, made of indium gallium arsenide (InGaAs). Layer 217b is intended to form a second etching stop layer during the subsequent step of removing substrate 213. Layer 217b is, for example, made of indium phosphide.Layer 217c is intended to form a third etching stop layer and a re-establishment layer for electrical contact with layer 215a. Layer 217c is, for example, made of P-doped indium gallium arsenide. In this example, each vignette 211 further includes an insulating layer 219, for example, made of the same material as layer 105, disposed on the upper surface of the semiconductor layer 215c, for example, in contact with the upper surface of layer 215c. The thickness of layer 219 is, for example, between 5 and 50 nm, or for example, between 10 and 20 nm.

[0027] For example, layers 217a, 217b, 217c, 215a, 215b, and 215c are formed successively by epitaxy on the upper surface of the growth substrate 213, before the substrate 213 is cut into individual vignettes. Each of the layers 217a, 217b, 217c, 215a, 215b, and 215c extends, for example, continuously and to a substantially uniform thickness over the entire upper surface of the substrate 213. The insulating layer 219 can then be deposited on the upper surface of the semiconductor layer 215c. Layer 219 is deposited, for example, so as to have a substantially constant thickness over the entire upper surface of substrate 213. The stack comprising substrate 213 and layers 217a, 217b, 217c, 215a, 215b, 215c and 219 can then be cut into a plurality of individual vignettes 211.

[0028] After cutting, each vignette 211 can be fixed to the temporary substrate 201 by the face of the substrate 213 opposite layers 217a, 217b, 217c, 215a, 215b, 215c and 219, i.e. by the lower face of the substrate 213 in the orientation of the figure 1B .

[0029] The vignettes 221 are formed from a deposition substrate 223, for example silicon. Each vignette 221 comprises a silicon nitride layer 225 disposed on the upper face (in the orientation of the figure 1B ) of the deposition substrate 223. The thickness of the layer 225 is, for example, between 50 nm and 2000 nm. Each vignette 221 may further include a dielectric layer 227, for example of silicon oxide, interfacing between the substrate 223 and the silicon nitride layer 225. By way of example, the layer 227 is in contact, on its lower face, with the upper face of the substrate 213, and, on its upper face, with the lower face of the layer 225. The thickness of the layer 227 is, for example, between 100 nm and 2500 nm. In this example, each vignette 221 further includes an insulating layer 229, for example of the same material as layer 105, disposed on the upper face of layer 225, for example in contact with the upper face of layer 225. The thickness of layer 229 is for example between 5 and 50 nm, for example between 10 and 20 nm.

[0030] Layers 227, 225, and 229 are deposited successively on the upper surface of the deposition substrate 223, before the substrate 223 is cut into individual vignettes. Each of the layers 227, 225, and 229 extends, for example, continuously and to a substantially uniform thickness over the entire upper surface of the substrate 223. Preferably, layer 225 is formed by a low-pressure chemical vapor deposition (LPCVD) process, for example, at a temperature of around 800°C. Such a process makes it possible to obtain a stoichiometric Si3N4 layer, which is particularly advantageous for the formation of photonic components. The stack comprising the substrate 223 and layers 227, 225, and 229 can then be cut into a plurality of vignettes 221.

[0031] After cutting, each vignette 221 can be fixed to the temporary substrate 201 by the face of the substrate 223 opposite to the layers 227, 225 and 229, that is to say by the lower face of the substrate 223 in the orientation of the figure 1B .

[0032] The attachment of the vignettes 211 and 221 to the temporary substrate 201 can be achieved by means of an adhesive layer (not shown) placed on the side of the upper face of the substrate 201.

[0033] For example, vignettes 211 and 213 are placed successively on the temporary substrate 201 using a pick and place tool.

[0034] There figure 1C illustrates a step of transferring and fixing labels 211 and 221 onto substrate 101. During this step, labels 211 and 221 are transferred and fixed collectively (i.e., simultaneously) onto substrate 101. Temporary substrate 201 (not visible in the figure 1C ) is used as a support handle for positioning the vignettes opposite the photonic circuits integrated into the substrate 101. Each of the vignettes 211 and 221 is fixed to the substrate 101 by its face opposite the temporary substrate 201. On the figure 1C , the orientation of substrate 101 is the same as on the figure 1A , but the orientation of thumbnails 211 and 221 is reversed compared to the figure 1B .

[0035] In this example, each vignette 211 is attached to the substrate 101 by direct bonding or molecular bonding of the lower face of layer 219 to the upper face of layer 105. Furthermore, each vignette 221 is attached to the substrate 101 by direct bonding or molecular bonding of the lower face of layer 229 to the upper face of layer 105. This bonding is made possible by the fact that vignettes 211 and 221 are transferred simultaneously to the substrate 101. Indeed, such bonding requires surface preparation of the substrate 101. This preparation includes, for example, at least one plasma activation step and one chemical-mechanical polishing (CMP) step. To implement this surface preparation, the bonding surface of the substrate 101 must be free of any vignettes.

[0036] After fixing the vignettes onto substrate 101, the temporary support substrate 201 is removed.

[0037] The thicknesses of the vignettes 211 and 221 are preferably substantially identical, so as to facilitate the gluing of the vignettes onto the substrate 101. To obtain vignettes 211 and 221 having substantially the same thickness, a step of thinning the substrate 223 on its face opposite the layer 229, and / or a step of thinning the substrate 213 on its face opposite the layer 219, may be provided before the step of cutting the vignettes.

[0038] The temporary support substrate 201 can be a relatively rigid substrate, for example, a silicon substrate. In this case, the maximum thickness difference between two vignettes is preferably less than 10 µm, so as to ensure contact between each vignette and the layer 105 coating the substrate 101. If the temporary support substrate 201 is rigid, it may have cavities (not shown) that laterally hold each vignette (one cavity per vignette) during transfer. The cavities may be shallower than the thickness of the vignettes. Alternatively, the vignettes protrude from cavities with a height between 10 and 100 µm, for example, a height of approximately 50 µm. The depth of the cavities is, for example, approximately 300 µm.

[0039] As an alternative, the temporary support substrate 201 can be a flexible film, for example, a plastic film. During transfer, a roller can be passed over the side of the film opposite the labels, so as to bring each label into contact with the layer 105 coating the substrate 101. In this case, the tolerance margin on the label thickness can be greater. Preferably, the maximum thickness difference between two labels is then less than 50 µm. It should be noted that in this variant, the further apart the labels are, the greater the thickness difference between them can be. For example, the thickness difference between two labels can be up to 50 µm between two labels separated by a distance of 8 mm or more, and preferably will not exceed 10 µm between two labels separated by a distance of approximately 400 µm.A linear rule can be defined between the spacing between two vignettes and the maximum tolerable difference between these two vignettes. As an example, this rule can be expressed as follows: δ h = 5.26 * 10 - 3 < * E + 7.89, where δ h is the maximum acceptable thickness difference between two vignettes and E is the lateral spacing between said two vignettes, for example within the range from 400 µm to 32000 µm.

[0040] There figure 1D illustrates a step subsequent to the step of postponing the figure 1C in which the vignettes 211 and 221 are simultaneously thinned by grinding, on their face opposite the substrate 101. During this step, the substrate 213 of each vignette 211 and the substrate 223 of each vignette 221 are partially removed. After the thinning step, the vignettes 211 and 221 have substantially the same thickness, for example between 20 and 80 µm, for example between 30 and 60 µm. As an alternative, this thinning step can be omitted if the vignettes have been sufficiently pre-thinned before cutting (paragraph

[0044] ), for example so as to have a thickness less than or equal to 150 µm, for example on the order of 100 µm, during the transfer step. This is particularly advantageous when the temporary support substrate 201 is a flexible film. Indeed, this helps to limit the risk of the vignettes being torn off or shifting during thinning.

[0041] There figure 1E illustrates a step subsequent to the thinning stage of the figure 1D during which the remaining substrate 223 is removed from the vignettes 221. In this example, the substrate 223 is removed by a selective wet etching process. For example, the substrate 223 is removed using a solution capable of selectively etching the substrate material 223 from the material of layer 227, for example, a solution based on tetramethylammonium hydroxide (TMAH) or nitric acid (HNO3). The etching stops at the top face of layer 227 of the vignettes 221. During this step, the substrate 213 of the vignettes 211 is preserved.

[0042] There figure 1F illustrates a step subsequent to the thinning stage of the figure 1D , during which substrate 213 is removed from vignettes 211. This step is, for example, subsequent to the step of the figure 1E of removing substrate 223 from the vignettes 221. In this example, substrate 213 is removed by a selective wet etching process. For example, in a first etching stage, substrate 213 is removed using a solution capable of selectively etching the material of substrate 213 with respect to the material of layer 217a, for example, a solution based on hydrochloric acid (HCl) and water (H₂O). A second etching stage can then be carried out using a solution capable of selectively etching the material of layer 217a with respect to the material of layer 217b, for example, a solution based on sulfuric acid (H₂SO₄), hydrogen peroxide (H₂O₂), and water (H₂O).A third etching phase can then be carried out using a solution capable of selectively etching the material of layer 217b with respect to the material of layer 217c, for example, a solution based on hydrochloric acid (HCl) and water (H₂O). The etching stops at the top surface of layer 217c.

[0043] There figure 1G Figure 230 schematically illustrates subsequent steps in the formation of photonic components 230, for example laser diodes, from figures 211, and of photonic components 240, for example waveguides, from figures 221. The fabrication of components 230 and 240 includes, in particular, steps for structuring the different materials of figures 211 and 221, for example, by lithography and etching processes. The fabrication of components 230 and 240 has not been detailed, as the described embodiments are compatible with the usual fabrication of photonic components based on III-V semiconductor materials and silicon nitride.

[0044] Once components 230 and 240 are formed, one or more encapsulation layers (not shown) can be deposited on the top surface of the structure. Conductive vias (not shown) can also be formed through the encapsulation layer to allow for the re-establishment of electrical contacts on active components of the device. The substrate 101 can then be sliced ​​into a plurality of individual chips, each containing a single heterogeneous photonic device comprising one or more components 103, one or more components 230, and one or more components 240.

[0045] One advantage of the process described in relation to the figures 1A à 1G The advantage is that it allows for the monolithic integration, within and onto the same substrate 101, of photonic components of different types. Components based on III-V materials and components based on silicon nitride are advantageously arranged on the same side of the photonic circuit previously formed in the substrate 101. Furthermore, the silicon nitride layer 225, which serves as the basis for the formation of the components 230, can advantageously be prepared by a high-temperature LPCVD process without risk of damaging the components 103 of the substrate 101. This is particularly advantageous when the components 103 include at least one PN junction with a controlled diffusion profile, for example, for the fabrication of a modulator or a photodiode.

[0046] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, although an example of a method in which vignettes of two different types are transferred onto the substrate 101 has been described above, the embodiments described in variations not included in the scope of the claims are not limited to this particular case. By way of variation, in addition to vignettes based on a III-V semiconductor material and vignettes based on silicon nitride, in an embodiment not included in the scope of the claims, vignettes of one or more other different types may be transferred onto the substrate 101 during the step of the figure 1C .

[0047] Furthermore, although an example of an embodiment in which the vignettes are first attached to the substrate 101 and then structured to form components 230, 240 has been described above, the embodiments described in variants not included in the scope of the claims are not limited to this particular case. By way of alternative, in an embodiment not included in the scope of the claims, the vignettes may be structured to form components 230, 240 before being transferred to the substrate 101. In particular, in an embodiment not included in the scope of the claims, the silicon nitride-based components 240 may be formed before cutting the vignettes, for example, by a process of the type described in the article entitled "Photonic Damascene Process for Low-Loss, High-Confinement Silicon Nitride Waveguides" by MHP Pfeiffer et al. (IEEE JSTQE vol.24, no.4, 2018).

[0048] Furthermore, although an example of a method in which vignettes of different types are transferred collectively (i.e., simultaneously) onto the upper surface of the substrate 101 has been described above, the embodiments described in variants not included in the scope of the claims are not limited to this particular case. As an alternative, in an embodiment not included in the scope of the claims, the different vignettes can be transferred successively onto the substrate 101, for example, by means of a pick-and-place tool.

Claims

1. A photonic device manufacturing method, comprising the following steps: - forming at least one first die (211) based on a III-V semiconductor material by epitaxy from a growth substrate (213), and at least one second die (221) based on silicon nitride from a deposition substrate (223), said at least one first die (211) and said at least one second die (221) being of different nature; - after dicing of the growth substrate (213) into said at least one first die (211) and of the deposition substrate (223) into said at least on second die (221), affixing said at least one first die (211) and said at least on second die (221) on a surface of a temporary support substrate (201); and - transferring simultaneously said at least one first die (211) and said at least on second die (221), by means of the temporary support substrate, onto a same surface of a photonic circuit previously formed inside and on top of a first substrate (101), the method further comprising a step of forming of photonic components (230, 240) in said at least one first (211) and at least one second (221) dies.

2. The method according to claim 1, wherein the step of forming of photonic components (230, 240) in said at least one first (211) and at least one second (221) dies is subsequent to the transfer step.

3. The method according to claim 1 or 2, further comprising, after the transfer step, a step of collective thinning of said at least one first (211) and at least one second (221) dies, by mechanical grinding from their surfaces opposite to the first substrate (101).

4. The method according to any of claims 1 to 3, further comprising, after the transfer step, a step of removal, by chemical etching, of the growth substrate (213) of said at least one first die (211), and a step of removal, by chemical etching, of the deposition substrate (223) of said at least one second die (221).

5. The method according to any of claims 1 to 4, wherein, during the transfer step, said at least one first (211) and at least one second (221) dies are fastened by molecular bonding onto said surface of the photonic circuit.

6. The method according to claim 5, wherein the molecular bonding implemented during the transfer step is a direct oxide-to-oxide bonding.

7. The method according to any of claims 1 to 6, wherein each second die (221) comprises a stoichiometric Si3N4 layer (225) deposited by LPCVD.

8. The method according to claim 7, comprising, before the transfer step, a step of local doping of the first substrate (101) for the forming of a PN junction of a component (103) of the photonic circuit.

9. The method according to any of claims 1 to 7, wherein the first substrate (101) is a substrate of silicon on insulator type.

10. The method according to any of claims 1 to 9, wherein the temporary support substrate (201) is a flexible film.