DYNAMIC COMPARATOR

Description

Domaine technique

[0001] This description relates generally to electronic circuits, and more specifically to the dynamic comparators that may be included in such electronic circuits. Technique antérieure

[0002] The role of dynamic comparators is to perform the comparison of two signals, in a manner synchronized with a signal, typically a clock signal, and to produce a binary signal whose binary state indicates the result of this comparison.

[0003] Dynamic comparators are used, for example, in successive approximation analog-to-digital converters. In such a converter, the dynamic comparator synchronously produces an output signal representing the comparison of an analog signal to a quantization threshold voltage. This allows the residual of the analog signal being digitized by the converter to be quantized at each step of the binary search for the digital code associated with the analog signal.

[0004] As an example, a successive approximation analog-to-digital converter includes a charge distribution node to which the first electrodes of a plurality of capacitances of increasing values ​​are connected. The node is loaded with the analog signal to be digitized while a given low voltage, typically zero, is applied to the second electrodes of the capacitors. Then, a high voltage is applied to the second electrode of the largest-value capacitor, and the voltage across the charge distribution node is compared, using a dynamic comparator, with a quantization voltage. If the voltage across the charge distribution node is greater than the quantization voltage, the second electrode, which was biased by the high voltage, is rebiased to the low voltage; otherwise, the high voltage remains.Then, these operations are repeated from the strongest capacitance to the weakest capacitance, until the digital code associated with the analog signal to be digitized is obtained, from the high or low biases applied to each of the second electrodes of the capacitors.

[0005] Among dynamic comparators, latched dynamic comparators are well-known. A latched dynamic comparator, for example, the latched dynamic comparator illustrated on the English Wikipedia page about comparators, typically comprises two negative feedback inverters whose outputs are initialized to a high level during a preliminary phase, and a differential pair connecting the inverters to ground. The two input transistors of the differential pair receive the two signals to be compared. Thus, the higher-value signal received by the input transistors of the differential pair induces a higher current in the corresponding inverter, resulting in a faster switching of that inverter's output to a low level, while maintaining the output of the other inverter at a high level.

[0006] However, in a dynamic latching comparator, manufacturing variations between transistors, particularly between the input transistors of the differential pair, lead to comparison errors, and therefore to quantization errors when the comparator is implemented in a successive approximation analog-to-digital converter. Furthermore, the gate-drain capacitance of each of the input transistors in the differential pair induces a load on the comparator input, which depends on the switching position of the comparator inverter associated with that transistor. This load, commonly called the kick-back effect, negatively impacts the comparator's accuracy, and thus the quantization of an analog signal when the comparator is implemented in a successive approximation analog-to-digital converter.

[0007] Among dynamic comparators, edge pursuit type dynamic comparators are also known.

[0008] There figure 1 represents an example of a front-tracking type dynamic comparator. More specifically, the figure 1 corresponds to the figure 2 from the article by M. Shim et al. entitled "Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS / s 15 b SAR ADC" and published in IEEE Journal of Solid-State Circuits, Vol. 52, No. 4, April 2017.

[0009] The article by NAYAK RAJENDRA ET AL: "Low power ring oscillator for IoT applications", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, SPRINGER NEW YORK LLC, US, vol. 93, no. 2, June 30, 2017, proposes a ring oscillator with a topology combining negative offset timing and current limiting.

[0010] The comparator of the figure 1 It is based on a basic inverting structure composed of a standard CMOS (Complementary Metal Oxide Semiconductor) inverter biased by a first N-channel MOS transistor connected between the source of the inverter's N-channel MOS transistor and a reference potential, and by a second P-channel MOS transistor connected between the source of the inverter's P-channel MOS transistor and a supply potential. The gates of these first and second transistors receive the same bias voltage, chosen from two voltages VINP and VINM compared by the comparator.By cascading two of these elementary structures and alternating the bias voltage VINP or VINM of the cascaded elementary structures, for example so that the upstream elementary structure is biased by the voltage VINP and the downstream elementary structure is biased by the voltage VINM, we observe the following four cases: . rising entry front ("E1" in figure 1 ) on the upstream elementary structure and VINP greater than VINM ("VINP > VINM" in figure 1 ): rapid descent ("F1-d" in figure 1 ) of the exit of the upstream elementary structure and rapid ascent ("F1-u" in figure 1 ) of the downstream elementary structure's output, rising inlet front on the upstream elementary structure and VINP less than VINM: slow descent of the upstream elementary structure's output and slow rise of the downstream elementary structure's output, falling inlet front ("E2" in figure 1 ) on the upstream elementary structure and VINP greater than VINM ("VINP > VINM" in figure 1 ): slow rise ("S2-u" in figure 1 ) of the exit of the upstream elementary structure and slow descent ("S2-d" in figure 1 ) of the output of the downstream elementary structure, and descending inlet front on the upstream elementary structure and VINP lower than VINM: rapid rise of the output of the upstream elementary structure and rapid descent of the output of the downstream elementary structure.

[0011] The comparator of the figure 1 comprises two branches, each containing four elementary structures. The two branches are looped back on each other by two NAND gates A and B, forming a ring structure. In one of the branches (the upper branch) figure 1 ), the elementary structures are alternately polarized by the voltages VINP then VINM, whereas it is the opposite in the other branch (the lower branch in figure 1 ). In addition, the input of each NAND gate that is not connected to the output of a branch receives a START synchronization signal.

[0012] The operation of this comparator is as follows. Initially, the START signal is low, resulting in a high output for each gate A and B, and a high output for each branch, including the comparator's COMP output. The transition of the START signal to a high state, i.e., a rising edge on the START signal, causes the output of each gate A and B to go low. This means that a falling edge is provided to the comparator's ring structure by each of gates A and B. These two edges propagate at different speeds within the ring, depending on the bias voltages VINP and VINM. The two edges then propagate within the ring (arrows 11 in figure 1 ) of the comparator until the fast edge reaches, or catches up with, the slow edge, resulting in a stabilization of the outputs of the elementary structures of both branches, the outputs of gates A and B, and the COMP output of the comparator. For example, in the configuration of the figure 1 The COMP output stabilizes at a high level when the VINP voltage is greater than the VINM voltage, and at a low level when the VINP voltage is less than the VINM voltage.

[0013] In a front-tracking comparator, the sequence of transitions on the two branches tends to average out the bounce effect. This reduces the negative influence of this bounce effect compared to a dynamic locking comparator. Similarly, comparison errors induced by manufacturing variations, as well as temporal noise, are reduced compared to a dynamic locking comparator. More precisely, the greater the number of elementary structures per branch, the more these comparison errors and temporal noise are smoothed out.

[0014] However, one drawback of the comparator of the figure 1 The problem is that the stabilization time of its ring, and therefore of its COMP output, increases as the difference between the VINP and VINM voltages being compared decreases. This increase in stabilization time is undesirable, particularly because it leads to increased power consumption. Résumé de l'invention

[0015] There is a need to address all or part of the drawbacks of known dynamic comparators.

[0016] For example, there is a need to overcome all or part of the drawbacks of known front-tracking type dynamic comparators.

[0017] One implementation overcomes all or part of the drawbacks of known dynamic comparators.

[0018] For example, one embodiment overcomes all or part of the drawbacks of known front-tracking type dynamic comparators.

[0019] One embodiment provides a dynamic comparator of a first voltage and a second voltage, of the edge-tracking type, comprising a ring of logic gates in series, in which: Each gate in the ring includes a first input connected to an output of the previous gate in the ring; each gate in the ring is configured to implement an inverter function between its first input and its output; at least one of said gates in the ring is controllable and is associated with another of said gates in the ring; each controllable gate includes a control input connected to the output of the gate associated with said controllable gate; each controllable gate is configured to prevent its output from switching to a high state when its control input is high, and to a low state when its control input is low; the control input of each controllable gate is configured to receive the state of the output of the gate associated with said controllable gate if an even number of gates in the ring separates the controllable gate from said associated gate, and to receive the complementary state of said output otherwise;and the logic gates of the ring are even in number.

[0020] According to one embodiment, each controllable door is separated from the door associated with the controllable door by at least one of said ring doors.

[0021] According to one embodiment, the number of ring doors separating each controllable door from the door associated with said controllable door is strictly less than half the total number of ring doors minus one.

[0022] According to one embodiment: said gates of the ring comprise a first logic gate, a second logic gate and third and fourth logic gates; a first branch of the ring comprises an alternation of third and fourth gates in series between the output of the first gate and the first input of the second gate, the first branch beginning with a third gate; a second branch of the ring comprises an alternation of third and fourth gates in series between the output of the second gate and the first input of the first gate, the second branch beginning with a fourth gate;and each of the third and fourth gates is biased from the first voltage and / or the second voltage, the biasing of the third gates being complementary to that of the fourth gates, the biasing of each of the third and fourth gates determining a switching speed of the output of said gate in the high state and a switching speed of the output of said gate in the low state.

[0023] According to one embodiment, each branch has the same number of third gates and each branch has the same number of fourth gates.

[0024] According to one embodiment: Each of the third and fourth gates includes a first bias node and a second bias node, for example coincident with the first node, a voltage on the first node determining the switching speed of the output of said gate in the high state and a voltage on the second node determining the switching speed of the output of said gate in the low state; the first nodes of the third gates are configured to receive the first voltage or the second voltage, the first nodes of the fourth gates being configured to receive the second voltage when the first nodes of the third gates receive the first voltage, or the first voltage when the first nodes of the third gates receive the second voltage;and the second nodes of the third gates are configured to receive either the first or second voltage, the second nodes of the fourth gates being configured to receive the second voltage when the second nodes of the third gates receive the first voltage, or the first voltage when the second nodes of the third gates receive the second voltage.

[0025] In one embodiment, each controllable gate comprises a first MOSFET connecting the output of the controllable gate to a high-potential application node. The first MOSFET has its gate connected to the control input of the controllable gate and is configured, in its off state, to electrically isolate the output of the controllable gate from the high-potential application node. The controllable gate further comprises a second MOSFET connecting the output of the gate to a low-potential application node. The second MOSFET has its gate connected to the control input of the controllable gate and is configured, in its off state, to electrically isolate the output of the controllable gate from the low-potential application node.

[0026] According to one embodiment, each of the third and fourth gates comprises: at least one first MOS transistor configured to switch the output of said gate to the high state when the first input of said gate receives a falling edge, said at least one first transistor being biased from the voltage on the first node of said gate; and at least one second MOS transistor configured to switch the output of said gate to the low state when the first input of said gate receives a rising edge, said at least one second transistor being biased from the voltage on the second node of said gate.

[0027] According to one embodiment, each of the third and fourth gates comprises a single first transistor and a single second transistor.

[0028] According to one embodiment, in each of the third and fourth doors: said at least one first transistor is in series with a transistor having a gate connected to the first node of said gate and said at least one second transistor is in series with another transistor having a gate connected to the second node of said gate; or said at least one first transistor and said at least one second transistor are implemented on silicon on insulator, for example completely depleted, a back gate of each first transistor being connected to the first node of said gate and a back gate of each second transistor being connected to the second node of said gate.

[0029] According to one embodiment, each controllable gate is one of the third and fourth gates and further comprises a third MOS transistor configured, in the blocked state, to electrically isolate the output of said controllable gate from a node applying a supply voltage, and a fourth MOS transistor configured, in the blocked state, to electrically isolate the output of said controllable gate from a node applying a reference voltage, a gate of each of the third and fourth transistors being connected to the control input of said controllable gate.

[0030] According to one embodiment, the first and second branches are symmetrical.

[0031] According to one embodiment, each of the first and second gates further includes a second input configured to receive a synchronization signal, the implementation of the inverting function between the first input and the output of said gate being conditioned by the state of the synchronization signal.

[0032] According to one embodiment, for each controllable door, the door associated with said controllable door is the first door or one of the third and fourth doors of the first branch when said controllable door belongs to the first branch, and is the second door or one of the third and fourth doors of the second branch when said controllable door belongs to the second branch.

[0033] One embodiment provides for an analog-to-digital converter including a comparator as described. Brève description des dessins

[0034] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1 The previously described dynamic comparator represents an example of a front-tracking type; figure 2 represents, schematically and in block form, an embodiment of a front-tracking type dynamic comparator; the figure 3 represents, schematically, one embodiment of a gate of the dynamic comparator of the figure 2 ; there figure 4 represents, schematically, a variant implementation of a gate of the dynamic comparator of the figure 2 ; and the figure 5 represents, schematically, one embodiment of another gate of the dynamic comparator of the figure 2 . Description des modes de réalisation

[0035] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0036] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, common electronic circuits in which a dynamic comparator is implemented have not been detailed, as the described embodiments are compatible with these common circuits.

[0037] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0038] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0039] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0040] In the following description, within a ring of a dynamic edge-tracking comparator, a first logic gate is considered to precede, or be upstream of, a second logic gate when an edge propagating through the ring is first propagated by, or through, the first gate and then by, or through, the second gate. Conversely, a first logic gate is further considered to follow, or be downstream of, a second logic gate when an edge propagating through the ring is first propagated by, or through, the second gate and then by, or through, the first gate. In other words, the terms "upstream," "downstream," "previous," and "next" applied to gates in the ring are defined with respect to the direction of edge propagation through the ring.

[0041] In the following description, a front, or binary transition, can have two different directions, namely rising and falling. A rising front, or falling front, will more generally be called a rising front, or falling front, respectively.

[0042] In the following description, a logic gate is defined as a purely combinational gate, or circuit, that is, one without a memory function. Preferably, the logic gates described here are implemented using CMOS technology (Complementary Metal Oxide Semiconductor).

[0043] This application proposes a dynamic edge-chasing comparator in which at least one of the logic gates in the comparator ring branches is driven by an output of an upstream, or preceding, gate of the ring, and is configured to block the propagation of the slowest edge when the output of that upstream gate switches following the propagation of the fastest edge. Because the upstream gate and the gate driven by the output of the upstream gate are separated from each other by at least one other logic gate of the ring, this reduces the ring settling time, and therefore the comparator's power consumption.

[0044] There figure 2 represents, schematically and in block form, an embodiment of such a comparator 2. The comparator 2 is configured to compare a voltage V+ with a voltage V-.

[0045] Comparator 2 includes a ring. The ring contains several logic gates in series. More specifically, each gate in the ring has an input 100 connected to an output 102 of the previous gate in the ring. Each gate in the ring is configured to implement an inverter function between its input 100 and its output 102.

[0046] According to one embodiment, the ring gates comprise a logic gate 106, a logic gate 108, logic gates 110A, and logic gates 110B. The ring comprises a branch 112 (delimited by dashed lines in figure 2 ) and branch 114 (delimited by dotted lines in figure 2 ). Branches 112 and 114 are looped back onto each other by gates 106 and 108.

[0047] According to this embodiment, branch 112 comprises an alternation of gates 110A and 110B between its input 1121 and its output 1122. Branch 112 begins with a gate 110A, or, in other words, the input 1121 of branch 112 corresponds to the input 100 of a gate 110A. Furthermore, branch 114 comprises an alternation of gates 110A and 110B between its input 1141 and its output 1142. Branch 114 begins with a gate 110B, or, in other words, the input 1141 of branch 114 corresponds to the input 100 of a gate 110B. Each gate 110A, 110B is biased from the voltage V+ and / or the voltage V-. The biasing, from one and / or the other of the voltages V+ and V-, of each gate 110A, 110B determines a switching speed of the output 102 of the gate to the high state and a switching speed of the output 102 of the gate to the low state.More specifically, each 110A gate is biased from one or both of the V+ and V- voltages in a way that complements the way each 110B gate is biased from one or both of these V+ and V- voltages. Thus, when the V+ and V- voltages are different, the switching speeds in the low and high states of the 110A gates are different from the switching speeds in the low and high states of the 110B gates.

[0048] In one embodiment, each gate 110A, 110B comprises a bias node 120 and a bias node 122. The switching speed to the high state of the output 102 of each gate 110A, 110B is determined by a voltage across node 120 of the gate in question, while the switching speed to the low state of the output 102 of each gate 110A, 110B is determined by a voltage across node 122 of the gate in question. The complementary biasing between gates 110A and 110B is then implemented as follows. The 120 nodes of the 110A gates are configured to receive the voltage V+ or V-, and the 120 nodes of the 110B gates are configured to receive the voltage V+ when the 120 nodes of the 110A gates receive the voltage V-, or to receive the voltage V- when the 120 nodes of the 110A gates receive the voltage V+.In addition, the 122 nodes of the 110A gates are configured to receive the voltage V+ or V-, and the 122 nodes of the 110B gates are configured to receive the voltage V+ when the 122 nodes of the 110A gates receive the voltage V-, or to receive the voltage V- when the 122 nodes of the 110A gates receive the voltage V+.

[0049] In the implementation of the figure 2 Nodes 120 and 122 of each gate 110A receive the same voltage V+, while nodes 120 and 122 of each gate 110B receive the same voltage V-. In this case, as shown in figure 2 Nodes 120 and 122 can be considered equivalent. In an alternative embodiment not shown, node 120 of each gate 110A receives the voltage V+, node 120 of each gate 110B receives the voltage V-, node 122 of each gate 110A receives the voltage V-, and node 122 of each gate 110B receives the voltage V+. However, the embodiment where each gate receives the same voltage on both its nodes 120 and 122 is preferred because it allows comparator 2 to stabilize more quickly for a given difference between the voltages V+ and V-.

[0050] According to one embodiment, branch 112 comprises as many 110A gates as branch 114, and as many 110B gates as branch 114. Preferably, each branch 112, 114 of the ring comprises the same even number of 110A, 110B gates.

[0051] The ring comprises an even number of logic gates 110A, 110B, 106 and 108. Due to the inverter function implemented by each gate 110A, 110B, 106 and 108, between its input 100 and its output 102, when edges propagate in the ring, the ring stabilizes when the fastest edge catches up with the slowest edge.

[0052] An OUT output of comparator 2 is available on output 1122 of branch 112 or on output 1142 of branch 114.

[0053] Among gates 106, 108, 110A, 110B, preferably among gates 110A and 110B of the ring, one or more gates are controllable. In the example of the figure 2 , branch 112 of the ring includes a controllable gate 110B, referenced as 110B' in the rest of the description, and branch 114 of the ring includes a controllable gate 110A, referenced as 110A' in the rest of the description. More specifically, in the example of the figure 2 Gate 110B' of branch 112 is the last gate of the branch, or, in other words, the output of gate 110B' of branch 112 corresponds to output 1122 of branch 112, and gate 110A' of branch 114 is the last gate of the branch, or, in other words, the output of gate 110A' of branch 114 corresponds to output 1142 of branch 114. However, the described embodiments are not limited to this example. For example, one of branches 112, 114, or each of branches 112 and 114 may include more than one controllable gate, or one of the two branches 112 and 114 may have no controllable gate. In addition, the number and / or position of controllable doors in branch 112 may be different from the number and / or position of controllable doors in branch 114.However, in preferred embodiments, when a controllable gate is located at a given position in branch 112 and is separated from its associated control gate by a given number of gates, branch 114 includes a controllable gate at the same position in branch 114. This controllable gate in branch 114 is separated from its associated control gate by the same given number of gates. This results in a comparator in which the comparator's settling, or response, time is substantially the same when the voltage V+ is greater than the voltage V-, with a given difference between the voltages V+ and V-, and when the voltage V+ is less than the voltage V-, with the same given difference between these voltages V+ and V-.

[0054] In the following description, unless otherwise indicated, the expression "gates 110A" and "gates 110B" respectively refer to all gates 110A and 110B respectively in the ring, including any controllable gates 110A' and 110B' respectively. Furthermore, although not illustrated here, each gate 106 and 108 may be a controllable gate as described above.

[0055] Each controllable gate in the ring is associated with another gate in the ring, preferably located upstream of the controllable gate in the ring. More specifically, each controllable gate 110A', 110B' includes a control input 116 connected to the output 102 of the gate to which that controllable gate is associated. In the example of the figure 2 The input 116 of the controllable gate 110B' of branch 112 is connected to the output 102 of the first gate of branch 112, namely gate 110A. The input 116 of the controllable gate 110A' of branch 114 is connected to the output 102 of the first gate of branch 114, namely gate 110B. However, the described embodiments are not limited to this example, and a controllable gate of a branch can be associated with a gate that is not the first gate of that branch. Furthermore, a controllable gate 110A' or 110B' can be associated with, or controlled by, a gate 106 or 108.

[0056] According to one embodiment, each controllable door 110A', 110B' is separated from the door associated with that controllable door by one or more other doors of the ring.

[0057] According to one embodiment, the number of doors separating each controllable door 110A', 110B' from the door to which that controllable door is associated is strictly less than half the total number of doors in the ring, reduced by one. In the example of the figure 2 where each branch 112, 114 comprises two gates 110A and two gates 110B, and where the total number of gates in the ring is ten, a maximum of three gates in the ring separate each controllable gate 110A', 110B' from the gate to which it is associated. The number of gates separating a controllable gate 110A', 110B' and the gate that controls it—that is, the number of gates arranged between the input 100 of this controllable gate 110A', 110B' and the output 102 of the gate that controls it—is counted following the direction of propagation of the edges in the ring, starting from the output 102 of the gate associated with the controllable gate. Thus, in the example of the figure 2 The controllable gate 110B' of branch 112 is separated from the gate 110A that controls it by two gates, namely successively a gate 110B and a gate 110A going from the output 102 of the gate 110A that controls the gate 110B' to the input of the controllable gate 110B'. Similarly, in the example of the figure 2 , the controllable door 110A' of branch 114 is separated from the door 110B which controls it by two doors, namely successively a door 110A and a door 110B going from the exit 102 of the door 110B which controls the door 110A' to the entrance of the controllable door 110A'.

[0058] According to one embodiment, the door associated with each controllable door of branch 112, respectively 114, belongs to this branch 112, respectively 114, or corresponds to door 106, respectively 108.

[0059] In one embodiment, branches 112 and 114 are symmetrical. In other words, for each position in branch 112, the gate at that position is identical to the gate at the same position in the opposite branch 114, except, where applicable, for the voltage V+ and / or the voltage V- received at nodes 120 and 122 of these gates. In particular, when a controllable gate is located at a given position in branch 112 and is separated from its associated control gate by a given number of gates, branch 114 preferably includes a controllable gate at the same position in branch 114, this controllable gate in branch 114 being preferably separated from its associated control gate by the same given number of gates.

[0060] According to one embodiment, all non-controllable gates 110A, 110B are identical, except, where applicable, for the voltage V+ and / or the voltage V- received on the nodes 120 and 122 of these gates, and all controllable gates 110A', 110B' are identical, except, where applicable, for the voltage V+ and / or the voltage V- received on the nodes 120 and 122 of these gates.

[0061] Each controllable gate 110A', 110B' is configured to prevent its output 102 from switching to the high state when its input 116 is in the high state, and to prevent its output 102 from switching to the low state when its input 116 is in the low state.

[0062] In one embodiment, each controllable gate 110A', 110B' comprises a first MOS transistor connecting the output 102 of the controllable gate to a high potential application node, for example, a high supply potential. This first transistor has its gate connected to the control input 116 of the controllable gate and is configured, in the off state, to electrically isolate the output 102 of the controllable gate from the high potential application node. Symmetrically, each controllable gate 110A', 110B' further comprises a second MOS transistor connecting the output 102 of the gate to a low potential application node, for example, a low supply potential. This second transistor has its gate connected to the control input 116 of the controllable gate and is configured, in the off state, to electrically isolate the output 102 of the controllable gate from the low potential application node.In other words, the first MOS transistor is configured in the off state to prevent switching to a high state of output 102 of the controllable gate. This first MOS transistor is configured to be off when the control input 116 of the controllable gate is high. Symmetrically, the second MOS transistor is configured in the off state to prevent switching to a low state of output 102 of the controllable gate. This second MOS transistor is configured to be off when the control input 116 of the controllable gate is low. One advantage of this embodiment is that, regardless of the state of the control input 116 and the state of the input 100 of a controllable gate, there is no cross-conductivity in the controllable gate.Of course, this embodiment applies when the gate 106 or 108 is controllable, the latter then comprising the first and second transistors described above, which allows that, whatever the state of the control input 116, the input 100 and the input 118 of this controllable gate, there is no cross-conducting in the controllable gate.

[0063] Input 116 of each controllable door 110A', 110B' is configured to receive the state, high or low, of output 102 of the door to which that controllable door is associated when the number of doors in the ring separating the controllable door and its associated door is even. In other words, in this case, input 116 of the controllable door is connected to output 102 of its associated door. Furthermore, input 116 of each controllable door 110A', 110B' is configured to receive the complementary state of output 102 of the door to which that controllable door is associated, namely high if output 102 is low and low if output 102 is high, when the number of doors in the ring separating the controllable door and its associated door is odd.In other words, in this case, the input 116 of the controllable gate is connected to the output 102 of its associated gate by an odd number of inverters, preferably a single inverter. As before, the number of gates separating a controllable gate and the gate that controls it—that is, the number of gates arranged between the input 100 of this controllable gate 110A', 110B' and the output 102 of the gate to which the controllable gate is associated—is counted following the direction of propagation of the edges in the ring, starting from the output 102 of the gate associated with the controllable gate.

[0064] In comparator 2, each gate 106, 108 includes an input 118 configured to receive a synchronization signal, for example, a clock signal, clk. Each gate 106, 108 is configured so that the inverting function implemented between its input 100 and its output 102 is conditional upon the state of the synchronization signal clk. For example, this inverting function is only implemented if the signal at the gate's input 118 is in a given high or low state.

[0065] For example, gates 106 and 108 are each implemented by a NAND gate. In this case, the inverting function between input 100 and output 102 of the gate is only implemented if the clk signal is high. Indeed, if the clk signal is low, output 102 of the gate is necessarily high, regardless of the state of input 100 of the gate.

[0066] In another example, gates 106 and 108 are each implemented as a NOR gate. In this case, the inverting function between input 100 and output 102 of the gate is only implemented if the clk signal is low. Indeed, if the clk signal is high, output 102 of the gate is necessarily low, regardless of the state of input 100 of the gate.

[0067] The operation of comparator 2 is as follows. In this example, gates 106 and 108 are each implemented by a NAND gate. Initially, the signal clk is low, which means that the output 102 of each gate 106 and 108 is high and no edge, or transition, propagates through the ring. The output of each branch 112, 114 is then high in the example illustrated by the figure 2 At a later instant, the signal clk switches to the high state, resulting in a falling edge at the output 102 of each gate 106, 108. These two edges then propagate through the ring at speeds that depend on the difference between the voltage V+ and the voltage V-. At a later instant, the edge that propagates most slowly through the ring is located between a controllable gate and the associated gate that controls it, for example, between the first gate 110A of branch 112 and gate 110B' of branch 112. Furthermore, at this instant, gate 110A, which controls the controllable gate 110B' of branch 112, receives the fastest edge, and its output switches, for example, to the low state. In the example of the figure 2 Where an even number of gates separate gate 110B' from the gate 100A that controls it, this prevents the switching of output 102 of controllable gate 110B' to a low state. At a later time, the slowest edge occurs at input 100 of controllable gate 110B' on branch 112; this slow edge is a rising edge in this example. Since input 116 of controllable gate 110B' on branch 112 is low, output 102 of this gate 110B' cannot switch to a low state, and its state, which is high in this example, remains unchanged. The slow edge is therefore blocked at input 100 of this controllable gate 110B'. At a later moment, the fastest edge appears on the input 100 of the controllable gate 110B' of the branch 112, the fast edge being a falling edge in the example considered, and therefore catches up with the slow edge.Because the output 102 of the gate 110B' is already high, this does not change the state of this output 102. As a result, the propagation of edges in the ring is stopped, the ring stabilizes and the result of the comparison of the voltage V+ with the voltage V- is given by the state of the OUT signal.

[0068] There figure 3 represents, schematically, an embodiment of a non-controllable 110A gate of comparator 2 of the figure 2 In this embodiment, all non-controllable doors 110A and 110B are, for example, implemented in the same way as door 110A of the figure 3 , by adapting the voltage(s) received by nodes 120 and 122 of gates 110B relative to those received by nodes 120 and 122 of gates 110A.

[0069] The 110A gate includes at least one MOS 300 transistor, preferably P-channel, connecting the gate output 102 to a node 301 for applying a supply potential Vcc. figure 3 The transistor 300, or the set of transistors 300 when the gate includes several transistors 300, is schematically represented as a block 302. As an example, when the gate includes several MOS transistors 300, these transistors are associated in series and / or in parallel between a node 3021 connected, for example connected, to the output 102, and a node 3022 connected to the node 301.

[0070] The 110A gate further includes at least one MOS transistor 303, preferably N-channel, connecting the gate output 102 to a node 304 for applying a reference potential, for example ground (GND). figure 3 The transistor 303, or the set of transistors 303 when the gate 108 includes several transistors 303, is schematically represented as a block 305. As an example, when the gate 108 includes several MOS transistors 303, these transistors are associated in series and / or in parallel between a node 3051 connected, for example connected, to the output 102, and a node 3052 connected to the node 304.

[0071] The transistor(s) 300 are configured to switch the output 102 of gate 110A to the high state (Vcc) when the input 100 of gate 110A receives a falling edge, that is, a transition from the high state (Vcc) to the low state (GND). Similarly, the transistor(s) 303 are configured to switch the output 102 of gate 110A to the low state (GND) when the input 100 of gate 110A receives a rising edge, that is, a transition from the low state (GND) to the high state (Vcc). For example, each transistor 300, 303 has its gate connected to the input 100 of the gate.

[0072] The transistor(s) 300 are biased by the voltage present at node 120 of the gate, therefore the switching speed to high of the gate's output 102 depends on this voltage. Furthermore, the transistor(s) 303 are biased by the voltage present at node 122 of the gate, therefore the switching speed to low of the gate's output 102 depends on this voltage.

[0073] In the embodiment illustrated by the figure 3 The 110A gate further includes a MOS transistor 306, preferably P-channel, and a MOS transistor 307, preferably N-channel. The transistor 306, respectively 307, is configured to implement the biasing of the transistor(s) 300, respectively 303, from the voltage on the node 120, respectively 122. The gate of the transistor 306 is connected to the node 120, the gate of the transistor 307 being connected to the node 122.

[0074] More specifically, transistor 306 is in series with transistor 300, or all 300 transistors as appropriate, between output 102 and node 301 of the gate, transistor 307 being in series with transistor 303, or all 303 transistors as appropriate, between output 102 and node 304.

[0075] In the example of the figure 3 Transistor 306 connects block 302 to node 301, and transistor 307 connects block 305 to node 304. For example, transistor 306 has one conduction terminal, for example its source, connected, preferably connected, to node 301, and another conduction terminal, for example its drain, connected, preferably connected, to node 3022. Similarly, transistor 307 has, for example, one conduction terminal, for example its source, connected, preferably connected, to node 304, and another conduction terminal, for example its drain, connected, preferably connected, to node 3052. In another example not shown, transistor 306 connects gate output 102 to block 302 and / or the transistor connects output 102 to block 305.

[0076] According to one embodiment, the gate 110A comprises a single transistor 300 and a single transistor 303. In this case, one conduction terminal, for example the source, of transistor 300 is connected, preferably connected, to node 3022, another conduction terminal, for example the drain, of transistor 300 is connected, preferably connected, to node 3021, one conduction terminal, for example the source, of transistor 303 is connected, preferably connected, to node 3052, and another conduction terminal, for example the drain, of transistor 303 is connected, preferably connected, to node 3051.

[0077] In one embodiment, the gate 110A comprises several transistors 300, for example two transistors 300, connected in parallel between nodes 3022 and 3021 and / or several transistors 303, for example two transistors 303, connected in series between nodes 3051 and 3052.

[0078] As an example, the transistors of gate 110A are implemented on a bulk semiconductor substrate. As another example, the transistors of gate 110A are implemented on a semiconductor-on-insulator (SOI) structure or a fully-depleted semiconductor-on-insulator (FDSOI) structure.

[0079] There figure 4 represents, schematically, a variant embodiment of the non-controllable 110A door of the figure 3 In this embodiment, all non-controllable doors 110A and 110B are, for example, implemented in the same way as door 110A of the figure 4 , by adapting the voltage(s) received by nodes 120 and 122 of gates 110B relative to those received by nodes 120 and 122 of gates 110A.

[0080] Door 110A of the figure 4 includes many elements in common with the 110A door of the figure 3 and only the differences between these two doors are highlighted here.

[0081] More specifically, door 110A of the figure 4 differs from that of the figure 3 only by the way in which the transistor(s) 300 are biased from the voltage present on node 120 of the gate, and the way in which the transistor(s) 303 are biased from the voltage present on node 122 of the gate.

[0082] In this variant, transistors 300 and 303 are implemented from an SOI structure, preferably from an FDSOI structure.

[0083] Because transistors 300 and 303 are implemented in SOI or FDSOI configurations, each of these transistors has a back gate in addition to its front gate. The back gate of each transistor 300 and 303 is then connected to the bias node 120 and 122, respectively.

[0084] Because the voltage present on the back gate of transistors 300 and the voltage present on the back gate of transistors 303 modify the conduction threshold of these transistors, the switching speed to the high state of output 102 of gate 110A depends on the voltage on node 120 and the switching speed to the low state of output 102 of gate 110A depends on the voltage on node 122.

[0085] Thus, in this embodiment, transistors 306 and 307 described in relation to the figure 3 can be omitted, the 110A gate of the figure 4 being then more compact than the 110A door described in relation to the figure 3 However, it will be possible to combine the alternative implementation of the figure 4 and the method of implementation of the figure 3 , that is to say, to provide that the 110A gate includes transistors 306 and 307 described in relation to the figure 3 and that transistors 300 and 303 of this 110A gate have their back gates connected to nodes 120 and 122 as described in relation to the figure 4 .

[0086] When transistors 306 and 307 are omitted, as is the case for example in figure 4 , node 3022 is, for example, connected to node 301, node 3052 being, for example, connected to node 304.

[0087] There figure 5 represents, schematically, an embodiment of a 110A' gate controllable by comparator 2 of the figure 2 In this embodiment, all controllable doors 110A', 110B' are implemented in the same way as door 110A' of the figure 5 .

[0088] Gate 110A' of the figure 5 includes many elements in common with the 110A door of the figure 3 and only the differences between these two doors are highlighted here.

[0089] More specifically, door 110A' of the figure 5 differs from the 110A gate of the figure 3 in that it further comprises input 116, a MOS transistor 400, preferably P-channel, and a MOS transistor 402, preferably N-channel. The transistor 400, respectively 402, corresponds to the first transistor, respectively the second transistor, mentioned in connection with the figure 2 , it being understood that the terms first and second are used here only to distinguish these two transistors which could have, for example, also been named third transistor and fourth transistor respectively.

[0090] The gate (front) of transistor 400 is connected to the control input 116 of the gate. In its off state, transistor 400 electrically isolates the output 102 of gate 110A' from node 301. For example, transistor 300, or all 300 transistors if applicable, transistor 306, and transistor 400 are in series between output 102 and node 301. In the example shown by the figure 5 The transistor 400 connects the node 3021 to the output 102, the transistor 400 then having one conduction terminal, for example its source, connected, preferably connected, to the node 3021, and another conduction terminal, for example its drain, connected, preferably connected, to the output 102. In other examples not shown, the transistor 400 is still in series with the block 302, but is arranged between the block 302 and the transistor 306, or between the transistor 306 and the node 301.

[0091] Transistor 402, like transistor 400, has its gate (front) connected to input 116 of gate 110A'. In a complementary fashion to transistor 400, transistor 402 is configured, in its off state, to electrically isolate output 102 of gate 110A' from node 304. For example, transistor 303, or all 303 transistors if applicable, transistor 307, and transistor 402 are in series between output 102 and node 304. In the example illustrated by the figure 5 , transistor 402 connects node 3051 to output 102, transistor 402 then having one conduction terminal, for example its source, connected, preferably connected, to node 3051, and another conduction terminal, for example its drain, connected, preferably connected, to output 102. In other examples not shown, transistor 402 is still in series with block 305, but is placed between block 305 and transistor 307, or between transistor 307 and node 304.

[0092] Thus, when a slow falling edge, or rising edge respectively, reaches input 100 of the controllable gate 110A', and a fast edge received by input 100 of the ring gate that controls gate 110A' has already switched input 116 of gate 110A' to the high, or low, state, transistor 400, or 402 respectively, is in the blocked state. As a result, output 102 of gate 110A' is isolated from node 301, or 304 respectively, and remains held in the low, or high, state. The slow edge is therefore blocked at input 100 of gate 110A' until the fast rising, or falling, edge catches up with the slow edge at input 100 of the gate.

[0093] We have described above, in relation to the figure 5 , an embodiment of a controllable gate 110A' in which transistor(s) 300, 303 respectively, are biased from the voltage on node 120, 122 respectively, via transistor 306, 307 respectively. In an alternative embodiment not shown, similar to the embodiment described in relation to the figure 4 Each transistor 300, or 303 respectively, is implemented on SOI or FDSOI and includes a back gate connected to node 120, or 122 respectively. In such a variant, transistors 306 and 307 can be omitted. However, this embodiment may be combined with the embodiment of the figure 5 , that is to say, to provide that the 110A' gate includes transistors 306 and 307 described in relation to the figure 5 and that transistors 300 and 303 of this gate 110A' have their rear gates connected to nodes 120 and 122 as described in relation to the figure 4 .

[0094] For example, in the case where: comparator 2 is identical to the one shown in figure 2 , the doors 110A, 110B, 110A', 110B' are implemented in the manner described in relation to the figures 3 et 5 , each gate 110A, 110B, 110A', 110B' comprises only one 300 transistor and one 302 transistor, and gates 104 and 106 are NAND gates, The inventors observed a fuel consumption saving of approximately 30% compared to the comparator shown in figure 1 Furthermore, when comparator 2 according to this example is implemented in a successive approximation analog-to-digital converter, for example as a replacement for the comparator shown in figure 1 This has little to no impact on the conversion error.

[0095] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0096] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

1. A dynamic comparator (2) of a first voltage (V+) with a second voltage (V-), of the edge pursuit type, comprising a ring of logic gates (110A, 110B, 110A', 110B', 106, 108) in series, wherein: each gate of the ring comprises a first input (100) connected to an output (102) of the preceding gate of the ring; each gate of the ring is configured to implement an inverting function between its first input (100) and its output (102); the logic gates (110A, 110B, 110A', 110B', 106, 108) of the ring are even in number; characterized in that: at least one (110A', 110B') of said gates of the ring is controllable and is associated with another one of said gates of the ring; each controllable gate (110A', 110B') comprises a control input (116) coupled to the output (102) of the gate associated with said controllable gate; each controllable gate (110A', 110B') is configured to prevent switching of its output (102) to a high state when its control input (116) is in the high state, and to a low state when its control input (116) is in the low state; the control input (116) of each controllable gate (110A', 110B') is configured to receive the state of the output (102) of the gate associated with said controllable gate if an even number of gates (110A, 110B, 110A', 110B', 106, 108) of the ring separates the controllable gate (110A', 110B') from said associated gate, and to receive the complementary state of said output if not.

2. The comparator according to claim 1, wherein each controllable gate (110A', 110B') is separated from the gate associated with the controllable gate by at least one of said gates (110A, 110B, 110A', 110B', 106, 108) of the ring.

3. The comparator according to claim 1 or 2, wherein a number of gates (110A, 110B, 110A', 110B', 106, 108) of the ring separating each controllable gate (110A', 110B') from the gate associated with said controllable gate is strictly less than half the total number of gates of the ring minus one.

4. The comparator according to any one of claims 1 to 3, wherein: said gates (110A, 110B, 110A', 110B', 106, 108) of the ring comprise a first logic gate (106), a second logic gate (108), and third (110A, 110A') and fourth (110B, 110B') logic gates; a first branch (112) of the ring comprises alternating third (110A, 110A') and fourth (110B, 110B') gates in series between the output (102) of the first gate (106) and the first input (100) of the second gate (108), the first branch (112) beginning with a third gate (110A); a second branch (114) of the ring comprises alternating third (110A, 110A') and fourth (110B, 110B') gates in series between the output (102) of the second (108) gate and the first input (102) of the first gate (106), the second branch (114) beginning with a fourth gate (110B); and each of the third and fourth gates (110A, 110A', 110B, 110B') is polarized from the first voltage (V+) and / or from the second voltage (V-), the polarization of the third gates (110A, 110A') being complementary to that of the fourth gates (110B, 110B'), the polarization of each of the third and fourth gates (110A, 110A', 110B, 110B') determining a switching speed of the output (102) of said gate to the high state and a switching speed of the output (102) of said gate to the low state.

5. The comparator according to claim 4, wherein each branch (112, 114) includes a same number of third gates (110A, 110A') and each branch (112, 114) includes a same number of fourth gates (110B, 110B').

6. The comparator according to claim 4 or 5, wherein: each of the third (110A, 110A') and fourth (110B, 110B') gates comprises a first polarization node (120) and a second polarization node (122), for example combined with the first node, a voltage (V+, V-) on the first node determining the switching speed of the output (102) of said gate to the high state and a voltage (V+, V-) on the second node (122) determining the switching speed of the output (102) of said gate to the low state; the first nodes (120) of the third gates (110A, 110A') are configured to receive the first voltage (V+) or the second voltage (V-), the first nodes (120) of the fourth gates (110B, 110B') being configured to receive the second voltage (V-) when the first nodes (120) of the third gates (110A, 110A') receive the first voltage (V+), or the first voltage (V+) when the first nodes (120) of the third gates (110A, 110A') receive the second voltage (V-); and the second nodes (122) of the third gates (110A, 110A') are configured to receive the first voltage (V+) or the second voltage (V-), the second nodes (122) of the fourth gates (110B, 110B') being configured to receive the second voltage (V-) when the second nodes (122) of the third gates (110A, 110A') receive the first voltage (V+), or the first voltage (V+) when the second nodes (122) of the third gates (110A, 110A') receive the second voltage (V-).

7. The comparator according to any one of claims 1 to 6, wherein each controllable gate (110A', 110B') comprises: - a first MOS transistor (400) connecting the output (102) of the controllable gate (110A', 110B') to a node (301) for applying a high potential (Vdd), the first transistor (400) having a gate connected to the control input (116) of the controllable gate (110A', 110B') and being configured, in the off state, to electrically isolate the output (102) of the controllable gate (110A', 110B') from the node (301) for applying the high potential (Vdd); and - a second MOS transistor (402) connecting the output of the gate to a node (304) for applying a low potential (GND), the second transistor (402) having a gate connected to the control input (116) of the controllable gate (110A', 110B') and being configured, in the off state, to electrically isolate the output (102) of the controllable gate (110A', 110B') from the node (304) for applying the low potential (GND).

8. The comparator according to claim 6 wherein each of the third (110A, 110A') and fourth (110B, 110B') gates comprises: at least one first MOS transistor (300) configured to switch the output of said gate to the high state when the first input (100) of said gate receives a falling edge, said at least one first transistor (300) being polarized from the voltage (V+; V-) on the first node (120) of said gate; and at least one second MOS transistor (303) configured to switch the output (102) of said gate to the low state when the first input (100) of said gate receives a rising edge, said at least one second transistor (303) being polarized from the voltage (V+; V-) on the second node (122) of said gate.

9. The comparator according to claim 8, wherein each of the third and fourth gates (110A, 110A', 110B, 110B') comprises a single first transistor (300) and a single second transistor (303).

10. The comparator according to claim 8 or 9, wherein, in each of the third and fourth gates (110A, 110A', 110B, 110B'): said at least one first transistor (300) is in series with a transistor (306) having a gate connected to the first node (120) of said gate and said at least one second transistor (303) is in series with another transistor (307) having a gate connected to the second node (122) of said gate; or said at least one first transistor (300) and said at least one second transistor (303) are implemented on silicon on insulator, for example completely depleted, a back gate of each first transistor (300) being connected to the first node (120) of said gate and a back gate of each second transistor (303) being connected to the second node (122) of said gate.

11. The comparator according to any one of claims 8 to 10, wherein each controllable gate (110A', 110B') is one of the third and fourth gates (110A, 110A', 110B, 110B') and further comprises a third MOS transistor (400) configured, in the off state, to electrically isolate the output (102) of said controllable gate (110A', 110B') from a node (301) for applying a supply voltage (Vcc), and a fourth MOS transistor (402) configured, in the off state, to electrically isolate the output (102) of said controllable gate (110A', 110B') from a node (304) for applying a reference voltage (GND), a gate of each of the third (400) and fourth (402) transistors being connected to the control input (116) of said controllable gate (110A', 110B').

12. The comparator according to any one of claims 5 to 11, wherein the first and second branches (112, 114) are symmetrical.

13. The comparator according to any one of claims 5 to 12, wherein each of the first (106) and second (108) gates further comprises a second input (118) configured to receive a synchronization signal (clk), the implementation of the inverting function between the first input (100) and the output (102) of said gate being conditioned by the state of the synchronization signal (clk).

14. The comparator according to any one of claims 5 to 13, wherein, for each controllable gate (110A', 110B'), the gate associated with said controllable gate is the first gate (106) or one of the third and fourth gates (110A, 110B) of the first branch (112) when said controllable gate (110B') belongs to the first branch (112), and is the second gate (108) or one of the third and fourth gates (110A, 110B) of the second branch (114) when said controllable gate (110A') belongs to the second branch (114).

15. An analog-digital converter comprising a comparator according to any one of claims 1 to 14.