A comparator circuit with a wide common-mode input range

Abstract

This invention discloses a comparator circuit with a wide common-mode input range. By combining a common-gate differential pair and an auxiliary differential pair, a wide common-mode input range from ground voltage to voltages higher than the power supply voltage is achieved. When the common-mode voltage is low, only the auxiliary differential pair operates; when the common-mode voltage is in the middle range, both differential pairs operate simultaneously to obtain maximum gain; when the common-mode voltage is high, only the common-gate differential pair operates. This design solves the problem of limited common-mode input range in traditional comparators.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to comparator circuits with a wide common-mode input range. Background Technology

[0002] As a core functional module in analog integrated circuits, the comparator compares the magnitudes of two input analog signals and outputs a logic level (high or low) to reflect the magnitude relationship between the inputs. In modern electronic systems, comparators play a crucial role and are widely used in switching power supplies, various sensor interfaces, high-speed analog-to-digital converters, and data communication, among other fields. Their performance directly affects the stability, accuracy, and efficiency of the entire system.

[0003] For a long time, to meet the ever-increasing performance demands, those skilled in the art have continuously dedicated themselves to optimizing comparator design. For example, patent documents CN104753505 B, US9178503B2, and CN 110995123B all disclose a mainstream comparator architecture, which typically employs a cascaded multi-stage MOSFET amplifier circuit. The core idea of ​​this design scheme is to effectively suppress the impact of offset voltage from subsequent amplifier stages and even the output stage on overall performance by setting a high-gain amplification stage at the front end of the comparator. This cascaded structure can achieve high comparison accuracy and response speed with relatively small power consumption and chip area budgets, and was once an effective way to solve technical problems at the time, powerfully promoting the development of analog integrated circuit technology.

[0004] However, with the continuous evolution of semiconductor technology and the expanding application boundaries of integrated circuits, the inherent limitations of the aforementioned traditional comparator structure have begun to emerge when dealing with increasingly complex and demanding working environments.

[0005] When the input common-mode level is too high or too low, the input differential pair will leave the saturation region and enter the linear or cutoff region, causing a decrease in the circuit's amplification function or even loss of proper function. In the aforementioned literature, because the input differential pair is powered by the power supply, the comparator's common-mode input range is limited by the comparator's power supply voltage and ground voltage. This causes the circuit to fail in some wide input range applications, thus greatly limiting its application potential in fields with strict requirements for wide voltage range and high reliability, such as industrial control, automotive electronics, and battery management systems.

[0006] Therefore, how to effectively expand the common-mode input range of comparators while maintaining their inherent advantages such as high precision and high speed, so as to adapt to a wider range of more demanding application scenarios, has become a key challenge and a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to address the above-mentioned problems by proposing a comparator circuit with a wide common-mode input range. This invention introduces multiple differential pairs in the comparator input stage and combines them with bias control to ensure continuous, stable and high-gain operation of the comparator circuit throughout the extended common-mode input range, thereby effectively widening its common-mode input range.

[0008] The technical solution of this invention is:

[0009] The present invention provides a comparator circuit with a wide common-mode input range, the comparator circuit including an input stage and multiple cascaded secondary amplifier circuits;

[0010] The input stage includes a common-gate differential pair and an auxiliary differential pair for receiving the input signal and generating a differential output signal to the secondary amplifier circuit; wherein the common-gate differential pair and the auxiliary differential pair of the input stage are configured to extend the common-mode input range;

[0011] The secondary amplifier circuit is used to amplify the signal output from the input stage and generate the comparator's output signal.

[0012] Furthermore, in the common-gate differential pair and auxiliary differential pair of the input stage;

[0013] The common-gate differential pair includes PMOS transistors M1-M4; the sources of PMOS transistors M1 and M2 are respectively connected to the positive input terminal INP of the analog input signal, the drain of PMOS transistor M1 is connected to the load R1 and the positive output node OUT1P, the gates of PMOS transistors M1 and M2 are connected to the drain of M2 and are coupled to a first bias current source Ibiasn, thereby providing effective input stage gain; the sources of PMOS transistors M3 and M4 are respectively connected to the negative input terminal INM of the analog input signal, the drain of PMOS transistor M4 is connected to the load R2 and the negative output node OUT1N, the gates of PMOS transistors M3 and M4 are connected to the drain of M3 and are coupled to a first bias current source Ibiasn, thereby providing effective input stage gain;

[0014] Among them, PMOS transistors M1 and M4 mirror the current of PMOS transistors M2 and M3 at a preset ratio to fix the total bias current of the common gate differential pair and improve the input stage gain; at the same time, the first bias current source Ibiasn provides bias current for PMOS transistors M2 and M3.

[0015] The auxiliary differential pair includes PMOS transistors M5 and M6, which are connected at a common source and biased by a second bias current source Ibiasp. The gates of PMOS transistors M5 and M6 are connected in series with resistors R3 and R4, respectively, and then connected to the positive input terminal INP and the negative input terminal INM of the corresponding analog input signal. The drain of PMOS transistor M5 is connected to the load R1 and the output node OUT1P, and the drain of PMOS transistor M6 is connected to the load R2 and the output node OUT1N.

[0016] Furthermore, in the input stage, the voltage drop of the first bias current source Ibiasn of the common-gate differential pair is Vbiasn, the voltage drop of the second bias current source Ibiasp of the auxiliary differential pair is Vbiasp, and the turn-on voltage of the PMOS is Vgsp; the first threshold of the input common-mode voltage corresponding to the common-gate differential pair is Vbiasn+Vgsp, the second threshold of the input common-mode voltage corresponding to the auxiliary differential pair is VDD-Vbiasp-Vgsp, and the common-gate differential pair and the auxiliary differential pair dynamically switch the turn-on state according to the input common-mode voltage.

[0017] Furthermore, the common-gate differential pair and the auxiliary differential pair dynamically switch their on / off states according to the input common-mode voltage, including: when the input common-mode voltage is lower than a first threshold, the auxiliary differential pair is in the saturation region and the common-gate differential pair is in the off region; when the input common-mode voltage is between the first threshold and a second threshold, both the common-gate differential pair and the auxiliary differential pair are on and in the saturation region; when the input common-mode voltage is higher than the second threshold, the common-gate differential pair is in the saturation region and the auxiliary differential pair is in the off region; the common-gate differential pair and the auxiliary differential pair dynamically switch their on / off states according to the input common-mode voltage, thereby achieving an ultra-wide common-mode input range with a minimum level to ground and a maximum level higher than the supply voltage.

[0018] Furthermore, the drain currents of the common-gate differential pair and the auxiliary differential pair are linearly superimposed on the load and converted into a voltage signal through the load, serving as the output signal of the input stage. Specifically, the drain currents of the PMOS transistors M5 and M1 are superimposed on the load R1, which converts the superimposed current into a positive output voltage, output from the output node OUT1P to the secondary amplifier circuit; the drain currents of the PMOS transistors M6 and M4 are superimposed on the load R2, which converts the superimposed current into a negative output voltage, output from the output node OUT1N to the secondary amplifier circuit; the gains of the common-gate differential pair and the auxiliary differential pair are linearly added in the form of current, ensuring that the total gain of the input stage remains stable across the entire input range.

[0019] Furthermore, the secondary amplifier circuit includes:

[0020] The first-stage amplifier, used to pre-amplify the input differential signal, includes PMOS transistors M7-M8, resistors R5 and R6, and a bias current source Ibiasp1. The gates of PMOS transistors M7 and M8 serve as the input terminals of the first-stage amplifier, connected to the positive and negative output nodes OUT1P and OUT1N, respectively. PMOS transistors M7 and M8 are connected to a common source and are biased by the bias current source Ibiasp1. The drains of PMOS transistors M7 and M8 are connected to ground via resistors R5 and R6, respectively. Simultaneously, the connection points between the drains of PMOS transistors M7 and M8 and resistors R5 and R6 serve as the positive and negative output terminals of the first-stage amplifier, connected to the corresponding input terminals of the second-stage amplifier.

[0021] The second-stage amplifier converts a small-amplitude differential input signal into a large-amplitude differential output signal, reducing the comparator's delay. It includes NMOS transistors M11-M14, PMOS transistors M15 and M16, and a bias current source Ibiasp2. The gates of PMOS transistors M15 and M16 serve as the input terminals of the second-stage amplifier, connected to the positive and negative output terminals of the first-stage amplifier, respectively. PMOS transistors M15 and M16 are connected via a common source and are biased by the bias current source Ibiasp2. The drain of PMOS transistor M15... The drain of the PMOS transistor M16 is connected to the drain and gate of NMOS transistor M11 and the drain of M13. The drain of the PMOS transistor M16 is connected to the drain and gate of NMOS transistor M14 and the drain of M12. NMOS transistors M11 and M12 are connected to a common gate, and M13 and M14 are connected to a common gate. The gates of NMOS transistors M11 and M12 are connected at a point. The sources of NMOS transistors M11-M14 are all grounded. The drains of PMOS transistors M15 and M16 serve as the positive and negative output terminals of the second-stage amplifier, respectively, and are connected to the corresponding input terminals of the third-stage amplifier.

[0022] The third-stage amplifier is used to convert a large-amplitude differential output signal into a single-ended output signal with increased amplitude. It includes PMOS transistors M19 and M20, and NMOS transistors M18 and M21-M23. The gates of NMOS transistors M18 and M21 are connected to the positive and negative outputs of the second-stage amplifier, respectively, as the input terminals of the third-stage amplifier. The drain of NMOS transistor M18 is connected to the drain and gate of PMOS transistor M19, and the drain of M21 is connected to the drain of M20 and the gates of M22 and M23. PMOS transistors M19 and M20 are connected with a common gate. The sources of PMOS transistors M19, M20, and M22 are connected to the power supply VDD, and the sources of M18, M21, and M23 are grounded. NMOS transistors M22 and M23 are connected with a common drain, and the drain connection point serves as the output of the third-stage amplifier, i.e., the output terminal OUT of the comparator circuit.

[0023] Furthermore, in the common-gate differential pair and auxiliary differential pair of the input stage;

[0024] The common-gate differential pair includes NMOS transistors M1'-M4'; the sources of NMOS transistors M1' and M2' are respectively connected to the positive input terminal INP' of the analog input signal, the drain of NMOS transistor M1' is connected to the load R1' and the positive output node OUT1P', and the gates of NMOS transistors M1' and M2' and the drain of M2' are connected together and coupled to a first bias current source Ibiasp', thereby providing effective input stage gain; the sources of NMOS transistors M3' and M4' are respectively connected to the negative input terminal INM' of the analog input signal, the drain of NMOS transistor M4' is connected to the load R2' and the negative output node OUT1N', and the gates of NMOS transistors M3' and M4' and the drain of M3' are connected together and coupled to a first bias current source Ibiasp', thereby providing effective input stage gain;

[0025] Among them, NMOS transistors M1' and M4' mirror the current of NMOS transistors M2' and M3' at a preset ratio to fix the total bias current of the common gate differential pair and improve the input stage gain; at the same time, the first bias current source Ibiasp' provides bias current for NMOS transistors M2' and M3'.

[0026] The auxiliary differential pair includes NMOS transistors M5' and M6', which are connected at a common source and biased by a second bias current source Ibiasn'. The gates of NMOS transistors M5' and M6' are connected in series with resistors R3' and R4', respectively, and then connected to the positive input terminal INP' and negative input terminal INM' of the corresponding analog input signals. The drain of NMOS transistor M5' is connected to the load R1' and the output node OUT1P', and the drain of NMOS transistor M6' is connected to the load R2' and the output node OUT1N'.

[0027] Furthermore, in the input stage, the voltage drop of the first bias current source Ibiasp' of the common-gate differential pair is Vbiasp', the voltage drop of the second bias current source Ibiasn' of the auxiliary differential pair is Vbiasn', and the turn-on voltage of the NMOS is Vgsn'; the first threshold of the input common-mode voltage corresponding to the common-gate differential pair is VDD'-Vbiasp'-Vgsn', and the second threshold of the input common-mode voltage corresponding to the auxiliary differential pair is Vbiasn'+Vgsn'. The common-gate differential pair and the auxiliary differential pair dynamically switch their turn-on states according to the input common-mode voltage.

[0028] Furthermore, the common-gate differential pair and the auxiliary differential pair dynamically switch their on / off states according to the input common-mode voltage, including: when the input common-mode voltage is higher than a first threshold, the auxiliary differential pair is in the saturation region and the common-gate differential pair is in the off region; when the input common-mode voltage is between the first threshold and a second threshold, both the common-gate differential pair and the auxiliary differential pair are on and in the saturation region; when the input common-mode voltage is lower than the second threshold, the common-gate differential pair is in the saturation region and the auxiliary differential pair is in the off region; the common-gate differential pair and the auxiliary differential pair dynamically switch their on / off states according to the input common-mode voltage, thereby achieving an ultra-wide common-mode input range from the supply voltage to below ground level.

[0029] Furthermore, the drain currents of the common-gate differential pair and the auxiliary differential pair are linearly superimposed on the load and converted into a voltage signal by the load, serving as the output signal of the input stage. Specifically, the drain currents of the NMOS transistors M5' and M1' are superimposed on the load R1', which converts the superimposed current into a positive output voltage, output from the output node OUT1P' to the secondary amplifier circuit; the drain currents of the NMOS transistors M6' and M4' are superimposed on the load R2', which converts the superimposed current into a negative output voltage, output from the output node OUT1N' to the secondary amplifier circuit. The gains of the common-gate differential pair and the auxiliary differential pair are linearly added in the form of current, ensuring that the total gain of the input stage remains stable across the entire input range.

[0030] Furthermore, the secondary amplifier circuit includes:

[0031] The first-stage amplifier, used to pre-amplify the input differential signal, includes NMOS transistors M7'-M8', resistors R5' and R6', and a bias current source Ibiasn1'. The gates of NMOS transistors M7' and M8' serve as the input terminals of the first-stage amplifier, connected to the positive and negative output nodes OUT1P' and OUT1N', respectively. NMOS transistors M7' and M8' are connected to a common source and are biased by the bias current source Ibiasp1'. The drains of NMOS transistors M7' and M8' are connected in series with resistors R5' and R6' and then grounded. Simultaneously, the connection points between the drains of NMOS transistors M7' and M8' and resistors R5' and R6' serve as the positive and negative output terminals of the first-stage amplifier, connected to the corresponding input terminals of the second-stage amplifier.

[0032] The second-stage amplifier converts a small-amplitude differential input signal into a large-amplitude differential output signal, reducing the comparator's delay. It includes PMOS transistors M11'-M14', NMOS transistors M15' and M16', and a bias current source Ibiasp2'. The gates of NMOS transistors M15' and M16' serve as the input terminals of the second-stage amplifier, connected to the positive and negative output terminals of the first-stage amplifier, respectively. NMOS transistors M15' and M16' are connected to a common source and are biased by the bias current source Ibiasp2'. The drain of NMOS transistor M15' is connected to... The drain and gate of PMOS transistor M11' and the drain of M13' are connected together. The drain of NMOS transistor M16' is connected to the drain and gate of PMOS transistor M14' and the drain of M12'. PMOS transistors M11' and M12' are connected to a common gate, and M13' and M14' are connected to a common gate. The gates of PMOS transistors M11' and M12' are connected at a point. The sources of PMOS transistors M11'-M14' are all grounded. The drains of NMOS transistors M15' and M16' serve as the positive and negative output terminals of the second-stage amplifier, respectively, and are connected to the corresponding input terminals of the third-stage amplifier.

[0033] The third-stage amplifier is used to convert a large-amplitude differential output signal into a single-ended output signal with increased amplitude. It includes NMOS transistors M19' and M20', and PMOS transistors M18' and M21'-M23'. The gates of PMOS transistors M18' and M21' serve as the input terminals of the third-stage amplifier, connected to the positive and negative output terminals of the second-stage amplifier, respectively. The drain of PMOS transistor M18' is connected to the drain and gate of NMOS transistor M19'. The drain of transistor 21' is connected to the drain of transistor M20' and the gates of transistors M22' and M23'. The NMOS transistors M19' and M20' are connected to a common gate. The sources of the NMOS transistors M19', M20', and M22' are connected to the power supply VDD'. The sources of transistors M18', M21', and M23' are grounded. The PMOS transistors M22' and M23' are connected to a common drain, and the drain connection point serves as the output of the third-stage amplifier, i.e., the output terminal OUT' of the comparator circuit.

[0034] The beneficial effects of this invention are:

[0035] This invention discloses a comparator circuit with a wide common-mode input range. By combining a common-gate differential pair and an auxiliary differential pair, a wide common-mode input range from ground voltage to voltages higher than the power supply voltage is achieved. When the common-mode voltage is low, only the auxiliary differential pair operates; when the common-mode voltage is in the intermediate range, both differential pairs operate simultaneously to obtain maximum gain; when the common-mode voltage is high, only the common-gate differential pair operates. This design solves the problem of limited common-mode input range in traditional comparators.

[0036] This invention discloses a comparator circuit with a wide common-mode input range. By combining a common-gate differential pair and an auxiliary differential pair, a wide common-mode input range from below ground voltage to the power supply voltage is achieved. When the common-mode voltage is high, only the auxiliary differential pair operates; when the common-mode voltage is in the middle range, both differential pairs operate simultaneously to obtain maximum gain; when the common-mode voltage is low, only the common-gate differential pair operates. This design solves the problem of limited common-mode input range in traditional comparators.

[0037] The present invention also employs a secondary amplification and single-ended conversion circuit to convert the differential signal into a full-swing single-ended output, and then shapes it with an inverter to obtain the final output signal. This design significantly expands the operating range of the comparator, improves the applicability and reliability of the circuit, and is particularly suitable for application scenarios that require processing a wide range of input signals.

[0038] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0039] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0040] Figure 1 A block diagram of the comparator principle with a wide common-mode input range according to the present invention is shown.

[0041] Figure 2 One of the input stage circuit diagrams of the comparator with a wide common-mode input range according to the present invention is shown.

[0042] Figure 3 One of the circuit diagrams of the comparator with a wide common-mode input range according to the present invention is shown.

[0043] Figure 4 Out Figure 3 A schematic diagram showing the relationship between the differential gain of the comparator input stage and the input common-mode gain.

[0044] Figure 5 Out Figure 3 A schematic diagram showing the variation of the output common-mode voltage of the comparator input stage with the input common-mode voltage.

[0045] Figure 6 The second diagram shows the input stage circuit of the comparator with a wide common-mode input range according to the present invention.

[0046] Figure 7 A second circuit diagram of the comparator with a wide common-mode input range of the present invention is shown.

[0047] Figure 8 Out Figure 7A schematic diagram showing the relationship between the differential gain of the comparator input stage and the input common-mode gain.

[0048] Figure 9 Out Figure 7 A schematic diagram showing the variation of the output common-mode voltage of the comparator input stage with the input common-mode voltage. Detailed Implementation

[0049] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0050] Figure 1 A block diagram of the comparator principle with a wide common-mode input range according to the present invention is shown.

[0051] like Figure 1 As shown, the present invention provides a comparator circuit with a wide common-mode input range, the comparator circuit including an input stage and multiple cascaded secondary amplifier circuits;

[0052] The input stage includes a common-gate differential pair and an auxiliary differential pair for receiving the input signal and generating a differential output signal to the secondary amplifier circuit; wherein the common-gate differential pair and the auxiliary differential pair of the input stage are configured to extend the common-mode input range;

[0053] The secondary amplifier circuit is used to amplify the signal output from the input stage and generate the comparator's output signal.

[0054] In one example, the input stage of the comparator is connected across an equivalent resistor to detect the current I flowing through it. The equivalent resistor can be the on-resistance of a MOSFET, a real poly resistor, etc. A proportional adjustment module can be connected in series between the equivalent resistor and the comparator to amplify the bias current by a certain factor to obtain the desired threshold current. The equivalent resistor is connected to the input stage of a wide input range comparator via the proportional amplification module, or directly to the input stage. A wide input range comparator consists of multiple cascaded secondary amplifier circuits at the input stage.

[0055] Example 1

[0056] Figure 2 One of the input stage circuit diagrams of the comparator with a wide common-mode input range according to the present invention is shown.

[0057] Figure 3 One of the circuit diagrams of the comparator with a wide common-mode input range according to the present invention is shown.

[0058] like Figure 2 , 3As shown, in the input stage, the common-gate differential pair and the auxiliary differential pair; the common-gate differential pair includes PMOS transistors M1-M4; the sources of PMOS transistors M1 and M2 are respectively connected to the positive input terminal INP of the analog input signal, the drain of PMOS transistor M1 is connected to the load R1 and the positive output node OUT1P, the gates of PMOS transistors M1 and M2 and the drain of M2 are connected together and coupled to a first bias current source Ibiasn, thereby providing effective input stage gain; the sources of PMOS transistors M3 and M4 are respectively connected to the negative input terminal INM of the analog input signal, the drain of PMOS transistor M4 is connected to the load R2 and the negative output node OUT1N, the gates of PMOS transistors M3 and M4 and the drain of M3 are connected together and coupled to a first bias current source Ibiasn, thereby providing effective input stage gain;

[0059] In this configuration, PMOS transistors M1 and M4 mirror the current of PMOS transistors M2 and M3 at a preset ratio to fix the total bias current of the common gate differential pair and improve the input stage gain. Simultaneously, the first bias current source Ibiasn provides bias current to PMOS transistors M2 and M3. The preset ratio is the device size ratio of PMOS transistors M1 and M2, which is the same as the device size ratio of PMOS transistors M4 and M3.

[0060] The auxiliary differential pair includes PMOS transistors M5 and M6, which are connected at a common source and biased by a second bias current source Ibiasp. The gates of PMOS transistors M5 and M6 are connected in series with resistors R3 and R4, respectively, and then connected to the positive input terminal INP and the negative input terminal INM of the corresponding analog input signal. The drain of PMOS transistor M5 is connected to the load R1 and the output node OUT1P, and the drain of PMOS transistor M6 is connected to the load R2 and the output node OUT1N.

[0061] Furthermore, the drain currents of the common-gate differential pair and the auxiliary differential pair are linearly superimposed on the load and converted into a voltage signal through the load, serving as the output signal of the input stage. Specifically, the drain currents of PMOS transistors M5 and M1 are superimposed on the load R1, which converts the superimposed current into a positive output voltage, output from the output node OUT1P to the secondary amplifier circuit; the drain currents of PMOS transistors M6 and M4 are superimposed on the load R2, which converts the superimposed current into a negative output voltage, output from the output node OUT1N to the secondary amplifier circuit; the gains of the common-gate differential pair and the auxiliary differential pair are linearly added in the form of current, ensuring that the total gain of the input stage remains stable across the entire input range.

[0062] In this circuit, R1 and R2 are loads, which can be actual resistors or implemented using MOSFETs. The two differential pairs convert the input voltage change into a drain current change, which is then superimposed in phase at nodes OUT1N and OUT1P; R1 and R2 then convert the change into a voltage change, which serves as the output of this stage.

[0063] like Figure 3 As shown, the secondary amplifier circuit includes:

[0064] The first-stage amplifier, used to pre-amplify the input differential signal, includes PMOS transistors M7-M8, resistors R5 and R6, and a bias current source Ibiasp1. The gates of PMOS transistors M7 and M8 serve as the input terminals of the first-stage amplifier, connected to the positive and negative output nodes OUT1P and OUT1N, respectively. PMOS transistors M7 and M8 are connected to a common source and are biased by the bias current source Ibiasp1. The drains of PMOS transistors M7 and M8 are connected to ground via resistors R5 and R6, respectively. Simultaneously, the connection points between the drains of PMOS transistors M7 and M8 and resistors R5 and R6 serve as the positive and negative output terminals of the first-stage amplifier, connected to the corresponding input terminals of the second-stage amplifier.

[0065] The second-stage amplifier converts a small-amplitude differential input signal into a large-amplitude differential output signal, reducing the comparator's delay. It includes NMOS transistors M11-M14, PMOS transistors M15 and M16, and a bias current source Ibiasp2. The gates of PMOS transistors M15 and M16 serve as the input terminals of the second-stage amplifier, connected to the positive and negative output terminals of the first-stage amplifier, respectively. PMOS transistors M15 and M16 are connected via a common source and are biased by the bias current source Ibiasp2. The drain of PMOS transistor M15... The drain of the PMOS transistor M16 is connected to the drain and gate of NMOS transistor M11 and the drain of M13. The drain of the PMOS transistor M16 is connected to the drain and gate of NMOS transistor M14 and the drain of M12. NMOS transistors M11 and M12 are connected to a common gate, and M13 and M14 are connected to a common gate. The gates of NMOS transistors M11 and M12 are connected at a point. The sources of NMOS transistors M11-M14 are all grounded. The drains of PMOS transistors M15 and M16 serve as the positive and negative output terminals of the second-stage amplifier, respectively, and are connected to the corresponding input terminals of the third-stage amplifier.

[0066] The third-stage amplifier is used to convert a large-amplitude differential output signal into a single-ended output signal with increased amplitude. It includes PMOS transistors M19 and M20, and NMOS transistors M18 and M21-M23. The gates of NMOS transistors M18 and M21 are connected to the positive and negative outputs of the second-stage amplifier, respectively, as the input terminals of the third-stage amplifier. The drain of NMOS transistor M18 is connected to the drain and gate of PMOS transistor M19, and the drain of M21 is connected to the drain of M20 and the gates of M22 and M23. PMOS transistors M19 and M20 are connected with a common gate. The sources of PMOS transistors M19, M20, and M22 are connected to the power supply VDD, and the sources of M18, M21, and M23 are grounded. NMOS transistors M22 and M23 are connected with a common drain, and the drain connection point serves as the output of the third-stage amplifier, i.e., the output terminal OUT of the comparator circuit.

[0067] In one example, for Figure 2 The differential gain of the input stage shown varies with the input common-mode gain as follows: Figure 4 As shown in the figure. A CG A is the gain of the common-gate differential pair when applied to the load alone. AUX To assist the gain of the differential pair acting alone on the load, when the input common mode is between (Vbiasn + Vgsp) and (VDD - Vbiasp - Vgsp), both differential pairs are enabled, and the gain is the sum of the two. It can be seen that the gain curve is relatively flat throughout the operating range. For example, setting A... CG =A AUX The total change in differential gain is approximately 3 dB.

[0068] for Figure 2 The input stage shown in the figure has an output common-mode voltage that varies with the input common-mode voltage as follows: Figure 5 As shown. Where k is the ratio of the dimensions of M1 to M2.

[0069] An example of a complete wide input range comparator circuit is as follows: Figure 3 As shown.

[0070] The secondary amplifier stage 1 acts as a pre-amplifier, suppressing the offset of subsequent stages and speeding up the comparison process. The maximum input common-mode of this stage is (V0). DD -Vbiasp1-Vgs7), where Vbiasp1 is the voltage drop across the current source Ibiasp1, and Vgs7 is the gate-source voltage of M7. Therefore, as long as V... DD - Vbiasp1-Vgs biasp R1 / 2+k I biasn R1 / 2 ensures the correct operating point of the circuit across all input ranges. Simultaneously, the output common-mode voltage of this stage is determined to be I. biasp1 R5 / 2, where I biasp1 ​The current source Ibiasp1 provides current, which reduces the design difficulty of subsequent stages.

[0071] Secondary amplifier 2 acts as a positive feedback comparison, using latch structure loads shown in M11~M14, which can convert the small differential signal input of the previous stage into a differential output with a large amplitude with a low delay.

[0072] Secondary amplifier 3 converts the differential input to a single-ended output and further increases the amplitude of the output signal. Meanwhile, M20 and M21 provide a certain driving capability, and M22 and M23 form an inverter, allowing the comparator output amplitude to be driven from the power supply to ground, thus ensuring that the output signal has the required driving capability.

[0073] Example 2

[0074] Figure 6 The second diagram shows the input stage circuit of the comparator with a wide common-mode input range according to the present invention.

[0075] Figure 7 A second circuit diagram of the comparator with a wide common-mode input range of the present invention is shown.

[0076] like Figure 6 , 7 As shown, when the input stage adopts an NMOS input pair structure; the common-gate differential pair includes NMOS transistors M1'-M4'; the sources of NMOS transistors M1' and M2' are respectively connected to the positive input terminal INP' of the analog input signal, and the drain of NMOS transistor M1' is connected to the load R1' and the positive output node OUT1P'. The gates and drains of NMOS transistors M1' and M2' are connected and coupled to a first bias current source Ibiasp', thereby providing effective input stage gain. The sources of NMOS transistors M3' and M4' are respectively connected to the negative input terminal INM' of the analog input signal. The drain of NMOS transistor M4' is connected to the load R2' and the negative output node OUT1N'. The gates and drains of NMOS transistors M3' and M4' are connected and coupled to a first bias current source Ibiasp', thereby providing effective input stage gain.

[0077] In this configuration, NMOS transistors M1' and M4' mirror the current of NMOS transistors M2' and M3' at a preset ratio to fix the total bias current of the common-gate differential pair and improve the input stage gain. Simultaneously, the first bias current source Ibiasp' provides bias current to NMOS transistors M2' and M3'. The preset ratio is the device size ratio of PMOS transistors M1' and M2', which is the same as the device size ratio of PMOS transistors M4' and M3'.

[0078] The auxiliary differential pair includes NMOS transistors M5' and M6', which are connected at a common source and biased by a second bias current source Ibiasn'. The gates of NMOS transistors M5' and M6' are connected in series with resistors R3' and R4', respectively, and then connected to the positive input terminal INP' and negative input terminal INM' of the corresponding analog input signals. The drain of NMOS transistor M5' is connected to the load R1' and the output node OUT1P', and the drain of NMOS transistor M6' is connected to the load R2' and the output node OUT1N'.

[0079] Furthermore, the drain currents of the common-gate differential pair and the auxiliary differential pair are linearly superimposed on the load and converted into a voltage signal by the load, serving as the output signal of the input stage. Specifically, the drain currents of the NMOS transistors M5' and M1' are superimposed on the load R1', which converts the superimposed current into a positive output voltage, output from the output node OUT1P' to the secondary amplifier circuit; the drain currents of the NMOS transistors M6' and M4' are superimposed on the load R2', which converts the superimposed current into a negative output voltage, output from the output node OUT1N' to the secondary amplifier circuit. The gains of the common-gate differential pair and the auxiliary differential pair are linearly added in the form of current, ensuring that the total gain of the input stage remains stable across the entire input range.

[0080] In this circuit, R1' and R2' are loads, which can be actual resistors or implemented using MOSFETs. The two differential pairs convert the input voltage change into a drain current change, which is superimposed in phase at nodes OUT1N' and OUT1P'; then R1' and R2' convert it into a voltage change, which serves as the output of this stage.

[0081] like Figure 7 As shown, the secondary amplifier circuit includes:

[0082] The first-stage amplifier, used to pre-amplify the input differential signal, includes NMOS transistors M7'-M8', resistors R5' and R6', and a bias current source Ibiasn1'. The gates of NMOS transistors M7' and M8' serve as the input terminals of the first-stage amplifier, connected to the positive and negative output nodes OUT1P' and OUT1N', respectively. NMOS transistors M7' and M8' are connected to a common source and are biased by the bias current source Ibiasp1'. The drains of NMOS transistors M7' and M8' are connected in series with resistors R5' and R6' and then grounded. Simultaneously, the connection points between the drains of NMOS transistors M7' and M8' and resistors R5' and R6' serve as the positive and negative output terminals of the first-stage amplifier, connected to the corresponding input terminals of the second-stage amplifier.

[0083] The second-stage amplifier converts a small-amplitude differential input signal into a large-amplitude differential output signal, reducing the comparator's delay. It includes PMOS transistors M11'-M14', NMOS transistors M15' and M16', and a bias current source Ibiasp2'. The gates of NMOS transistors M15' and M16' serve as the input terminals of the second-stage amplifier, connected to the positive and negative output terminals of the first-stage amplifier, respectively. NMOS transistors M15' and M16' are connected to a common source and are biased by the bias current source Ibiasp2'. The drain of NMOS transistor M15' is connected to... The drain and gate of PMOS transistor M11' and the drain of M13' are connected together. The drain of NMOS transistor M16' is connected to the drain and gate of PMOS transistor M14' and the drain of M12'. PMOS transistors M11' and M12' are connected to a common gate, and M13' and M14' are connected to a common gate. The gates of PMOS transistors M11' and M12' are connected at a point. The sources of PMOS transistors M11'-M14' are all grounded. The drains of NMOS transistors M15' and M16' serve as the positive and negative output terminals of the second-stage amplifier, respectively, and are connected to the corresponding input terminals of the third-stage amplifier.

[0084] The third-stage amplifier is used to convert a large-amplitude differential output signal into a single-ended output signal with increased amplitude. It includes NMOS transistors M19' and M20', and PMOS transistors M18' and M21'-M23'. The gates of PMOS transistors M18' and M21' serve as the input terminals of the third-stage amplifier, connected to the positive and negative output terminals of the second-stage amplifier, respectively. The drain of PMOS transistor M18' is connected to the drain and gate of NMOS transistor M19'. The drain of transistor 21' is connected to the drain of transistor M20' and the gates of transistors M22' and M23'. The NMOS transistors M19' and M20' are connected to a common gate. The sources of the NMOS transistors M19', M20', and M22' are connected to the power supply VDD'. The sources of transistors M18', M21', and M23' are grounded. The PMOS transistors M22' and M23' are connected to a common drain, and the drain connection point serves as the output of the third-stage amplifier, i.e., the output terminal OUT' of the comparator circuit.

[0085] In one example, for Figure 6 The differential gain of the input stage shown varies with the input common-mode gain as follows: Figure 8 As shown in the figure. A CG A is the gain of the common-gate differential pair when applied to the load alone. AUX To assist the gain of the differential pair acting alone on the load, when the input common mode is between (Vbiasn' + Vgsn') and (VDD - Vbiasp' - Vgsn'), both differential pairs are enabled, and the gain is the sum of the two. It can be seen that the gain curve is relatively flat throughout the operating range. For example, setting A... CG '=AAUX If ', then the total change in differential gain is approximately 3dB.

[0086] for Figure 2 The input stage shown in the figure has an output common-mode voltage that varies with the input common-mode voltage as follows: Figure 9 As shown in the figure. Where k' is the ratio of the dimensions of M1' to M2'.

[0087] An example of a complete wide input range comparator circuit is as follows: Figure 7 As shown.

[0088] Secondary amplifier 1 acts as a pre-amplifier, suppressing offset in subsequent stages and accelerating the comparison speed. The minimum input common-mode voltage of this stage is (Vbiasn1' + Vgs7'), where Vbiasn1' is the voltage drop across the current source Ibiasn1', and Vgs7' is the gate-source voltage of M7'. Therefore, as long as Vbiasn1' + Vgs7' is maintained... <VDD-I biasn 'R1' / 2+k I biasp R1 / 2 ensures the correct operating point of the circuit across all input ranges. Simultaneously, the output common-mode voltage of this stage is determined to be (VDD-I). biasp1 'R5' / 2), where I biasp1 The current of the current source Ibiasp1' is ', which reduces the design difficulty of the subsequent stage.

[0089] Secondary amplifier 2 acts as a positive feedback comparison, using latch structure loads shown in M11~M14, which can convert the small differential signal input of the previous stage into a differential output with a large amplitude with a low delay.

[0090] Secondary amplifier 3 converts the differential input to a single-ended output and further increases the amplitude of the output signal. Meanwhile, M20 and M21 provide a certain driving capability, and M22 and M23 form an inverter, allowing the comparator output amplitude to be driven from the power supply to ground, thus ensuring that the output signal has the required driving capability.

[0091] The above example is just one illustration; different secondary amplification modules can be used for different application scenarios. The design must comprehensively consider factors such as the area, speed, offset, and driving capability of the secondary amplification module.

[0092] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A wide common-mode input range comparator circuit, characterized by, The comparator circuit comprises an input stage and a plurality of secondary amplification circuits connected in cascade; The input stage comprises a common-gate differential pair and an auxiliary differential pair, and is configured to receive an input signal and generate a differential output signal to the secondary amplification circuits; wherein the common-gate differential pair and the auxiliary differential pair of the input stage are configured to expand the common-mode input range; when the input stage adopts a PMOS input pair structure, the common-mode input range is realized from the lowest ground level to the highest voltage higher than the supply voltage; when the input stage adopts an NMOS input pair structure, the common-mode input range is realized from the lowest voltage lower than the ground level to the highest voltage up to the supply voltage; The secondary amplification circuits are configured to amplify the signal output by the input stage and generate an output signal of the comparator; When the input stage adopts a PMOS input pair structure; the common-gate differential pair comprises PMOS transistors M1-M4; the sources of the PMOS transistors M1 and M2 are respectively connected to the positive input terminal INP of the analog input signal, the drain of the PMOS transistor M1 is connected to the load R1 and the positive output node OUT1P, the gates of the PMOS transistors M1 and M2 and the drain of the PMOS transistor M2 are connected together and are coupled to a first bias current source Ibiasn, thereby providing effective input stage gain; the sources of the PMOS transistors M3 and M4 are respectively connected to the negative input terminal INM of the analog input signal, the drain of the PMOS transistor M4 is connected to the load R2 and the negative output node OUT1N, the gates of the PMOS transistors M3 and M4 and the drain of the PMOS transistor M3 are connected together and are coupled to a first bias current source Ibiasn, thereby providing effective input stage gain; wherein the PMOS transistors M1 and M4 current mirror the PMOS transistors M2 and M3 to fix the total bias current of the common-gate differential pair and improve the input stage gain; at the same time, the PMOS transistors M2 and M3 are provided with bias current by the first bias current source Ibiasn; the auxiliary differential pair comprises PMOS transistors M5 and M6, the common sources of the PMOS transistors M5 and M6 are connected together and are provided with bias current by a second bias current source Ibiasp, the gates of the PMOS transistors M5 and M6 are respectively connected to the resistors R3 and R4 and then connected to the positive input terminal INP and the negative input terminal INM of the corresponding analog input signal; the drain of the PMOS transistor M5 is connected to the load R1 and the output node OUT1P, and the drain of the PMOS transistor M6 is connected to the load R2 and the output node OUT1N. When the input stage adopts the NMOS input pair structure, the common-gate differential pair comprises NMOS tubes M1'-M4'; the sources of the NMOS tubes M1' and M2' are respectively connected to the positive input end INP' of the analog input signal, the drain of the NMOS tube M1' is connected to the load R1' and the positive output node OUT1P', the gates of the NMOS tubes M1' and M2' and the drain of the NMOS tube M2' are connected, and are commonly coupled to a first bias current source Ibiasp', thereby providing effective input stage gain; the sources of the NMOS tubes M3' and M4' are respectively connected to the negative input end INM' of the analog input signal, the drain of the NMOS tube M4' is connected to the load R2' and the negative output node OUT1N', the gates of the NMOS tubes M3' and M4' and the drain of the NMOS tube M3' are connected, and are commonly coupled to the first bias current source Ibiasp', thereby providing effective input stage gain; wherein the NMOS tubes M1' and M4' current mirror the NMOS tubes M2' and M3' to fix the total bias current of the common-gate differential pair and improve the input stage gain; meanwhile, the NMOS tubes M2' and M3' are provided with bias current by the first bias current source Ibiasp'; the auxiliary differential pair comprises NMOS tubes M5' and M6', the common source of the NMOS tubes M5' and M6' is connected, and is provided with bias current by a second bias current source Ibiasn'; the gates of the NMOS tubes M5' and M6' are respectively connected to the positive input end INP' and the negative input end INM' of the corresponding analog input signal after being connected in series with resistors R3' and R4'; the drain of the NMOS tube M5' is connected to the load R1' and the output node OUT1P', and the drain of the NMOS tube M6' is connected to the load R2' and the output node OUT1N'.

2. The wide common-mode input range comparator circuit of claim 1, wherein When the input stage adopts the PMOS input pair structure, in the input stage, The voltage drop of the first bias current source Ibiasn of the common-gate differential pair is Vbiasn, the voltage drop of the second bias current source Ibiasp of the auxiliary differential pair is Vbiasp, and the opening voltage of the PMOS is Vgsp; The first threshold value of the input common-mode voltage corresponding to the common-gate differential pair is Vbiasn+Vgsp, the second threshold value of the input common-mode voltage corresponding to the auxiliary differential pair is VDD-Vbiasp-Vgsp, the first threshold value Vbiasn+Vgsp is less than the second threshold value VDD-Vbiasp, and the common-gate differential pair and the auxiliary differential pair dynamically switch the opening state according to the input common-mode voltage.

3. The wide common-mode input range comparator circuit of claim 2, wherein, The common-gate differential pair and the auxiliary differential pair dynamically switch the opening state according to the input common-mode voltage, comprising: When the input common-mode voltage is lower than the first threshold value, the auxiliary differential pair is in the saturation region, and the common-gate differential pair is in the cutoff region; When the input common-mode voltage is between the first threshold value and the second threshold value, the common-gate differential pair and the auxiliary differential pair are opened and are both in the saturation region; When the input common-mode voltage is higher than the second threshold value, the common-gate differential pair is in the saturation region, and the auxiliary differential pair is in the cutoff region; The common-gate differential pair and the auxiliary differential pair dynamically switch on-state according to input common-mode voltage, thereby realizing a common-mode input range from the lowest to ground level to the highest above the supply voltage.

4. The wide common-mode input range comparator circuit of claim 1, wherein When the input stage adopts a PMOS input pair structure, the drain currents of the common-gate differential pair and the auxiliary differential pair are linearly superimposed on the load, and are converted into voltage signals by the load as output signals of the input stage, specifically comprising: The drain currents of the PMOS tubes M5 and M1 are superimposed on the load R1, and the load R1 converts the superimposed current into a positive output voltage, which is output from the output node OUT1P to the secondary amplification circuit; The drain currents of the PMOS tubes M6 and M4 are superimposed on the load R2, and the load R2 converts the superimposed current into a negative output voltage, which is output from the output node OUT1N to the secondary amplification circuit; The gains of the common-gate differential pair and the auxiliary differential pair are linearly added in the form of current, so that the total gain of the input stage can remain stable in the full input range.

5. The wide common-mode input range comparator circuit of claim 1, wherein When the input stage adopts a PMOS input pair structure, the secondary amplification circuit comprises: A first secondary amplifier for pre-amplifying the input differential signal; comprising PMOS tubes M7-M8, resistors R5, R6 and a bias current source Ibiasp1, the gates of the PMOS tubes M7 and M8 are connected to the positive and negative output nodes OUT1P and OUT1N of the first secondary amplifier respectively; the common source of the PMOS tubes M7 and M8 is connected and provided with a bias current by the bias current source Ibiasp1, the drains of the PMOS tubes M7 and M8 are connected to the ground after being connected to the resistors R5 and R6 in series respectively; at the same time, the connection points of the drains of the PMOS tubes M7 and M8 and the resistors R5 and R6 are connected to the corresponding input terminals of the second secondary amplifier as the positive and negative output terminals of the first secondary amplifier respectively; A second secondary amplifier for converting small-amplitude differential input signals into large-amplitude differential output signals and reducing the delay of the comparator; comprising NMOS tubes M11-M14, PMOS tubes M15 and M16 and a bias current source Ibiasp2, the gates of the PMOS tubes M15 and M16 are connected to the positive and negative output terminals of the first secondary amplifier as the input terminals of the second secondary amplifier; the common source of the PMOS tubes M15 and M16 is connected and provided with a bias current by the bias current source Ibiasp2, the drain of the PMOS tube M15 is connected to the drain, gate and drain of the NMOS tube M13, the drain of the PMOS tube M16 is connected to the drain, gate and drain of the NMOS tube M12; the common gate of the NMOS tubes M11 and M12 is connected, and the common gate of the NMOS tubes M13 and M14 is connected, the connection point of the gates of the NMOS tubes M11 and M12 is connected, and the sources of the NMOS tubes M11-M14 are all connected to the ground; the drains of the PMOS tubes M15 and M16 are connected to the corresponding input terminals of the third secondary amplifier as the positive and negative output terminals of the second secondary amplifier respectively; A third secondary amplifier is configured to convert the large-amplitude differential output signal into a single-end output signal with increased amplitude; the third secondary amplifier comprises PMOS transistors M19 and M20, and NMOS transistors M18, M21-M23, the gates of the NMOS transistors M18 and M21 are connected to the positive and negative output terminals of the second secondary amplifier as the input terminals of the third secondary amplifier; the drain of the NMOS transistor M18 is connected to the drain and gate of the PMOS transistor M19, the drain of the NMOS transistor M21 is connected to the drain of the PMOS transistor M20, and the gates of the NMOS transistors M22 and M23, the gates of the PMOS transistors M19 and M20 are connected together, the sources of the PMOS transistors M19, M20 and M22 are connected to a power supply VDD, the sources of the NMOS transistors M18, M21 and M23 are connected to ground, the drains of the NMOS transistors M22 and M23 are connected together, and the connection point of the drains is the output of the third secondary amplifier, i.e., the output terminal OUT of the comparator circuit.

6. The wide common-mode input range comparator circuit of claim 1, wherein When the input stage adopts the NMOS input pair structure, in the input stage, The voltage drop of the first bias current source Ibiasp' of the common-gate differential pair is Vbiasp', the voltage drop of the second bias current source Ibiasn' of the auxiliary differential pair is Vbiasn', and the turn-on voltage of the NMOS is Vgsn'; The first threshold value of the input common-mode voltage corresponding to the common-gate differential pair is VDD'-Vbiasp'-Vgsn', the second threshold value of the input common-mode voltage corresponding to the auxiliary differential pair is Vbiasn'+Vgsn', the first threshold value VDD'-Vbiasp' is greater than the second threshold value Vbiasn'+Vgsn', and the common-gate differential pair and the auxiliary differential pair dynamically switch the turn-on state according to the input common-mode voltage.

7. The wide common-mode input range comparator circuit of claim 6, wherein, The common-gate differential pair and the auxiliary differential pair dynamically switch the turn-on state according to the input common-mode voltage, comprising: When the input common-mode voltage is higher than the first threshold value, the auxiliary differential pair is in the saturation region, and the common-gate differential pair is in the cutoff region; When the input common-mode voltage is between the first threshold value and the second threshold value, the common-gate differential pair and the auxiliary differential pair are turned on and are both in the saturation region; When the input common-mode voltage is lower than the second threshold value, the common-gate differential pair is in the saturation region, and the auxiliary differential pair is in the cutoff region; The common-gate differential pair and the auxiliary differential pair dynamically switch the turn-on state according to the input common-mode voltage, thereby realizing the common-mode input range from the highest supply voltage to the lowest ground level.

8. The wide common-mode input range comparator circuit of claim 1, wherein When the input stage adopts the NMOS input pair structure, the drain currents of the common-gate differential pair and the auxiliary differential pair are linearly superimposed on the load, and are converted into voltage signals by the load as the output signal of the input stage, specifically comprising: The drain currents of the NMOS transistors M5' and M1' are superimposed on the load R1', and the load R1' converts the superimposed current into a positive output voltage, which is output from the output node OUT1P' to the secondary amplification circuit; The drain currents of the NMOS transistors M6' and M4' are superimposed on the load R2', and the load R2' converts the superimposed current into a negative output voltage, which is output from the output node OUT1N' to the secondary amplification circuit; The gains of the common-gate differential pair and the auxiliary differential pair are linearly added in the form of current, so that the total gain of the input stage can remain stable in the full input range.

9. The wide common-mode input range comparator circuit of claim 1, wherein When the input stage adopts the NMOS input pair structure, the secondary amplification circuit comprises: a first secondary amplifier for pre-amplifying the differential input signal; comprising NMOS tubes M7'-M8', resistors R5' and R6', and a bias current source Ibiasn1'; the gates of the NMOS tubes M7' and M8' are connected to the positive and negative output nodes OUT1P' and OUT1N' of the first secondary amplifier respectively; the common source of the NMOS tubes M7' and M8' is connected and provided with a bias current by the bias current source Ibiasp1'; the drains of the NMOS tubes M7' and M8' are connected to the resistors R5' and R6' respectively, and then grounded; meanwhile, the connection points of the drains of the NMOS tubes M7' and M8' and the resistors R5' and R6' are connected to the corresponding input terminals of the second secondary amplifier respectively; a second secondary amplifier for converting the small-amplitude differential input signal into a large-amplitude differential output signal and reducing the delay of the comparator; comprising PMOS tubes M11'-M14', NMOS tubes M15' and M16', and a bias current source Ibiasp2'; the gates of the NMOS tubes M15' and M16' are connected to the positive and negative output terminals of the first secondary amplifier respectively; the common source of the NMOS tubes M15' and M16' is connected and provided with a bias current by the bias current source Ibiasp2'; the drain of the NMOS tube M15' is connected to the drain and gate of the PMOS tube M11' and the drain of M13'; the drain of the NMOS tube M16' is connected to the drain and gate of the NMOS tube M14' and the drain of M12'; the common gate of the PMOS tubes M11' and M12' is connected, and the common gate of M13' and M14' is connected; the connection point of the gates of the PMOS tubes M11' and M12' is connected; the sources of the PMOS tubes M11'-M14' are all grounded; the drains of the NMOS tubes M15' and M16' are connected to the corresponding input terminals of the third secondary amplifier respectively as the positive and negative output terminals of the second secondary amplifier; a third secondary amplifier for converting the large-amplitude differential output signal into a single-ended output signal with increased amplitude; comprising NMOS tubes M19' and M20', and PMOS tubes M18', M21'-M23'; the gates of the PMOS tubes M18' and M21' are connected to the positive and negative output terminals of the second secondary amplifier respectively as the input terminals of the third secondary amplifier; the drain of the PMOS tube M18' is connected to the drain and gate of the NMOS tube M19', and the drain of the PMOS tube M21' is connected to the drain of the NMOS tube M20' and the gates of the PMOS tubes M22' and M23'; the common gate of the NMOS tubes M19' and M20' is connected; the sources of the MOS tubes M19', M20', and M22' are connected to the power supply VDD', the sources of the MOS tubes M18', M21', and M23' are grounded, and the common drain of the MOS tubes M22' and M23' is connected, and the connection point of the drains is connected to the output of the third secondary amplifier, i.e. the output terminal OUT' of the comparator circuit.

Images