Rear-end control type high-end ideal diode

Abstract

The utility model discloses a rear-end control type high-end ideal diode, which comprises a PMOS (P-channel Metal Oxide Semiconductor) main tube, a comparator circuit and a driving circuit, the PMOS main tube, the comparator circuit and the driving circuit form an integral circuit, and the comparator circuit comprises a PMOS auxiliary tube and a resistor. On the basis of the technical scheme of a PMOS pair transistor and a PMOS main transistor, circuit improvement is carried out, two circuits are designed, the function of preventing backflow is achieved, and a pre-stage circuit can be protected; the loss is low, and the quiescent current loss is small; the high-end load switch and the comparator are used, the circuit is simple, the cost is low, and the practicability is high.

Description

TECHNICAL FIELD

[0001] The utility model relates to diode technical field, concretely is a back end control type high -end ideal diode. BACKGROUND

[0002] Diode has unidirectional conduction characteristic, has the function that prevents reverse flow, obtains more and more application, especially Schottky diode string into power supply has smaller pressure drop, is more and more welcomed by designer. Because Schottky diode's pressure drop is still greater than MOS tube pressure drop, for some voltage sensitive circuit, more inclined to use the MOS tube with low impedance characteristic, improve the reliability of product. Now there are many USB power switches (distribution switches), with prevent reverse flow function, such as MP62055 chip. Because when external equipment is connected to the USB port of computer, the equipment absolutely cannot flow into the VBus of computer in reverse, otherwise will burn the computer. Current Oring circuit is applied to many occasions, and the role is to ensure that each single power supply is independent, does not appear reverse flow phenomenon, and is most commonly used in current sharing circuit, satisfies different power demand.

[0003] PMOS pair tube + PMOS main tube technical scheme: as shown in Figure 1 The prior art patent (a kind of ultra-low loss ideal diode, patent number: CN201821304820.X) belongs to high-end ideal diode, including comparator circuit and PMOS main tube V1, comparator circuit is composed of two independent PMOS auxiliary tube or PMOS pair tube V2, V3 with same parameters and packaged together and resistance R1, R2 etc. The G pole and S pole between PMOS tube are insulated, unlike the BE junction of BJT tube, which can be turned on, the G pole and S pole can be considered to be disconnected in nature, the voltage between the G pole and S pole of PMOS tube is less than V TP (V TP PMOS tube conduction threshold voltage) can be turned on, Figure 2 The PMOS tube parameters of V2, V3 are consistent, like PNP pair tube + PMOS main tube scheme in PNP pair tube, which PMOS tube source voltage is high, which PMOS tube is preferentially turned on, and the other voltage low PNP tube is cut off.

[0004] The PMOS pair + PMOS main diode scheme effectively achieves the function of an ideal diode, controlling the conduction and cutoff of the PMOS main diode V1: when the input power supply VCC is not less than the output power supply Vout, the PMOS main diode V1 conducts; conversely, the PMOS main diode V1 is cut off, preventing the current from the output power supply Vout from flowing back to the input power supply VCC, thus protecting the input power supply circuit. It is equivalent to a high-side ideal diode. The bias resistor is in the megaohm range. Since PMOS transistors are voltage devices, their on-state voltage drop and bias current are very small (in the microampere range), and the losses are negligible. Compared with traditional diodes and ideal diodes composed of a PNP pair + PMOS main diode, the losses are greatly reduced.

[0005] from Figure 1 (PMOS transistor pair + PMOS main transistor technology solution) It can be seen that the gate of the PMOS main transistor V1 is affected by the comparator back-end transistor ( Figure 1 The control of the PMOS transistor V3 (which must be retained) controls the conduction and cutoff of the PMOS transistor V1, and can be called a back-end controlled high-side ideal diode. Therefore, by utilizing the characteristics of discrete components and designing various comparator circuits, we propose a back-end controlled high-side ideal diode to control the conduction and cutoff of the PMOS transistor V1, enriching the implementation forms of the PMOS pair + PMOS transistor technology. This addresses the aforementioned problem. Utility Model Content

[0006] The purpose of this invention is to provide a back-end controlled high-end ideal diode to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, this utility model provides the following technical solution: a back-end controlled high-end ideal diode, comprising a PMOS main tube, a comparator circuit, and a driving circuit, wherein the PMOS main tube, the comparator circuit, and the driving circuit constitute an integrated circuit, and the comparator circuit comprises a PMOS auxiliary tube and a resistor.

[0008] Preferably, the comparator circuit is used to compare the magnitudes of the input power supply VCC and the output power supply Vout.

[0009] Preferably, the driving circuit is composed of a BJT composite transistor (NPN transistor and PNP transistor) or a MOS composite transistor (NMOS transistor and PMOS transistor).

[0010] Compared with the prior art, the beneficial effects of this utility model are: based on the PMOS pair + PMOS main tube technology, the circuit is improved, two circuits are designed, and it has the function of preventing backflow, which can protect the front-end circuit; it has low loss and low static current loss; it uses high-side load switch and comparator, the circuit is simple, the cost is very low, and it is highly practical. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 High-end ideal diode principle diagram realized by comparator of prior art PMOS pair;

[0012] Figure 2 High-end ideal diode principle diagram of rear-end control type of the utility model (one);

[0013] Figure 3 High-end ideal diode principle diagram of rear-end control type of the utility model (two);

[0014] Figure 4 High-end ideal diode principle diagram of rear-end control type of the utility model (three) driven by BJT tube;

[0015] Figure 5 High-end ideal diode principle diagram of rear-end control type of the utility model (four) driven by MOS tube;

[0016] Figure 6 High-end ideal diode principle diagram of rear-end control type of the utility model (five) driven by BJT tube;

[0017] Figure 7 High-end ideal diode principle diagram of rear-end control type of the utility model (six) driven by MOS tube;

[0018] Figure 8 High-end ideal diode principle diagram of rear-end control type of the utility model Figure 2 Forward conduction simulation;

[0019] Figure 9 High-end ideal diode principle diagram of rear-end control type of the utility model Figure 2 Reverse cut-off simulation;

[0020] Figure 10 High-end ideal diode principle diagram of rear-end control type of the utility model Figure 3 Forward conduction simulation;

[0021] Figure 11 High-end ideal diode principle diagram of rear-end control type of the utility model Figure 3 Reverse cut-off simulation. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0023] Embodiment 1

[0024] Referring to Figure 1 , 2 , the utility model discloses a first embodiment, and the embodiment provides a rear end control type high -end ideal diode, including PMOS main tube, comparator circuit, drive circuit, PMOS main tube, comparator circuit, drive circuit constitute integral circuit, comparator circuit includes PMOS auxiliary tube, resistance, and comparator circuit is by PMOS auxiliary tube V3, diode D1 and resistance R1, R2, R3 etc.

[0025] PMOS main tube V1, auxiliary tube is PMOS tube V3, and the gate of PMOS tube V1 is connected with the drain of PMOS tube V3 and the one pin of resistance R2, and the other pin of resistance R2 is connected with the negative pole of power supply;One input end (front end, the anode of diode D1) of comparator is connected with input end power supply VCC, and the other input end (rear end, the anode of D2 tube) of comparator is connected with output end power supply Vout, and the output signal VB of comparator is connected with the gate of PMOS main tube V1.

[0026] Specifically, comparator circuit is used for comparing the size of input end power supply VCC and output end power supply Vout, and the comparison signal of comparator output or is transferred to the gate of PMOS main tube through drive circuit, and the conduction and cut-off of PMOS main tube are controlled, and the output end power supply is prevented from pouring to input end power supply, and the front stage circuit of input end power supply is protected.

[0027] When input end power supply VCC is not less than output end power supply Vout: V3 pipe cut-off, and VB is pulled down due to resistance R2, and the output comparison signal VB of comparator is low level, namely VB≈0V, and the drain of PMOS tube V3 is low level, namely the gate of PMOS main tube V1 is low level, and PMOS main tube V1 is conducted. When input end power supply VCC is less than output end power supply Vout: V3 pipe conduction, and the output comparison signal VB of comparator is approximately Vout-V F , the gate of PMOS main tube V1 is high level, and PMOS main tube V1 is cut-off, and Vout current is prevented from pouring to VCC, and the front stage circuit of VCC power supply is protected.

[0028] PMOS main tube V1 can use PMOS tube of different conduction current size.For the power control of high power, PMOS main tube can select the conduction resistance R DS(ON) It is milliohm, and the power tube device is passed through large current, and the voltage drop is small, namely having very low forward voltage, and it is approximately ideal diode.

[0029] The resistance R1, R3 resistance value range derivation process is as follows.

[0030] 1. When the input power supply VCC is not less than the output power supply Vout: To ensure that the PMOS main transistor V1 can be turned on, the PMOS auxiliary transistor V3 must first be turned off.

[0031] According to the voltage divider principle, the voltage across VA is as shown in equation (1), where V F This refers to the conduction threshold voltage of the diode or PMOS transistor.

[0032] VA = (VCC - V) F ) / (R1+R3)×R1 (1)

[0033] When the body diode controlling V1 is turned on, Vout = VCC - V F When transistor V3 is cut off, the gate-source voltage difference V3 is... GS >V TP V TP V is the turn-on threshold voltage of the PMOS transistor. TP(MAX) <V TP <V TP(MIN) (Consistent with the simulated PMOS transistor parameters), the approximate calculation yields the result shown in equation (2):

[0034] V3 GS =VA - (Vout - V) F )>V TP

[0035] =(VCC-V F ) / (R1+R3)×R1-(VCC-2×V F )>V TP (2)

[0036] Because the bias resistor is relatively large, V is approximately considered to be F =Von=0.5V, to ensure that the PMOS auxiliary transistor V3 is cut off, then V TP >V TP(MIN) Thus, we obtain equation (3):

[0037] (VCC-V F ) / (R1+R3)×R1-(VCC-2×V F )>V TP(MIN) (3)

[0038] 2. When the input power supply VCC is less than the output power supply Vout: To ensure that the PMOS main transistor V1 can be turned off, the PMOS auxiliary transistor V3 must first be turned on.

[0039] Because transistor V3 is turned on, the gate-source voltage difference V3 of transistor V3... GS <V TP V TPV TP(MAX) <V TP <V TP(MIN) , get as shown in equation (4):

[0040] V3 GS = VA- (Vout-V F ) < V TP(MAX)

[0041] = (VCC-V F ) / (R1+R3) x R1- (Vout-V F ) < V TP(MAX) (4) Equation (4) is simplified as shown in equation (5):

[0042] (VCC-V F ) / (R1+R3) x R1- V TP(MAX) + V F < Vout (5)

[0043] Because the bias resistance is large, approximately VF = Von = 0.5V, to ensure that the PMOS auxiliary tube V3 is turned on, V TP < V TP(MAX) , that is, equation (6) is shown:

[0044] Vout > (VCC-V F ) / (R1+R3) x R1- V TP(MAX) + V F (6)

[0045] Because Vout ≥ VCC, equation (6) is established, Vout = VCC is substituted into equation (6) and is simplified as shown in equation (7):

[0046] (VCC-V F ) / (R1+R3) x R3 > - V TP(MAX) (7)

[0047] Equation (3) and equation (7) are combined to solve.

[0048] Embodiment 2

[0049] The circuit in embodiment 1 Figure 2 is deleted on the basis of diode D1, the composition is unchanged, as shown in Figure 3 , the difference between the two embodiments is that embodiment 2 has no diode D1, because V3 tube is a voltage device, the resistance R1, R3 resistance value is different, R1, R3 resistance value is relatively large. Therefore, the total loss of embodiment 2 is lower than that of embodiment 1.

[0050] The resistance R1, R3 resistance value range derivation process is as follows:

[0051] 1、When the input power VCC is not less than the output power Vout: to ensure that the PMOS main V1 can be turned on, first to ensure that the PMOS auxiliary V3 is off.

[0052] According to the principle of voltage division, the voltage of VA is shown as formula (8):

[0053] VA = VCC / (R1+R3) x R1 (8)

[0054] The body diode of the main V1 is turned on, and Vout = VCC-V F , wherein V F is the threshold voltage of the diode and the body diode of the MOS tube, V3 is off, and the voltage difference V3 GS between the gate and the source of the V3 tube is greater than V TP , wherein V TP is the threshold voltage of the PMOS tube, and if V TP(MAX) is less than V TP , V TP(MIN) is less than V GS , and the formula (9) is obtained:

[0055] V3 TP

[0056] = VCC / (R1+R3) x R1-(VCC-V F ) > V TP (9)

[0057] Because the bias resistance is large, it is approximately considered that VF = Von = 0.5V, since the PMOS tube is a voltage type device, the bias resistance R1 can take a large value, R1 = 1MΩ, to ensure that the PMOS auxiliary V3 is off, V3 GS > V TP(MIN) , that is, the formula (10) is obtained:

[0058] VCC / (R3+R1) x R1-(VCC-V on ) > V TP(MIN) (10)

[0059] 2、When the input power VCC is less than the output power Vout: to ensure that the PMOS main V1 can be turned off, first to ensure that the PMOS auxiliary V3 is turned on.

[0060] Since the V3 tube is turned on, the voltage difference V3 GS between the gate and the source of the V3 tube is less than V TP , and the formula (11) is obtained:

[0061] V3 GS = VA-Vout < VTP

[0062] = VCC / (R1+R3) x R1 - V TP (11)

[0063] Simplify formula (11) as shown in formula (12):

[0064] VCC / (R1+R3) x R1 - V TP <Vout (12)

[0065] Because the bias resistance is large, it is approximately considered that VF = Von = 0.5V, R1 = 1MΩ, in order to ensure that V3 can be turned on, V3 GS <V TP(MAX) , formula (13) is obtained:

[0066] Vout > VCC / (R1+R3) x R1 - V TP(MAX) (13)

[0067] Because Vout ≥ VCC, formula (13) is established, and Vout = VCC is substituted into formula (13) to simplify formula (14):

[0068] VCC / (R1+R3) x R3 > -V TP(MAX) (14)

[0069] Solve formula (10) and formula (14) together.

[0070] Example 3

[0071] On the basis of Figure 2 , the totem pole driving circuit is improved, and the totem pole circuit uses discrete components NPN tube V4 (high end) + PNP tube V5 (low end) to form a complementary push-pull circuit, which has a current amplification effect, and in the output state, one transistor is always off and the other transistor is always on; Because the gain is about 1, the Miller effect does not occur, and the frequency characteristic is very good, and the push-pull circuit can realize high-speed switching of BJT. Integrated push-pull circuit driving chip can also be used to realize high-speed switching of BJT. The NPN tube (high end) and the PNP tube (low end) are the upper and lower output tubes, and the connection between the two tubes is the output end. The upper tube V4 is turned on, the lower tube V5 is turned off, and the high level is output. The lower tube V5 is turned on, the upper tube V4 is turned off, and the low level is output. The two output tubes alternately work in the off state and the saturation state, and if the circuit logic makes the upper and lower tubes both off, the output is in a high impedance state. NPN tube V4 (high end) + PNP tube V5 (low end), the driving rear-end control type high-end ideal diode schematic diagram is shown in Figure 4 .

[0072] Figure 4The middle totem pole circuit uses discrete components NMOS tube V4 (high end) + PMOS tube V5 (low end) to form a complementary push-pull circuit, and the NMOS tube (high end) and the PMOS tube (low end) are respectively the upper and lower output tubes, and the connection place of the two tubes is the output end, which realizes the driving of the rear-end control type high-end ideal diode schematic diagram as shown in Figure 5 .

[0073] Example 4

[0074] On the basis of Figure 3 , the totem pole driving circuit is added, and the complementary push-pull circuit composed of NPN tube V4 (high end) + PNP tube V5 (low end) is used to drive the rear-end control type high-end ideal diode schematic diagram as shown in Figure 6 : wherein the value range of resistors R1 and R3 is referred to Example 2.

[0075] Figure 6 The middle totem pole circuit uses discrete components NMOS tube V4 (high end) + PMOS tube V5 (low end) to form a complementary push-pull circuit, and the NMOS tube (high end) and the PMOS tube (low end) are respectively the upper and lower output tubes, and the connection place of the two tubes is the output end, which realizes the driving of the rear-end control type high-end ideal diode schematic diagram as shown in Figure 7 .

[0076] Simulation test

[0077] According to Figures 2-3 circuit schematic diagram, the simulation software Multisim (version V14.0) of National Instruments Company is used for simulation test, the PMOS tube is selected from ON Semiconductor Company, the model is NVTFS5124PLTAG, the minimum value V TP(MIN) =-1.5V, the maximum value V TP(MAX) =-2.5V, the typical value V TP is not given, the conduction current can reach-6A, the conduction resistance R DS(ON) =0.26Ω (V GS =-10V), R DS(ON) =0.38Ω (V GS =-4.5V). The load resistance RL=10Ω, and the specific simulation test is as follows.

[0078] Example 1 simulation

[0079] R1=47.0kΩ, R3=12.0kΩ.

[0080] DC power positive conduction simulation test (when the input end power VCC is not less than the output end power Vout): VCC=VCC1=12V (switch J1 is closed and switch J2 is opened): VA=9.20V, the simulation is as Figure 8As shown, transistor V3 is off, the comparator outputs a comparison signal VB≈177mV, the drain of PMOS transistor V3 is at a low level, meaning the gate of PMOS transistor V1 is at a low level, and PMOS transistor V1 is turned on. During forward conduction, the power supply Vout at the output of PMOS transistor V1 is 11.7V (test point PR2), and the forward voltage drop of PMOS transistor V1 is 12V - 11.7V = 0.3V, which is lower than the forward voltage drop of the diode V. F The power supply output current at the positive terminal is 1.17A (test points PR1 and PR3), corresponding to the on-resistance R. DS(ON) =0.3V / 1.17A=0.256Ω, which is not much different from the datasheet data.

[0081] DC power supply reverse cutoff simulation test (input power supply VCC is less than output power supply Vout): After switch J1 is closed, switch J2 is also closed. Assuming Vout = VCC2 = 12.001V > VCC = 12V: VA = 9.20V, ... Figure 9 As shown, transistor V3 is turned on, and the comparator's output comparison signal VB≈Vout-V F =11.6, meaning the drain of PMOS transistor V3 is at a high level, and PMOS transistor V1 is cut off, preventing Vout current from flowing back into VCC and protecting the VCC power supply pre-amplifier circuit. The current flowing into PMOS transistor V1 from VCC1 is 9.69nA (test point PR1, negligible), with no backflow current; the output current of power supply VCC1 is 196μA (test point PR5, negligible).

[0082] The simulation test of VCC2 boost reverse bias with VCC=12V is shown in Table 1. When the voltage range of VCC2 is 12.0V < VCC2 < 36V, the simulation test shows that there is no reverse current from VCC2 to VCC.

[0083] Table 1. Reverse bias simulation test

[0084]

[0085] Example 2 Simulation

[0086] Let R1 = 1MΩ and R3 = 300kΩ.

[0087] DC power supply forward conduction simulation test (when the input power supply VCC is not less than the output power supply Vout): VCC = VCC1 = 12V (switch J1 closed, switch J2 open): VA = 9.23V, simulation results are as follows. Figure 10As shown, PMOS V3 is off, the comparator output comparison signal VB≈97mV, the drain of PMOS V3 is low, the gate of PMOS main V1 is low, and PMOS main V1 is on. When PMOS main V1 is on, the output power supply Vout of PMOS main V1 is 11.7V (test point PR2), and the on voltage drop of PMOS main V1 is 12V-11.7V=0.3V, which is lower than the on voltage drop V F of the diode. DS(ON) The output current of the positive power supply is 1.17A (test points PR1 and PR3), and the on impedance R

[0088] DC power supply reverse blocking simulation test (input power supply VCC is less than output power supply Vout): after switch J1 is closed, switch J2 is also closed, and assuming Vout=VCC2=12.001V>VCC=12V: VA=9.23V, V3 is on, the output comparison signal VB of the comparator is approximately Vout-V F =11.6V, that is, the gate of PMOS main V1 is high, PMOS main V1 is off, and the Vout current is prevented from flowing back to VCC, protecting the VCC power supply front-end circuit. The current flowing from VCC to PMOS main V1 is 184nA (test point PR1, which can be ignored), and it can be considered that no backflow current exists; the output current of the power supply VCC1 is 9.41μA (test point PR5, which can be ignored), as shown in Figure 11 .

[0089] VCC=12V, VCC2 reverse bias simulation test as shown in Table 2, when VCC2 voltage range 12.0V

[0090] Table 2 reverse bias simulation test

[0091]

[0092] The simulation tests of example 3 and example 4 are not described in detail, and refer to the simulation of example 1 and example 2.

[0093] Although the embodiments of the utility model have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and spirits of the utility model, and the scope of the utility model is defined by the appended claims and their equivalents.

Claims

1. A back-end controlled high-side ideal diode comprising a PMOS master, a comparator circuit, a driver circuit, characterized in that: The PMOS main pipe, the comparator circuit and the driving circuit constitute an overall circuit, and the comparator circuit comprises a PMOS auxiliary pipe and a resistor.

2. A high-end ideal diode of the back-end controlled type according to claim 1, characterized in that: The comparator circuit is used for comparing the sizes of an input power supply VCC and an output power supply Vout.

3. A back end controlled high end ideal diode as claimed in claim 1, wherein: The driving circuit is composed of a BJT compound pipe (NPN pipe and PNP pipe) or a MOS compound pipe (NMOS pipe and PMOS pipe).

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