PERIPHERAL STORAGE CIRCUIT WITH THREE-DIMENSIONAL TRANSISTORS AND METHOD FOR THEIR MANUFACTURING

DE602021054147T2Active Publication Date: 2026-05-06YANGTZE MEMORY TECH CO LTD
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
YANGTZE MEMORY TECH CO LTD
Filing Date
2021-06-30
Publication Date
2026-05-06

AI Technical Summary

Technical Problem

Existing memory devices face challenges in achieving high speed, low leakage current, high voltage, and small size in memory peripheral circuits without increasing cost, as scaling down planar transistors leads to undesirable high leakage current and advanced CMOS technology nodes are not suitable due to voltage reduction and increased complexity.

Method used

Replace conventional planar transistors in memory peripheral circuits with 3D transistors, allowing for a hybrid configuration with both 3D and planar transistors in the same process flow, which reduces leakage current and enables smaller sizes while maintaining high saturated drain current.

Benefits of technology

The use of 3D transistors in memory peripheral circuits achieves better speed and leakage current performance, reduces circuit size, and maintains high voltage levels without increasing cost, addressing the limitations of planar transistors and advanced CMOS technology nodes.

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