WRITING METHOD FOR DIFFERENTIAL RESISTIVE MEMORIES

Description

Field of invention

[0001] The present invention relates to a writing method for differential resistive memories, of 2T2R structure. State of the art

[0002] Resistive memories are non-volatile memories that offer higher operating speeds than NAND flash (SSD memory), low power consumption, and a long lifespan. For these reasons, resistive memories are promising candidates to replace both RAM and current non-volatile memories such as flash memories.

[0003] There are several resistive memory technologies. These include conductive bridge resistive memories, also known as CBRAM (for "Conductive-Bridging Random-Access Memory"), or oxide-based resistive memories, also known as OxRAM (for "Oxide-based Random-Access Memory"), or phase change memories, also known as PCM (for "Phase Change Memory").

[0004] A resistive memory is composed of a multitude of resistive memory cells arranged in rows and columns to form a matrix. An RRAM memory cell has at least one resistive element whose electrical resistance can be modified.

[0005] An elementary resistive memory cell as illustrated in the Figure 1a(with an example of an associated reading device), generally consists of a transistor (T) and a resistive component (R) or resistor (12), where a bit of information is encoded by the value of the electrical resistance of the resistor and accessed via the transistor at the intersection of a bit line (BL) and a word line (WL). For these elementary cells, a logic '0' can for example be encoded by programming the resistor in a high resistance state HRS, and a logic '1' can then be encoded by programming the resistor in a low resistance state LRS, and we then speak of encoding in 1T1R mode.

[0006] To program a memory cell, a programming voltage is applied between the electrodes of the memory cell. This can be a write voltage to write the memory cell, i.e., place it in the low-resistive state LRS, or an erase voltage to erase the memory cell, i.e., place it in the high-resistive state HRS. However, after a programming operation, it may happen that the memory cell does not go into the desired resistance state. For this reason, a check is usually performed to ensure that the memory cell is correctly programmed by comparing its resistance value R to a predefined resistance threshold R REF .

[0007] However, the difference between the lowest value corresponding to an HRS level and the highest value corresponding to the LRS level, also called a "memory window", is often small. Therefore, "differential encoding" is commonly used to encode a binary value to be stored. A bit of information can then be encoded in a so-called 2T2R memory cell, composed of two elementary 1T1R cells, comprising 2 transistors (2T) and 2 resistors (2R), and this is called 2T2R mode encoding. Figure 1b illustrates an alternative implementation of a 2T2R cell with a device for reading such a memory cell.

[0008] Since each of the HRS and LRS states can be associated with a logic value, i.e. '0' or '1', it can be considered that in a 2T2R cell one of the two resistive elements encodes the bit to be programmed in a non-inverted version while the other resistive element encodes the same bit in an inverted version. For example, a logic '0' is encoded by programming the resistor of the first 1T1R cell in a high resistance state HRS and the resistor of the second 1T1R cell in a low resistance state LRS, and a logic '1' is encoded by programming the resistor of the first 1T1R cell in a low resistance state LRS and the resistor of the second cell in a high resistance state HRS.

[0009] Thus, in differential encoding, each bit of information is encoded in a 2T2R elementary cell formed by two resistive elements which are written in opposition of state, that is to say one of the resistive elements with an HRS level and the other with an LRS level, the respective resistance levels of the two resistive elements being always determined in the same order between the two elements, which define whether we are in the presence of a '0' or a logical '1' depending on whether it corresponds to the HRS-LRS or LRS-HRS states.

[0010] When writing to a 1T1R or 2T2R memory cell, it must be ensured that each electrical resistance that is to be programmed to an HRS state or the LRS state is respectively either larger or smaller than a reference value R REF . The comparison of an electrical resistance with the value R REF is made by a read operation during which the programmed resistance is compared with the value R REF using a sense amplifier or SA (for "Sense Amplifier" according to the English terminology) illustrated by component 14 on the Figure 1a , 24 on the Figure 1b , and 34 in Figure 1c. Subsequently, this reading operation with comparison to a reference value is called 1T1R mode.

[0011] On the Figure 1a, the detection amplifier 14 reacts to the difference of its two inputs 'SL' (coming from the cell 1T1R) and 'ref' (representative of a reference electrical resistance value R REF ), to generate an output signal 'V out ' which indicates the resistive state of the memory element of the cell and thus informing the value which is stored in the cell 1T1R.

[0012] On the Figure 1b, the detection amplifier 24 is sensitive to the difference on its inputs, to generate an output signal 'V out '. Two multiplexers (23-1, 23-2) are respectively connected, on a first input, to each SL line (SL1, SL2) connected to a 1T1R cell (22-1, 22-2). The second input of each multiplexer is connected to a reference resistor R REF . The outputs of the multiplexers are respectively connected to the inputs of the differential detection amplifier 24. This diagram is very symbolic and does not represent all the electronic elements necessary for carrying out a reading operation which are well known to those skilled in the art (in particular the polarization circuits of the elementary cells and the reference resistor). This simplified diagram makes it possible to illustrate several possible reading principles for differential cells.Thus, when the two multiplexers are configured to pass the signals present on the lines SL1 and SL2, the amplifier 24 evaluates a difference in resistance of the two resistive elements of the 2T2R cell (respectively, the difference between 22-1 and 22-2), thus providing information on the value which is stored in the selected differential pair of the 2T2R cell. When one wishes to carry out a reading of a single 1T1R cell, and return to the reading mode represented in . Figure 1a , the multiplexers are positioned so as to allow a SL1 or SL2 line to pass through one of the multiplexers and to allow the signal connected to the reference resistor to pass through the other of the multiplexers.

[0013] Read operations in resistive memories are usually performed in 1T1R mode. To read data from the RRAM cell, a small read voltage that does not disturb the current state of the cell is applied to determine what logic state the cell is in.

[0014] In memories where the information is encoded in 2T2R mode, the reading operations, except for the programming verification operation, can be carried out in 2T2R mode, also called differential reading mode. The values ​​of the two resistors present in each 2T2R memory cell that is addressed are compared with each other using a sense amplifier SA.

[0015] A technique for reading data stored in a 2T2R memory cell is described in the document: "Hybrid Analog-Digital Learning with Differential RRAM synapses" by Bocquet et al. IEDM19-534. It uses a read circuit with a latch-type sense amplifier which, during a read operation, is coupled to the differential pair of resistive elements via a pair of bit lines and is equipped with nodes whose potentials switch according to current values ​​flowing through the resistive elements. This type of sense amplifier is implemented with few transistors and operates as a high-gain differential current amplifier. It allows direct comparison of currents flowing through the resistive elements and circulating via bit lines.

[0016] Since the resistive elements retain their respective values ​​even after the applied voltage is removed, resistive RRAM is a non-volatile memory. However, memory usage involves frequent transitions between a high resistance state (HRS) and a low resistance state (LRS), and vice versa, and each switching event between these resistive states can introduce damage, as the programmed resistance values ​​may change due to relaxation phenomena, thus leading to degradation of the RRAM performance.

[0017] The retention time of information in a resistive memory then depends on (a) read and write operations, (b) operating temperatures and / or (c) high magnetic fields in the case of magnetic memories.

[0018] In addition, switching voltages are also parameters with a high degree of variation. Variations in resistance switching include temporal (cycle-to-cycle) fluctuations and spatial (device-to-device) fluctuations.

[0019] Furthermore, resistive memories also exhibit cell-to-cell non-uniformity which also degrades memory performance by reducing the memory margin between two states. The origin of this variability is attributed to manufacturing process non-uniformities such as switching film thickness, etching damage and electrode surface roughness.

[0020] These variations cause the resistances of resistive memories that are programmed in the LRS state to drift toward an HRS state, and the resistances that are programmed in the HRS state to drift toward an LRS state. Therefore, this shift in the values ​​of the programmed resistances can cause errors during read operations and reduce the performance of the memories.

[0021] A common way to improve the performance of RRAM memories is to reduce their error rate. To reduce the error rate of memories, a commonly used solution is to use an error-correcting code (ECC) that encodes the data before it is written to memory. Typically, the ECC encoder is located inside or near the memory controller. When encoding data with an ECC code, check bits are added to the data bits. The check bits represent redundant information calculated from the data bits, which allows for the detection and correction of errors affecting both the data bits and the check bits. The data bits and check bits together form a code word.

[0022] The use of 2T2R resistive memories, which theoretically have a reading window twice as large, allows to reduce the error rate and the need to use an expensive correction code. The efficiency of differential encoding is greater in the case where the programming of each resistor used for differential encoding is carried out in 1T1R mode, that is to say in a mode where it is necessary to guarantee that if the value of the resistor must be in HRS / LRS state then it is much larger / smaller than a reference value R REF . However this last constraint makes the operation of writing a resistive memory more difficult and longer.

[0023] In 2T2R resistive memories, a write operation uses significantly more energy than a read operation and, moreover, it affects the performance of the memory cells, much more than a read operation does. Faced with this problem of performance loss, there is a need for a solution to avoid or reduce write operations in 2T2R resistive memories. WO 2021 / 016237 A1 and US 2019 / 333579 A1 disclose methods for programming resistive memories. Brief description of the invention

[0024] The invention aims to overcome all or part of the problems mentioned above by proposing a writing method for resistive type memories of the 2T2R type which is less restrictive and also faster. This writing method makes it possible to guarantee the functionality of the resistive memory despite the intrinsic variability of the writing operations for resistive memories.

[0025] To this end, the subject of the invention is a method for writing a data word into a resistive memory composed of 2T2R differential cells each comprising first and second sets of a resistor (R) and a selection transistor (T), the method comprising steps consisting of: generating an initial code word from initial data bits and verification bits generated from the data word, and initializing a programming number counter, the number of programmings corresponding to a maximum number of programmings for said word in a group of selected differential cells; programming in 1T1R mode this initial code word into the resistive memory, by selecting the first 1T1R sets of the selected differential cells, then performing a 1T1R verification reading and incrementing or decrementing the programming number counter;repeat the previous step until all the bits of the initial code word have been programmed correctly and the maximum number of programmings has not been reached; invert the initial code word and reset the number of programmings counter; program in 1T1R mode in the resistive memory, the initial code word inverted in the previous step, by selecting the second 1T1R sets of the selected differential cells, then carry out a 1T1R verification reading and increment or decrement the number of programmings counter; repeat the previous step until all the bits of the initial inverted code word have been programmed correctly and the maximum number of programmings has not been reached; carry out a verification reading in 2T2R differential mode of the selected differential cells and verify at least that the data read correspond to said initial data;and depending on the result of the verification, terminate the writing process or report an error in the writing process.;

[0026] In one embodiment, said 2T2R differential mode verification reading includes verifying all bits of the read codeword against bits of the original codeword.

[0027] In one embodiment, the step of repeating the previous step (programming in 1T1R mode this initial code word in the resistive memory) comprises the following substeps of: checking by reading in 1T1R mode in the resistive memory if there are still unprogrammed data and verification bits; and if there are still unprogrammed bits and if the maximum number of memory writes for said initial code word is not reached, repeating the step of programming in 1T1R mode said initial code word in the resistive memory; or if there are no unprogrammed bits or if the maximum number of memory writes for said initial code word is reached, continuing with the next step.

[0028] In one embodiment, the step of repeating the previous step (if there are unprogrammed bits remaining and if the maximum number of memory writes for said initial code word is not reached) comprises the following substeps of: checking by reading in 1T1R mode in the resistive memory if there are unprogrammed data and verification bits of the inverted initial code word remaining; and if there are unprogrammed bits remaining and if the maximum number of memory writes for said inverted initial code word is not reached, repeating the step of programming in 1T1R mode said inverted initial code word in the resistive memory;or if there are no unprogrammed bits remaining or if the maximum number of memory writes for said inverted initial code word is reached, continue with the next step (perform a verification reading in 2T2R differential mode of the selected differential cells and verify at least that the data read correspond to said initial data).;

[0029] In one embodiment, the step of repeating the previous step (programming in 1T1R mode in the resistive memory, the initial code word inverted in the previous step) comprises the following substeps of: checking by reading in 1T1R mode in the resistive memory if there are still unprogrammed data and verification bits of the initial inverted code word; and if there are still unprogrammed bits and if the maximum number of memory writes for said initial inverted code word is not reached, repeating the step of programming in 1T1R mode said initial inverted code word in the resistive memory;or if there are no unprogrammed bits remaining or if the maximum number of memory writes for said inverted initial code word is reached, continue with the next step (perform a verification reading in 2T2R differential mode of the selected differential cells and verify at least that the data read correspond to said initial data).;

[0030] In one embodiment, the step of terminating the writing process is performed if the data read in 2T2R mode matches said initial data; and wherein the step of signaling an error of the writing process is performed if the data read in 2T2R mode does not match said initial data.

[0031] In one embodiment, the step of programming in 1T1R mode the initial code word in the resistive memory and / or the step of programming in 1T1R mode the inverted initial code word in the resistive memory comprising sub-steps consists of: reading in 1T1R mode in the resistive memory the bits at the programming address of the code word and comparing the bits read at said programming address and the bits of the code word to be programmed, and programming in 1T1R mode in the resistive memory only the bits of the code word which do not correspond to the read bits.

[0032] In one embodiment, the step of programming in 1T1R mode the initial code word in the resistive memory or the step of programming in 1T1R mode the inverted initial code word in the resistive memory are performed by a single write circuit adapted to configure the cells of the resistive memory in an HRS or LRS state.

[0033] In one embodiment, the step of programming in 1T1R mode the initial code word in the resistive memory and / or the step of programming in 1T1R mode the inverted initial code word in the resistive memory are performed by a first write circuit only adapted to configure in an HRS state the cells of the resistive memory and, in parallel, by a second write circuit only adapted to configure in an LRS state the cells of the resistive memory.

[0034] In one embodiment, the step of programming in 1T1R mode the initial code word in the resistive memory and / or the step of programming in 1T1R mode the inverted initial code word in the resistive memory are performed firstly by the first write circuit concerning the cells of the resistive memory to be programmed in an HRS state and then being performed secondarily by the second write circuit concerning the cells of the resistive memory to be programmed in an LRS state, or vice versa.

[0035] The invention also relates to a system comprising a resistive memory composed of 2T2R differential cells each comprising first and second sets of a resistor (R) and a selection transistor (T), and a device for writing a data word in the resistive memory, the device comprising means for implementing the steps of the writing method of the invention.

[0036] In one embodiment, the means of the device for writing a data word comprise a memory controller coupled to the resistive memory to implement the verification reading step in 2T2R differential mode of the writing method of the invention.

[0037] In one embodiment, the means of the device for writing a data word comprise a host processor coupled to the resistive memory adapted to implement the verification reading step in 2T2R differential mode of the method of the invention. Brief description of the figures

[0038] Other characteristics, details and advantages of the invention will emerge from reading the description given with reference to the attached drawing given by way of example and which represents: There Figure 1a and the Figure 1b illustrate implementations of a 1T1R memory cell and a 2T2R memory cell respectively. The figure 2represents the steps of a method of writing a data word in a resistive memory composed of 2T2R differential cells according to an embodiment of the invention. The figure 3 represents a particular embodiment of the step of programming in 1T1R mode an initial code word in a resistive memory. The figure 4 represents a general system for implementing the steps of a method for writing a data word in a resistive memory composed of 2T2R differential cells according to an embodiment of the invention. Detailed description of the invention

[0039] A write operation in 2T2R type resistive memories requires the programming of two resistors.

[0040] A write operation to a 2T2R resistive memory, such as the 2T2R 430 resistive memory of the figure 1, allows differential encoding which can be achieved by programming the code word in 1T1R mode a first time as it was generated, to write in the “left” cells 22-1 and a second time in a complementary manner to write in the “right” cells 22-2.

[0041] There figure 2represents a method 200 for writing a data word into a 2T2R type resistive memory according to an embodiment of the invention. When initiating the writing method, the initial data bits that are to be written are first encoded by an ECC encoder, during step 210 of generating an initial code word. Also during this step 210, a counter is initialized with a maximum number of programming operations. For example, the maximum number of programming operations may be 10 units, the counter starting at 10 and being decremented by one unit at each programming operation until reaching 0 in which case there are no more programming operations available. Alternatively, the maximum number of programming operations may be 10 units, the counter starting at 0 and being incremented by one unit at each operation until reaching 10 in which case there are no more programming operations available.

[0042] The writing method 200 continues with a step 220 of programming the initial code word in the resistive memory according to a 1T1R writing mode. In practice, it is the “left” cells of each differential cell which are written in 1T1R mode. This programming step 220 also includes the decrementing of the programming counter. The programming counter is decremented or incremented at each new data bit programming step.

[0043] After the programming step 220, a reading step 230 in 1T1R mode according to the address of the initial code word which has just been programmed is carried out. Similarly, it is the "left" cells of each differential cell which are read in 1T1R mode. These two programming and reading steps 220, 230 correspond to an operation generally called WRITE / VERIFY, making it possible to check whether there are still unprogrammed bits of a code word after its programming.

[0044] In the affirmative case, i.e. in the case where data and / or verification bits have not been programmed, and if the maximum number of memory writes according to the programming number counter for said initial code word has not yet been reached, the programming step 220 is repeated (yes branch of 230). At each repetition of a programming step 220, the programming number of the counter is only incremented if it has already been incremented during the first programming. Alternatively, the programming number of the counter is decremented if it has already been decremented during the first programming.

[0045] This cycle of steps 220, 230 is carried out as many times as necessary until the data and verification bits of the initial code word are all programmed or until the maximum number of writes to memory according to the programming number counter for said initial code word is reached.

[0046] If all bits of the initial code word or if the maximum number of writes has been reached (branch no of 230), the method continues with the next step 240 of inverting the initial code word and resetting the counter of the number of programmings.

[0047] The writing method 200 continues with a step 240 of inverting the initial code word, making it possible to obtain a new word and to reset the counter of the number of programmings. By inverting the initial code word, it is understood that each data and verification bit of the initial code word is inverted, the logic values ​​'1' becoming '0' and vice versa.

[0048] The writing method 200 then continues with a step 241 of programming the bits of the inverted initial code word according to a 1T1R writing mode. In practice, this time it is the "right" cells of each differential cell that are written in 1T1R mode. This programming step 241 also includes the decrementing of the programming counter. After this programming step 241, a reading step 242 in 1T1R mode, at the memory address that has just been programmed, is carried out. Here too, it is the "right" cells of each differential cell that are read in 1T1R mode. These two steps 241, 242, of programming and reading and verification also correspond to an operation generally called WRITE / VERIFY, making it possible to check whether there are still unprogrammed bits of the inverted initial code word after its programming.

[0049] When programming in 1T1R mode the data bits and the check bits of the inverted initial code word (or complementary word) the programming address is generally incremented so as to correspond to the complementary address of each 2T2R resistive memory cell for which the data and check bits of the initial code word had to be programmed during programming step 220 (for the "left" cells). Thus, the complementary address corresponds to the "right" resistors complementary to the "left" resistors for which programming has already been carried out (or attempted if there has been a programming error).

[0050] Returning to step 242, in the affirmative case where data and verification bits of the inverted initial code word have not been programmed, and if there are still programming operations available, i.e. if the maximum number of memory writes according to the programming number counter for said inverted initial code word has not yet been reached, the programming step 241 is repeated (yes branch of 242).

[0051] This cycle of steps 241, 242 is carried out as many times as necessary until the bits of the inverted initial code word are all programmed or until the maximum number of memory writes according to the programming number counter for said inverted initial code word is reached, in which case (branch no. 242) the writing process continues with the following step 250 which consists of a verification reading operation in 2T2R differential mode of the selected differential cells and a minimum verification operation that the data read correspond to said initial data. By this verification, it is determined whether the differential reading in 2T2R mode of the bits which were programmed during the previous steps makes it possible to read data which correspond to the initial data for which the writing process was carried out.If the data read in 2T2R mode matches the initial data, then the write process can be terminated 251. If the data read in 2T2R mode does not match the initial data, then a write process error is reported 252.

[0052] Advantageously, the step 240 of inverting the initial code word followed by the step 241 of programming in 1T1R mode the inverted initial code word are carried out without any other operation of writing and verifying the initial code word which was programmed in 1T1R mode during the previous step 220 of programming the initial code word.

[0053] The writing method of the present invention makes it possible to overcome programming failures or errors in 1T1R mode when programming an initial code word or this initial code word in an inverted form. Indeed, if it is customary in the technical field of resistive memories to check after each writing the correct programming of data and verification bits, it is also customary not to continue such writing operations until all the bits are programmed. Thus, if in the field a limitation of the maximum number of programming operations is already known, this maximum number of programming operations is determined so as to ensure sufficient reliability of the programming in 1T1R mode and therefore a sufficient number of programming cycles.

[0054] The inventors have established that the method of writing a code word in a resistive memory composed of 2T2R cells of the present invention can at least partially overcome this level of reliability of programming in 1T1R mode required in the art. Indeed, the method of the present invention relies on doubling the reading margin when this reading is carried out in differential mode, which makes it possible to reduce the repetition of the writing procedures while maintaining a sufficient level of reliability. In other words, the maximum number of writing iterations in 1T1R mode is in the present invention chosen to be lower than the maximum number of writing iterations in 1T1R mode generally retained in the devices of the state of the art.

[0055] Thus, the writing method of the present invention makes it possible to maximize the chances of correctly reading a code word while the maximum number of programming operations is reduced. Consequently, the writing method of the present invention makes it possible to optimize the performance and reliability of a resistive memory in 2T2R mode by going against a search for the reliability of programming operations carried out in 1T1R mode.

[0056] In a particular case concerning writing for resistive memories in 2T2R mode where the writing method 200 does not involve writing data bits constituting a whole word but only a subdivision of this whole word, it is necessary beforehand to carry out a reading of the whole word at the memory address targeted by the writing operation 200, to correct any storage or reading errors using the ECC decoder and to include in the possibly corrected whole word, the subdivision of the word to be written. The writing method 200 can then be carried out according to the first step 210 of generating a code word from the data bits corresponding to the corrected and modified word.

[0057] There figure 3represents a particular embodiment of a method 300 consisting of programming in 1T1R mode a word in a resistive memory. The method 300 of programming a word in the 1T1R memory can be applied for the presented step 220 of the figure 2 , of programming the bits of the initial code word generated in the resistive memory according to a 1T1R mode and also for step 241 of programming the bits of the inverted initial code word, in the resistive memory and according to a 1T1R mode.

[0058] Programming a word in memory in 1T1R mode according to the figure 3begins with a step 310 consisting of reading in 1T1R mode in the resistive memory the bits at the programming address and comparing the bits read at said programming address and the bits of the word to be programmed. Thanks to this comparison, it is possible to determine which bits read are already programmed correctly for the word which must be programmed and which are not programmed correctly.

[0059] Following this step 310, the programming 300 continues with a step 320 consisting of programming in 1T1R mode in the resistive memory only the bits which do not correspond to the bits of the word to be programmed. In particular, in the particular embodiment of the figure 3, only the bits that were not equal to '1' are programmed and the bits that were already programmed to '1' are not programmed. This step is also known as a "set" operation. Also, during this programming the programming number counter is decremented.

[0060] This step 310, of reading then programming bits only equal to '1', corresponds to a step known in English as "READ BEFORE WRITE" which makes it possible to save the programming of cells which do not need to be programmed.

[0061] Programming a code word into memory in 1T1R mode according to the figure 3 continues with a step consisting of checking by reading in 1T1R mode at the programming address in the resistive memory if there are still bits not programmed at '1'. This step corresponds to steps 230 and 242 of the figure 2 .

[0062] Programming a word in memory in 1T1R mode according to the figure 3 continues with a step 340 consisting of programming in 1T1R mode in the resistive memory the bits of the code word equal to '0' which do not correspond to the bits read. In particular, in the particular embodiment of the figure 3 , the data bits that were already programmed to '0' are not changed. This step is also known as a "reset" operation. Also, during this programming the programming count counter is decremented.

[0063] Programming a code word into memory in 1T1R mode according to the figure 3 continues with a step consisting of checking by reading in 1T1R mode at the programming address in the resistive memory if there are still unprogrammed bits at '0'. This step also corresponds to steps 230 and 242 of the figure 2, which are thus doubled, one step being carried out for each operation, one of the “set” type and one of the “reset” type.

[0064] A particular embodiment of a writing method according to the present invention consists in carrying out the writing method represented by the figure 2 , steps 220 and 241 of programming in 1T1R mode in the resistive memory being carried out according to the figure 3 , this particular embodiment not comprising a step of verifying unprogrammed bits carried out just after step 320 of programming bits equal to 1, and / or a step of verifying unprogrammed bits carried out just after step 340 of programming bits equal to 0.

[0065] In another particular embodiment of the invention which can be combined with the embodiments previously described, the device implementing the writing method 300 in a resistive memory in 1T1R mode comprises a first writing circuit solely adapted to configure the cells of the resistive memory in an HRS state and a second writing circuit solely adapted to configure the cells of the resistive memory in an LRS state.In this particular embodiment, step 320 consisting of programming bits equal to 1 (operation of the “set” type used to program the cells in LRS state) and step 340 consisting of programming bits equal to 0 (operation of the “reset” type used to program the cells in HRS state) are carried out in parallel, that is to say at the same time by the first write circuit concerning the cells of the resistive memory to be programmed in an HRS state and by the second write circuit concerning the cells of the resistive memory to be programmed in an LRS state. Such an embodiment allows in particular a saving in writing time, the programming of data bits being able to be done by two write circuits at the same time during each programming step.

[0066] In another particular embodiment of the invention, the device implementing the writing method 200 in a resistive memory composed of 2T2R differential cells comprises a single writing circuit adapted to configure the cells of the resistive memory in an HRS or LRS state. In comparison with the embodiments where the device implementing the writing method 200 of the invention comprises two writing circuits, a device comprising a single writing circuit allows a saving in surface area and a reduction in static consumption in the production of this device. It will be noted that this “single” writing circuit, because it is capable of programming “0” and “1”, is in practice often constituted of several writing circuits associated for example with columns of different memory cells, in order to be able to carry out several writing operations in parallel in distinct memory cells.

[0067] Furthermore, it will be noted that the writing of the memory cells associated with a code word is, in a conventional manner in itself, carried out in a group of memory cells selected from the same address value which is provided by the host processor, the number of selected memory cells being for example equal to k+r (k being the size of the data and r the number of ECC bits). Thus, when a reading is carried out, in “2T2R” differential mode at an address indicated by the processor, a plurality of parallel differential readings of the memory cells associated with the indicated address are carried out in practice.

[0068] Some types of memory devices can be configured for storing data in "single" cells or "differential" cells, with the possibility of doubling the size of the memory if the data is stored in single. Thus, the address range provided for this type of memory is that corresponding to the maximum storage space, in 1T1R storage configuration, in practice this corresponds to an address space twice that required for a memory operating only in 2T2R storage mode. When such a dual storage mode device is configured in 1T1R storage mode, then writes and reads are all, always, carried out in 1T1R read mode and of course in 1T1R write mode only.Only when such a memory device is configured in 2T2R storage mode, the writing of a cell is done as described previously with 1T1R programming to program the "left" cells then the "right" cells and finally by doing a 2T2R differential reading if necessary to exit the write cycle, possibly without error if the differential reading is correct.

[0069] With a dual-mode memory device, reading the left and then right cells in 1T1R mode results in the host processor producing two different successive addresses, which could, for example, be differentiated only by an address bit (thus meaning "left" or "right").

[0070] According to an alternative embodiment, the selection of the "left" or "right" cells of the differential cells can also be transparent to the host processor and ensured by the memory controller. Thus, the host processor can request a write to a given address and it is the memory controller which will be responsible for carrying out the entire iterative process of verification writes / reads and which will therefore be responsible for controlling the row / column selection devices of the memory matrix to select either the left cells or the right cells in the 1T1R write and read phases. In other words, from outside the memory device, the processor can only see differential writes and reads at a selection address, and it is the memory controller which carries out all the sub-steps constituting a write operation requiring the transition to 1T1R mode.

[0071] Thus, in the case where we have a memory device that does not have a dual storage mode, the selection of "left" or "right" cells can be managed by the memory controller, transparently for the host processor as explained previously.

[0072] There figure 4represents a general system 400 for implementing the steps of a method of writing in a resistive memory composed of 2T2R differential cells according to an embodiment of the invention, which comprises an electronic subsystem 410, also called a host electronic subsystem or host processor, a memory controller 420 comprising an encoder and decoder for an error correcting code (ECC) and a 2T2R resistive memory 430. The host electronic subsystem may comprise one or more processor cores, a microcontroller or a programmable logic circuit also called FPGA (acronym for "Field Programmable Gate Array"). In addition or alternatively, the host subsystem may correspond to an ASIC (acronym for "Application-Specific Integrated Circuit") integrated circuit.During an operation of writing a word in a resistive memory such as that included in the calculation system 400, data bits of this word are emitted by the electronic subsystem 410 and sent to the memory controller 420. The data bits of a word emitted by the electronic subsystem 410 are first used by the ECC encoder, which will generate verification bits which are added after the data bits in order to form a code word. These verification bits will be stored at the same address in the resistive memory composed of 2T2R differential cells 430 as the data bits of the same word. These verification bits may in particular be used by an ECC decoder to correct possible storage errors of a word in the resistive memory in 2T2R mode 430 during the reading phase. The data bits and the check bits then constitute a code word which must be programmed into the cells of the 2T2R 430 resistive memory.

[0073] In the example of the method described in relation to the figure 2, in step 250, a verification reading in 2T2R differential mode of the selected differential cells is carried out and it is verified at least that the data read correspond to said initial data. This assumes that this verification is carried out internally of the memory device, by the memory controller. The memory controller then has direct access to the data provided by the reading devices which read the data bits and the ECC bits, that is to say has access to the bits which are sent to the decoder present in the memory device to correct any errors before outputting only the data bits, possibly corrected.The memory controller can then detect programming difficulties in the data bits or ECC bits and thus achieve a more precise identification of the bits that have been incorrectly programmed, in order to then focus on these unique bits that are more difficult to program in programming iteration phases.

[0074] According to an alternative embodiment, it is possible for the last step 250 to be carried out differently, by considering only the data leaving the ECC decoder. This alternative can in particular be envisaged in the case where it is the host processor which carries out the final verification and makes the final decision whether or not to accept the writing.

[0075] We can also consider a combination of the two variants, namely a verification of the code word by the memory controller with raising of a flag to the processor in the event of an error detected on the code word, followed by a verification of the data read by the processor, which may possibly decide to validate the writing anyway if the data read is correct, even though this required using the correction mechanism by the decoder.

[0076] An advantage of using a code word check by the memory controller is that it is possible to ensure that the write was satisfactory enough to have a written word that does not require correction by ECC, by the decoder. This allows more margin for correction by ECC to cope with errors that may creep into the memory over time. However, if the programmer of the application executed by the processor considers that the data will not be kept for very long, it is possible to be satisfied with a less "reliable" write, but which gives, during a subsequent reading, correct data thanks to the ECC correction. Here again, it is a compromise between reliability and write time that can be adjusted according to the application being executed.

[0077] This description illustrates a preferred implementation of the invention, but is not limiting. Examples are chosen to allow a good understanding of the principles of the invention and a concrete application, but are in no way exhaustive and must allow those skilled in the art to make modifications and implementation variants while retaining the same principles. Thus, for example, the different methods described can be implemented within the same device.

Claims

1. Method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells each comprising first and second sets of a resistor (R) and a selection transistor (T), the method comprising: - (210) generating an initial codeword from initial data bits and check bits generated from the data word, and initialising a counter for counting a number of programming operations, the number of programming operations corresponding to a maximum number of programming operations for said word in a group of selected differential cells; - (220) programming this initial codeword in the resistive memory in 1T1R mode, by selecting the first 1T1R sets of the selected differential cells, and then performing a 1T1R check read operation and incrementing or decrementing the counter for counting the number of programming operations; - (230) repeating the previous step (220) for as long as all of the bits of the initial codeword have not been correctly programmed and the maximum number of programming operations has not been reached; - (240) inverting the initial codeword and reinitialising the counter for counting the number of programming operations; - (241) programming the initial codeword inverted in the previous step (240) in the resistive memory in 1T1R mode, by selecting the second 1T1R sets of the selected differential cells, and then performing a 1T1R check read operation and incrementing or decrementing the counter for counting the number of programming operations; - (242) repeating the previous step (241) for as long as all of the bits of the inverted initial codeword have not been correctly programmed and the maximum number of programming operations has not been reached; - (250) performing a check read operation in 2T2R differential mode on the selected differential cells and checking at least that the read data corresponds to said initial data; and, depending on the result of the check, - (251) terminating the writing method or - (252) signalling an error in the writing method.

2. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to claim 1, wherein said check read operation in 2T2R differential mode includes checking all of the read bits of the codeword against the bits of the initial codeword.

3. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to any one of the preceding claims, wherein the step (230) of repeating the previous step (220) comprises the following sub-steps: - checking, by reading the resistive memory in 1T1R mode, whether there are still unprogrammed data and check bits; and - if there are still unprogrammed bits and if the maximum number of write operations to memory for said initial codeword has not been reached, repeating the step (220) of programming said initial codeword in the resistive memory in 1T1R mode; or - if there are not still unprogrammed bits or if the maximum number of write operations to memory for said initial codeword has been reached, continuing with the following step (240).

4. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to any one of the preceding claims, wherein the step (242) of repeating the previous step (241) comprises the following sub-steps: - checking, by reading the resistive memory in 1T1R mode, whether there are still unprogrammed data and check bits of the inverted initial codeword; and - if there are still unprogrammed bits and if the maximum number of write operations to memory for said inverted initial codeword has not been reached, repeating the step (241) of programming said inverted initial codeword in the resistive memory in 1T1R mode; or - if there are not still unprogrammed bits or if the maximum number of write operations to memory for said inverted initial codeword has been reached, continuing with the following step (250).

5. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to any one of the preceding claims, wherein the step (251) of terminating the writing method is performed if the data read in 2T2R mode corresponds to said initial data; and wherein the step (252) of signalling an error in the writing method is performed if the data read in 2T2R mode does not correspond to said initial data.

6. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to one of the preceding claims, the step (220) of programming the initial codeword in the resistive memory in 1T1R mode and / or the step (241) of programming the inverted initial codeword in the resistive memory in 1T1R mode comprising substeps of: - (310) reading, in 1T1R mode, from the resistive memory, the bits at the programming address of the codeword and comparing the bits read at said programming address and the bits of the codeword to be programmed, and - (320, 340) programming, in 1T1R mode, in the resistive memory, only the bits of the codeword that do not correspond to the read bits.

7. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to any one of the preceding claims, the step (220) of programming the initial codeword in the resistive memory in 1T1R mode or the step (241) of programming the inverted initial codeword in the resistive memory in 1T1R mode being performed by a single write circuit adapted to configure the cells of the resistive memory in an HRS or LRS state.

8. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to one of claims 1 to 6, the step (220) of programming the initial codeword in the resistive memory in 1T1R mode and / or the step (241) of programming the inverted initial codeword in the resistive memory in 1T1R mode being performed by a first write circuit adapted only to configure the cells of the resistive memory in an HRS state and, in parallel, by a second write circuit adapted only to configure the cells of the resistive memory in an LRS state.

9. The method (200) for writing a data word to a resistive memory consisting of 2T2R differential cells according to claim 8, the step (220) of programming the initial codeword in the resistive memory in 1T1R mode and / or the step (241) of programming the inverted initial codeword in the resistive memory in 1T1R mode being performed firstly by the first write circuit concerning the cells of the resistive memory to be programmed in an HRS state and then being performed secondly by the second write circuit concerning the cells of the resistive memory to be programmed in an LRS state, or vice versa.

10. A system comprising a resistive memory consisting of differential cells 2T2R each comprising first and second sets of a resistor (R) and a selection transistor (T), and a device for writing a data word into the resistive memory, the device comprising means which are configured to implement the steps of the writing method according to any one of the preceding claims.

11. The system according to Claim 10, wherein the means comprise a memory controller coupled to the resistive memory adapted to implement the step of a check read operation in 2T2R differential mode of the writing method according to any one of the preceding claims.

12. The system according to Claim 10 or 11, wherein the means comprise a host processor coupled to the resistive memory adapted to implement the step of a check read operation in 2T2R differential mode of the writing method according to any one of the preceding claims.