MULTI-STAGE AMPLIFIER CIRCUITS AND METHODS

Description

Technical field

[0001] The description relates to amplifier circuits, such as fully-differential amplifier circuits of the multistage operational transconductance amplifier (briefly, OTA) type.

[0002] One or more embodiments may be applied to a charge amplifier circuit suitable for detecting charge variation in capacitive sensors.Technological Background

[0003] Amplifier circuits such as OTAs are suitable for a wide set of electronic applications.

[0004] A drawback of existing OTA circuits lies in the existence of a plurality of possible stable bias points. Such a drawback may exist irrespective of the kind of transistors (e.g., PMOS or NMOS) used for an input differential-pair of the OTA.

[0005] For instance, there is an undesired stable bias point value when input and output common mode nodes are at a same constant value (e.g., VCM IN = VCM OUT = 0 for the NMOS input differential-pair or VCM IN = VCM OUT = VDD for the PMOS input differential-pair). Such an undesired bias point value can, for instance, be carried from the output to the input nodes of the OTA via a feedback circuit branch, in particular a resistive feedback branch.

[0006] As a result, a start-up phase of an OTA can be relevant in order to counter any risk of latching the amplifier in undesired bias conditions.

[0007] Even with an adequate start-up phase, a perturbation on the virtual ground of a multistage OTA during its normal operations, can still result in an undesired shutdown of the amplifier stage.

[0008] Document US 2018 / 152156 A1 discusses an operational amplifier and a differential amplifying circuit thereof.

[0009] The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and / or controls the current flowing therethrough.

[0010] Document WO 00 / 27029 A1 discusses a functional circuit such as an OP-amp that has a differential output. A common mode signal at the differential output is adjusted by means of a common mode feedback circuit coupled between the differential output and the common mode adjustment input. The common mode feedback circuit contains IGFETs, each having a channel and a backgate, each connection of the differential output being coupled to the backgate of a respective one of the IGFETS. Thus, the voltages at the outputs influence the current through the channel. The sum of the currents determines a feedback to the common mode control input.

[0011] Document US 2002 / 024384 A1 discusses the opamp with common mode feedback bias, including: a first differential pair M1 and M2 having first and second inputs; active load devices M3 and M4 coupled to the first differential pair M1 and M2; a common mode feedback circuit 20 coupled to the active load devices M3 and M4 for controlling the active load devices M3 and M4; a second differential pair M18 and M19 having a first input coupled to the first input of the first differential pair M1 and M2 and a second input coupled to the second input of the first differential pair M1 and M2; and current drivers M22 and M23 having control nodes coupled to the second differential pair M18 and M19 and outputs coupled to the active load devices M3 and M4.Object and summary

[0012] The invention is set out in the appended set of claims. An object of one or more embodiments is tc contribute in overcoming the aforementioned drawbacks.

[0013] According to one or more embodiments, that object can be achieved by means of a multistage amplifier circuit having the features set forth in claim 1 that follows. A startup circuit for a multi-stage amplifier circuit is part of such a circuit.

[0014] One or more embodiments may relate to a corresponding multi-stage amplifier circuit.

[0015] One or more embodiments may relate to a corresponding method. A start-up method for an OTA may be exemplary of such a circuit.

[0016] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

[0017] One or more embodiments may counter performance deterioration due to process-voltage-temperature (briefly, PVT) circuit variations.

[0018] One or more embodiments may facilitate increasing circuit robustness against non-idealities, such as noise and mismatch, for instance, which may otherwise reduce accuracy.

[0019] One or more embodiments may provide an effective improvement over existing solutions using a relatively simple arrangement.

[0020] One or more embodiments facilitate providing a start-up network without loss of performances.

[0021] One or more embodiments may facilitate providing a compact, area-saving solution.Brief description of the several views of the drawings

[0022] One or more embodiments will now be described, by way of non-limiting example only, with reference to the annexed Figures, wherein: Figure 1 is an exemplary diagram of a charge amplifier, Figure 2 is an exemplary circuit diagram of an operational transconductance amplifier, Figure 3 is an exemplary diagram of a charge amplifier with reset switches on its virtual ground, Figure 4 is an exemplary circuit diagram of an operational transconductance amplifier having a start-up circuit portion, Figure 5 is a circuit diagram exemplary of one or more embodiments of a startup circuit portion, forming part of the current invention as claimed, Figure 6 is a circuit diagram exemplary of a cascoded amplifier, Figure 7 is a circuit diagram exemplary of alternative embodiments of Figure 5, forming part of the current invention as claimed. Detailed description of exemplary embodiments

[0023] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0024] Reference to "an embodiment" or "one embodiment" in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

[0025] Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0026] Throughout the figures annexed herein, like parts or elements are indicated with like references / numerals and a corresponding description will not be repeated for brevity.

[0027] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0028] Figure 1 shows an exemplary diagram of a charge amplifier circuit 10 which may comprise: a bias node V R configured to be coupled to some voltage source, in a way per se known; a capacitive sensor 12 coupled to the reference node V R and having a differential, variable capacitance whose value is C 0 ±ΔC; and an operational transconductance amplifier (OTA) 10, which may have: a non-inverting input node V INp connected to the sensor 12 and coupled to a first output node V OUTn via a first feedback branch comprising a first RC network R F1 , C F1 , and an inverting input node V INn connected to the sensor 12 and coupled to a second output node V OUTp via a second feedback branch comprising a second RC network R F2 , C F2 .

[0029] An input VCM IN , respectively output VCM OUT , common mode voltage level of the OTA 10 As exemplified in Figure 1 can be expressed as: VCM IN = V INp + V INn 2 VCM OUT = V OUTp + V OUTn 2

[0030] Due to the presence of feedback RC networks R F1 , C F1 , R F2 , C F2 , it may be desirable to have equal input and output common mode voltage levels, that is VCM IN =VCM OUT =VCM.

[0031] As exemplified in Figures 2 and 3, a circuit diagram of an OTA 10 as exemplified in Figure 1 can comprise a multi-stage arrangement of electronic transistors.

[0032] For the sake of simplicity, embodiments are discussed herein with reference to a multi-stage arrangement comprising two (differential) stages, being otherwise understood that such a number of stages is purely exemplary and in no way limiting, as one or more embodiments may notionally comprise any number of stages.

[0033] For the sake of simplicity, one or more embodiments are discussed in the following mainly with respect to an OTA circuit implemented using NMOS transistor as differential-pair, being otherwise understood that such a type of transistor technology is purely exemplary and in no way limiting. One or more embodiments may use PMOS or any other kind of transistor technology.

[0034] As exemplified in Figure 2, a two-stage OTA circuit 10 comprises an arrangement of, e.g., NMOS, transistors, the circuit arrangement comprising: a pair of differential input nodes V INp , V INn of the OTA 10, a first differential stage comprising a first differential pair of transistors M 1 , M 2 having a respective current path between a respective drain terminal and a common source terminal V TAIL , the input nodes of the OTA 10 coupled to the respective control nodes V INp , V INn of the first differential pair of transistors M 1 , M 2 , at plurality of current generators, e.g., at least three current generators M 0 , M 7 , M 8 comprising transistors configured to mirror a "tail" current at the common source terminal V TAIL of the first differential pair of transistors M 1 , M 2 , a second differential stage comprising a second differential pair of transistors M 5 , M 6 having respective control nodes V 1p , V 1n coupled to respective drain terminals of the first differential pair of transistors M 1 , M 2 , the transistors M 5 , M 6 having a respective channel path between a respective drain node coupled to a bias voltage VDD and respective output nodes V OUTp , V OUTn ; the respective output nodes V OUTp , V OUTn of the transistors M 5 , M 6 are coupled to their respective control nodes V 1p , V 1n via a respective feedback capacitor C C ; two active load stages M 3 , M 4 coupled to drain terminals of the first differential pair of transistors M 1 , M 2 - that is to the control terminals V 1p , V 1n of the second differential pair of transistors M 5 , M 6 - and to a reference / bias voltage VDD; each active load stage M 3 , M 4 comprises a respective pair of first transistors M 3A , M 4A and second transistors M 3B , M 4B , wherein: i) the control terminal of first transistors M 3A , M 4A is connected to a control node V CTRL of the respective active stage M3, M4, and ii) respective second transistors M 3B , M 4B are coupled to the bias node VDD and configured to operate as current generators of a reference current; and an output common mode feedback (OCMFB) stage 20 coupled to the control terminal V CTRL of the two active load stages M 3 , M 4 , the OCMFB stage 20 configured to facilitate stability of a bias point chosen by design, e.g., a reference common mode voltage level VCM=VCM 0 .

[0035] In one or more embodiments, in a manner per se known to those of skill in the art, an arrangement of active loads M 3 , M 4 as exemplified in Figure 2 can facilitate compensation of the common-mode feedback loop and current savings on the second, output stage of the OTA circuit.

[0036] In addition to the selected stable common mode voltage level VCM 0 , the circuit of Figure 2 can have a second, parasitic, stable common mode voltage level such as VCM=0 Volts. This may result from nodes V 1p and V 1n - when the input nodes are grounded, that is V INp -V INn =0 Volts - being "pulled up" to the bias voltage level VDD by the second transistors M 3B , M 4B of the active loads M 3 , M 4 (whose control nodes are not driven by the OCMFB network 20). Consequently, also output nodes can be grounded, that is V OUTp =V OUTn =0 Volts, with the parasitic value becoming the common mode voltage level as a result. As mentioned, this parasitic bias point can be carried to the input nodes of the OTA as exemplified in Figure 1 via the feedback branches, in particular via feedback resistances R F1 and R F2 , introducing a positive common mode feedback and latching the circuit in the state VCM IN =VCM OUT =0 Volts.

[0037] A way of countering the risk of latching the OTA on the parasitic stable point involves introducing a start-up phase comprising a reset phase in order to force the input nodes V INp , V INn of the OTA 10 to the chosen common mode voltage level, e.g., VCM=VCM 0 . As exemplified in Figure 3, this may involve providing the OTA circuit 10 of common-mode nodes VCM and coupling a pair of switches S1, S2 between such common mode nodes VCM and the input nodes of the OTA 10, the switches configured to be driven by a reset signal RST from a start-up-phase logic (not visible in the Figure).

[0038] As often the case in various application, in particular in micro-electro-mechanical systems (MEMS), common mode stimulation can still take place on the virtual ground of the OTA during normal operation, with this event possibly resulting in shutdown of the amplifier 10.

[0039] A first approach to these issues may involve introducing a start-up circuit 40, as exemplified in Figure 4. In the example considered, the start-up circuit 40 may comprise a pair of startup transistors M 9A , M 9B , e.g., using NMOS technology, having respective control terminals coupled therebetween and to a biasing node V BIASn , the pair of startup transistors M 9A , M 9B having respective current paths therethrough between a respective drain terminal coupled to the respective control terminal V 1p , V 1n of the second differential pair M 5 , M 6 and the common source terminal V TAIL of the first differential pair of transistors M 1 , M 2 .

[0040] As exemplified in Figure 4, the start-up circuit 40 is designed so that the startup transistors M 9A , M 9B are: in a first, e.g., OFF-state, when the input nodes V INp , V INn of the OTA 10 are biased at the chosen bias point, e.g., VCM=VCM 0 , and in a second, e.g., ON-state, when a common mode perturbation causes a voltage drop at the input nodes V INp , V INn of the OTA 10, so that when the common source node V TAIL of the first differential pair M1, M2 "follows" this drop, a current flow travels in the start-up circuit transistors M 9A , M 9B , this current flow acting as a "pull-down" for the control terminals V 1p , V 1n of the second differential pair of transistors M 5 , M 6 , balancing the "pull-up" by the respective second transistors M 3B , M 4B of the active loads M 3 , M 4 .

[0041] Optionally, the OCMFB circuit 20 can be also present (although not visible in Figure 4) in addition to the startup circuit 40. In such a case, the startup circuit 40 is effective as a function of what portion of bias current is controlled by the OCMFB circuit 20 driving first transistors M 3A , M 4A of the active load stages M 3 , M 4 . For instance, a low current managed by the OCMFB circuit 20 may result in an easier stabilization and a lower current on the output branches of the OTA 10, while at the same time posing constrains to the start-up circuit 40, in particular in terms of high conductivity to counter the pull-up effect of the second transistors M 3B , M 4B of the active load stages M 3 , M 4 . These constrains may present cost in terms of area occupancy of the start-up circuit, which may take from 50% to 100% of the dimension of the input differential pair M1, M2. Maintaining the start-up circuit 40 sufficiently highly conductive over any PVT situation may result in leavening the startup circuit 40 turned on also when the correct bias point is recovered from any given input common mode variation, with a negative impact on the input transconductance of the stage 10. This may lead to a subsequent reduction of the performances of the OTA 10 in terms of bandwidth and noise, for instance.

[0042] As exemplified in Figure 5, an improved start-up circuit 50, e.g., in NMOS technology, which is used in a multi-stage amplifier, according to the invention as claimed, in place of circuit 40, comprises: a startup differential stage M SU1 , M SU2 , having a pair of input nodes V SUp , V SUn and a pair of output nodes V 1p , V 1n configured to be coupled to the control terminals V 1p , V 1n of the second differential pair of transistors M 5 , M 6 of the OTA 10, the startup differential stage comprising a differential pair of transistors M SU1 , M SU2 having respective control terminals connected to the input nodes V SUp , V SUn of the startup differential stage, the differential pair of transistors M SU1 , M SU2 having a respective current path therethrough between a respective drain node, at the output node of the startup differential stage, and a common source node; a further pair of transistors M SU4 , M SU5 , having respective control terminals coupled to a biasing node V BIASsu and having respective current paths therethrough between the output nodes V 1p , V 1n of the startup differential circuit and the common source node V TAIL of the first differential pair of transistors M 1 , M 2 of the first stage of the OTA 10; a current mirror transistor M SU3 coupling the common source node of the start-up differential pair with the control terminals of the further pair of transistors M SU4 , M SU5 .

[0043] As exemplified in Figure 5, when there is a common mode voltage drop at the input nodes V INn , V INp of the OTA 10, the control terminals V 1p , V 1n of the second differential pair of transistors M 5 , M 6 are "pulled-up" to a higher voltage level, leading to a current flowing through start-up differential transistors M SU1 and M SU2 ; this can increase their respective bias voltage V GS , changing both the voltage level at the control terminals V INp , V INn voltage and the voltage level at the common source terminal. As a result, such a change during the common mode perturbation is injected as a current in the diode M SU3 (e.g., using a current-reuse approach) and mirrored thereby and via the further transistors M SU4 and M SU5 back to the control terminals V 1p and V 1n of the second differential pair of transistors M 5 , M 6 , re-balancing their input common-mode variation. This is indicative of an increase of the overall pull-down effectiveness of the start-up network 50.

[0044] In one or more embodiments as exemplified in Figure 5, the mirroring ratio between M SU3 and the pair M SU4 , M SU5 can be used as free parameter to optimize dimension of the transistors.

[0045] Re-balancing the second differential pair of transistors M 5 , M 6 via applying a "pull-down" effect on their control terminals V 1p , V 1n as well as on the source terminals V TAIL facilitates operating the start-up circuit 50 in a same manner notionally for any PVT situation. Moreover, this can be possible while using a reduced amount of (circuit) area in comparison with a solution as in Figure 4.

[0046] As discussed in the foregoing an OTA circuit 10 as exemplified in Figure 2 can be realized with any transistor technology. As exemplified in Figure 6, this includes the known cascode technology, where: the first differential stage M1, M2 is implemented using a pair of cascode arrangements of a respective common-emitter stage M NC1 , M NC2 , feeding into a respective common-base stage M 1s , M 2s with a respective differential cascode node V CN1 , V CN2 interposed therebetween, in the two active loads M3, M4, the first transistors M 3A , M 4A are implemented using a pair of cascode arrangements of a respective common-emitter stage M PC1 , M PC2 feeding into a respective common-base stage M 3As , M 4As , with a respective cascode node V CP1 , V CP2 interposed therebetween.

[0047] Figure 7 is a circuit diagram of an alternative start-up circuit 70 suitable for use in combination with the cascode implementation (see Figure 6) of the OTA according to the invention as claimed.

[0048] As exemplified in Figure 7, the cascode start-up circuit 70 may comprise: a startup differential stage M SU1 , M SU2 , having a pair of input nodes V SUp , V SUn and a pair of output nodes V CP1 , V CP2 configured to be coupled to the control terminals V 1p , V 1n of the cascode nodes of the first transistors of the active loads M3, M4 of the OTA 10, the startup differential stage comprising a differential pair of transistors M SU1 , M SU2 having respective control terminals connected to the input nodes V SUp , V SUn of the startup differential stage, the differential pair of transistors M SU1 , M SU2 having a respective current path therethrough between a respective drain node, at the output node of the startup differential stage, and a common source node; a further pair of transistors M SU4 , M SU5 , having respective control terminals coupled to a biasing node V BIASsu and having respective current paths therethrough between differential cascode nodes V CP1 , V CP2 and the common source node V TAIL of the first differential pair of transistors M 1 , M 2 of the first stage of the OTA 10; a current mirror transistor M SU3 coupling the common source node of the start-up differential pair M SU1 , M SU2 with the control terminals of the further pair of transistors M SU4 , M SU5 .

[0049] It will be otherwise understood that the various individual implementing options exemplified throughout the figures accompanying this description are not necessarily intended to be adopted in the same combinations exemplified in the figures. One or more embodiments may thus adopt these (otherwise non-mandatory) options individually and / or in different combinations with respect to the combination exemplified in the accompanying figures.

[0050] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection. The extent of protection is defined by the annexed claims.

Claims

1. A multi-stage amplifier circuit (10), comprising: a pair of input nodes (VINp, VINn) and a pair of output nodes (VOUTp, VOUTn), a cascade of differential stages (M1, M2, M5, M6) comprising a first differential stage (M1, M2) coupled to said pair of input nodes (VINp, VINn) of the multi-stage amplifier circuit (10) and at least one further differential stage (M5, M6, M7, M8) coupled to said pair of output nodes (VOUTp, VOUTn), wherein said first differential stage (M1, M2) comprises a first differential couple of transistors having respective control nodes at said pair of input nodes (VINp, VINn) of the multi-stage amplifier (10) and having a first common source terminal (VTAIL) therebetween, a startup circuit (50; 70) coupled to the first differential stage (M1, M2), the startup circuit (50; 70) including: a pair of input nodes (VSUp, VSUn) and at least two output nodes (V1p, V1n; VCP1, VCP2, VCN1, VCN2) coupled to said multi-stage amplifier circuit (10), a startup differential stage comprising a second differential pair of transistors (MSUp, MSUn) having respective control terminals coupled to said pair of input nodes (VSUp, VSUn) of the startup circuit (50; 70), each transistor in said second differential pair of transistors (MSUp, MSUn) having a respective current path therethrough between a respective output node (V1p, V1n, VCP1, VCP2) in said at least two output nodes of the startup circuit (V1p, V1n; VCP1, VCP2, VCN1, VCN2) and a second common source terminal, the startup differential stage being configured to sense (MSU1, MSU2) a common mode voltage drop at said first differential stage (M1, M2) of said multi-stage amplifier circuit (10), current mirror circuitry (MSU3, MSU4, MSU5) coupled to said second common terminal of said second differential pair of transistors (MSUp, MSUn) and having two output nodes (V1p, V1n; VCN1, VCN2) in said at least two output nodes of the startup circuit (V1p, V1n; VCP1, VCP2, VCN1, VCN2), the current mirror circuitry (MSU3, MSU4, MSU5) comprising a plurality of transistors, comprising: a further pair of transistors (MSU4, MSU5) having respective control terminals coupled to a biasing node (VBIASsu) and having respective current flow paths therethrough between said at least two output nodes of the startup circuit (V1p, V1n; VCN1, VCN2) and the first common source terminal (VTAIL) of said first differential stage (M1, M2), and a diode-connected transistor (MSU3) coupling said second common source terminal of said second differential couple of transistors (MSUp, MSUn) of said startup differential stage to respective control terminals of transistors of the further couple of transistors (MSU4, MSU5), wherein: - the at least two output nodes of the startup circuit (V1p, V1n; VCN1, VCN2) are coupled to said first differential stage (M1, M2) of said multi-stage amplifier circuit (10), and - said current mirror circuitry (MSU3, MSU4, MSU5) is configured to perform current mirroring of a current variation at the common source of said startup differential stage, compensating as a result said sensed common mode voltage drop at said first differential stage (M1, M2) of the multi-stage amplifier (10).

2. The multi-stage amplifier circuit (10) of claim 1, wherein said first differential stage (M1, M2) comprises a first differential pair of transistors with a first transistor (M1) and a second transistor (M2) each having a respective current path between a respective output drain terminal and the first common source terminal (VTAIL) , and wherein the first output node of the startup circuit (V1p) is coupled to a first output drain terminal of said first transistor (M1) of the first differential pair of transistors of said first differential stage (M1, M2) and the second output node of the startup circuit (V1n) is coupled to a second output drain terminal of the second transistor (M2) of said first differential pair of transistors of the first differential stage (M1, M2).

3. The multi-stage amplifier circuit (10) of claim 1, wherein: said first differential stage (M1, M2) comprises a first differential pair of transistors each having a respective current path therethrough between a respective output drain terminal and the first common source terminal (VTAIL), the multi-stage amplifier circuit (10) further comprises active load stages (M3, M4) coupled between said output drain terminals of the first differential stage (M1, M2) and input nodes of the at least one further differential stage (M5, M6, M7, M8), each active load stage (M3, M4) comprising a switch (M3A, M4A) and a current generator (M3B, M4B) coupled therebetween, and said startup circuit (50; 70) is further coupled to at least one of said further differential stage (M5, M6) and said active load stages (M3, M4).

4. The multi-stage amplifier circuit (10) of claim 3, wherein the first differential stage (M1, M2) comprises a pair of cascode arrangements of a respective common-emitter stage (MNC1, MNC2) feeding into a respective common-base stage (M1s, M2s) with differential cascode nodes (VCN1, VCN2) interposed therebetween, and wherein said switches (M3A, M4A) of said active load stages (M3, M4) are implemented using a pair of cascode arrangements of a respective common-emitter stage (LPC1, MPC2) feeding into a respective common-base stage (M3As, M4As) with a respective cascode node (VCP1, VCP2) interposed therebetween, wherein said startup circuit (50, 70) has a first pair of output nodes (VCP1, VCP2) coupled to said cascode nodes (VCP1, VCP2) of said switches (M3A, M4A) of said active load stages (M3, M4) and a second pair (VCN1, VCN2) of output nodes coupled to said differential cascode nodes (VCN1, VCN2) of said first differential stage (M1, M2).

5. The multi-stage amplifier circuit (10) of claim 3 or claim 4, wherein said active load stages (M3, M4) have at least one control terminal (VCTRL) configured to drive said switches (M3A, M4A) in said active load stages (M3, M4), and wherein the multi-stage amplifier circuit (10) comprises an output common mode feedback stage (20), OCMFB, coupled to the control terminal (VCTRL) of the active load stages (M3, M4).

6. The multi-stage amplifier circuit (10) according to claim 1, wherein: - said at least two output nodes of the startup circuit (V1p, V1n; VCP1, VCP2, VCN1, VCN2) comprise two output nodes (V1p, V1n), and - said two output nodes of said current mirror circuitry (MSU3, MSU4, MSU5) are each coupled to a respective one of said output nodes of the first differential pair of transistors (MSUp, MSUn).

7. The multi-stage amplifier circuit (10) according to claim 1, wherein the current mirror circuitry (MSU3, MSU4, MSU5) has a current mirroring parameter which varies as a function of respective size ratios of transistors in the plurality of transistors in current mirror circuitry (MSU3, MSU4, MSU5).

8. A method of operating of a multi-stage amplifier circuit (10) according to any of claims 1 to 7, the method comprising: sensing (MSUp, MSUn) the common mode voltage drop at said first differential stage (M1, M2) of said multi-stage amplifier circuit (10) via said startup differential stage configured to sense said common mode voltage drop, performing current mirroring (MSU3, MSU4, MSU5) of a current variation at said common source of said startup differential stage, and compensating (V1p, V1n; VCP1, VCP2, VCN1, VCN2), as a result of said current mirroring (MSU3, MSU4, MSU5), said sensed common mode voltage drop at said first differential stage (M1, M2) of said multi-stage amplifier circuit (10).