Entropy source with on-board calculation methods for generating true random numbers

Description

Technical field

[0001] This description relates generally to electronic circuits, and more particularly to the sources of entropy implemented in electronic circuits to generate random numbers. Prior art

[0002] Many electronic circuits implement a True Random Number Generation (TRNG) function. To do this, these circuits have a source of entropy from which random information or randomness is extracted. This random information is then used to generate truly random numbers. For example, the resulting truly random numbers are used to generate encryption keys, signatures, etc.

[0003] In some of the circuits described above, the source of entropy is the clock jitter of a ring oscillator. Ring oscillators are widely used due to their simplicity and the familiarity of their theoretical models. The uncertainty (or jitter) in the actual period of a ring oscillator output signal relative to the theoretical period of that signal is exploited as a source of randomness. This uncertainty increases with the number of accumulated periods (or equivalently the accumulation time).

[0004] The physical phenomena that cause jitter are well documented in the literature. The model generally used as a theoretical basis is that proposed by Hajimiri in the article "Jitter and phase noise in ring oscillators" in the journal IEEE J. Solid-State Circuits, vol. 34, no. 6, June 1999. This model defines the susceptibility function of the output signal of a ring oscillator to generate phase noise in the face of a disturbance. More concretely, only a disturbance occurring during the transient phases (rising or falling) of the output signal is capable of inducing phase noise in this signal. Furthermore, the model describes the effect of the different physical sources of noise on the accumulated jitter.These phenomena are divided into thermal noise from thermal agitation and low-frequency noise ("flicker") induced by the charging / discharging of the gate oxide traps of metal-oxide semiconductor (MOS) transistors implementing the ring oscillator or by the diffusion of carriers in the channel of these transistors. Indeed, the accumulated jitter has two regions: a region varying linearly with the variance of the jitter, which corresponds to the thermal noise, and a region varying quadratically with the variance of the jitter, which corresponds to the low-frequency noise ("flicker"). To use jitter as an entropy source for the generation of truly random numbers, only the thermal component of the jitter remains interesting because it is the only completely random one.Indeed, the low-frequency noise component ("flicker") is not interesting because low-frequency noise is self-correlated and detrimental to the predictability of the generated randomness.

[0005] Thus, in the circuits described above where the entropy source for generating truly random numbers is based on the jitter of a ring oscillator, it is desirable to characterize the entropy source, i.e. the jitter, to discriminate the amplitude of the thermal component of the jitter.

[0006] There are embedded methods to characterize, in a circuit, an entropy source based on the jitter of a first ring oscillator of the circuit by using a second oscillator of the circuit which is identical to the first.

[0007] A first method consists of measuring the number of oscillations of the first oscillator RO1 during Q oscillations of the second oscillator, the Q factor being obtained through a frequency divider. This method is presented in the article "On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models", by P. Haddad, Y. Teglia, F. Bernard, and V. Fischer, presented at "Design, Automation & Test in Europe Conference & Exhibition (DATE)", in 2014, in Dresden.

[0008] The jitter is then characterized using the Allan variance, that is to say the variance calculated on the difference between two consecutive values, namely here two consecutive values ​​available at the output of a counter clocked by the output signal of the first oscillator and reset every Q periods of the output signal of the second oscillator by the output signal of the frequency divider by Q. The use of the Allan variance makes it possible to circumvent the problems related to the convergence of the models while respecting a condition of stationarity. The Allan variance is plotted as a function of the number Q of accumulation periods and then follows a law (or curve or function) very similar to that of the model presented previously.More precisely, the Allan variance plotted as a function of the Q factor includes a linear part corresponding to the thermal noise, a quadratic part corresponding to the flicker noise, and a noise floor corresponding to the quantization noise inherent in any acquisition. By performing a quadratic regression of the plotted curve to approximate it by a function of the type σ(Q)^2=a0+a1.Q+a2.Q ^2, with σ(Q) the Allan variance as a function of the accumulation Q, it is possible to obtain the coefficients a0, a1 and a2 which represent the coefficients respectively for the quantization noise, for the thermal noise and for the low-frequency noise ("flicker"). Obtaining the coefficients a0, a1 and a2 therefore amounts to characterizing the source of entropy, i.e. the jitter of the first oscillator.

[0009] However, this first method has the disadvantage that the contribution of the frequency divider circuit to the final noise is not known.

[0010] Furthermore, in this first method, the characterization of the jitter of the first oscillator is implemented by a circuit arranged next to the processing of the entropy source, which requires a significant additional surface.

[0011] A second method is to sample the output signal of the first oscillator with a D-type synchronous flip-flop clocked at the frequency of the second oscillator. The output signal of the flip-flop is then a periodic signal whose average period Tm is inversely proportional to the difference between the periods of the two oscillators. More specifically, the length of the period Tm in number H of periods of the oscillator signal is such that H = T1 / (T1-T2), with T1 and T2 the average value of the periods of the first and second oscillators respectively. Then, a variance is calculated on the resultant of an EXCLUSIVE OR operation between two values ​​of the output signal of the flip-flop separated from each other by G periods of the second oscillator.The variance as a function of G then has two parts, a part varying linearly with G, which corresponds to the thermal noise, and a part varying quadratically with G, which corresponds to the low-frequency noise ("flicker"). This method is presented in the article "Embedded Evaluation of Randomness in Oscillator Based Elementary TRNG", by V. Fischer and D. Lubicz, presented in "Advanced Information Systems Engineering", vol. 7908, Springer Berlin Heidelberg, 2014, pp. 527-543. In the same way as before, it is possible to characterize the source of entropy, thus the jitter of the first oscillator, by performing a quadratic regression of the variance plotted as a function of G.

[0012] However, this second method has the disadvantage of being based on frequency ratios which are not controlled but suffered, and consequently the precision of this second method is low and uncontrollable between different circuits.

[0013] Furthermore, in this second method, as in the first method, the characterization of the jitter of the first oscillator is implemented by a circuit arranged next to the processing of the entropy source, which requires a significant additional surface area.

[0014] Thus, in the two known circuits and methods described above which make it possible to characterize an entropy source based on the jitter of a ring oscillator, with a view to ensuring a truly random generation of randomness, have drawbacks. This is more generally the case of the known circuits and methods making it possible to characterize, in an embedded manner, the jitter of a ring oscillator, that is to say making it possible to characterize, in an embedded manner, an entropy source. Summary of the invention

[0015] There is a need to overcome some or all of the drawbacks of known circuits and known methods implemented in these known circuits for characterizing, in an embedded manner, an entropy source when the entropy source is based on the jitter of a ring oscillator.

[0016] An embodiment overcomes all or part of the drawbacks of known circuits and known methods implemented in these known circuits for characterizing, in an embedded manner, an entropy source when the entropy source is based on the jitter of a ring oscillator.

[0017] One embodiment provides an electronic device comprising: an entropy source comprising: a first ring oscillator and a second ring oscillator identical to the first ring oscillator, and a synchronous flip-flop configured to provide an output signal corresponding to a sampling of an output of the first oscillator at a frequency of an output of the second oscillator; a counter configured to provide, for each period of the output signal of the flip-flop, a value equal to a number of periods of the second oscillator counted during said period of the output signal of the flip-flop; a first circuit configured to modify, during a first phase, a period of at least one of the two oscillators on the basis of the values ​​provided by the counter so that an average deviation between the periods of the two oscillators is equal to a target deviation;and a second circuit configured to receive the values ​​provided by the counter and to characterize, during a second phase and from said values, an Allan variance on the output of the counter.;

[0018] According to one embodiment, the target deviation is determined at least in part by a ratio between the jitter and the period of the first oscillator and / or by a target measurement accuracy.

[0019] According to one embodiment, the two oscillators are implemented in complementary metal-oxide-semiconductor technology on a fully depleted semiconductor on insulator, preferably on a fully depleted silicon on insulator.

[0020] According to one embodiment, the first circuit is configured to control back gates of at least one delay element of at least one of the two oscillators to modify the average deviation between the periods of the two oscillators.

[0021] According to one embodiment, the second circuit is configured, when characterizing the Allan variance, to: calculating a first Allan variance value on several successive values ​​provided by the counter; calculating a second Allan variance value on several sums of K1 successive values ​​provided by the counter; receiving a third theoretical Allan variance value or calculating a third Allan variance value on several sums of K2 successive values ​​provided by the counter; and calculating three coefficients of a quadratic curve characterizing the Allan variance from at least said first, second and third Allan variance values.

[0022] According to one embodiment, the second circuit is configured to sum K successive values ​​provided by the counter and to provide a low-order bit of said sum, K being determined by a target minimum entropy.

[0023] According to one embodiment, the device further comprises: a first alarm circuit configured to compare each value supplied by the meter to a first threshold and to trigger a first alarm when said value is greater than the first threshold; and / or a second alarm circuit configured to calculate an Allan variance value from the output values ​​of the meter and a corresponding Allan variance value using the Allan variance characterized by the second circuit, then to compare a difference between these two calculated values ​​to a second threshold and to trigger a second alarm if the difference between these two calculated values ​​is greater than the second threshold.

[0024] Another embodiment provides a method of characterizing an entropy source comprising: a first ring oscillator and a second ring oscillator identical to the first ring oscillator, and a synchronous flip-flop providing an output signal corresponding to a sampling of an output of the first oscillator at a frequency of an output of the second oscillator, the method comprising: providing, with a counter and at each period of the output signal of the flip-flop, a value equal to a number of periods of the second oscillator counted during said period of the output signal of the flip-flop; a first phase consisting of modifying, with a first circuit and on the basis of the values ​​provided by the counter, a period of at least one of the two oscillators so that an average deviation between the periods of the two oscillators is equal to a target deviation; and a second phase consisting of characterizing, by a second circuit and from the values ​​provided by the counter, an Allan variance of the output of the counter.

[0025] According to one embodiment, the target deviation is determined at least in part by a ratio between the jitter and the period of the first oscillator and / or by a target measurement accuracy.

[0026] According to one embodiment, the two oscillators are implemented in complementary metal oxide semiconductor technology on completely depleted semiconductor on insulator, preferably on completely depleted silicon on insulator.

[0027] According to one embodiment, the first circuit controls back gates of at least one delay element of at least one of the two oscillators to modify the average deviation between the periods of the two oscillators.

[0028] According to one embodiment, the Allan variance characterization comprises: calculating, by the second circuit, a first Allan variance value on several successive values ​​provided by the counter; calculating, with the second circuit, several sums of K1 successive values ​​provided by the counter and a second Allan variance value on said several sums of K1 successive values; receiving, by the second circuit, a third theoretical variance value or calculating, with the second circuit, several sums of K2 successive values ​​provided by the counter and a third Allan variance value on said several sums of K2 successive values; and calculating, by the second circuit, three coefficients of a quadratic curve characterizing the Allan variance from at least said first, second and third Allan variance values.

[0029] According to one embodiment, the method further comprises a calculation by the second circuit of a sum of K successive values ​​provided by the counter and a provision by the second circuit of a least significant bit of the sum, K being determined by a target minimum entropy.

[0030] According to one embodiment, the method further comprises: comparing, by a first alarm circuit, each value provided by the counter with a first threshold and triggering, by the first alarm circuit, a first alarm if a value provided by the counter is greater than the threshold; and / or calculating, by a second alarm circuit, an Allan variance value from the output values ​​of the counter and a corresponding Allan variance value using the characterized Allan variance, comparing, by the second alarm circuit, a difference between the two calculated Allan variance values ​​with a second threshold, and triggering, by the second alarm circuit, a second alarm if the difference is greater than the second threshold. Brief description of the drawings

[0031] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there Figure 1 represents a circuit according to an exemplary embodiment; the Figure 2 illustrates, by means of a flowchart, an exemplary embodiment of a method for characterizing an entropy source of the circuit of the Figure 1 ; there Figure 3 represents implementation details of a part of the circuit of the Figure 1 according to one embodiment; the Figure 4 represents implementation details of another part of the circuit of the Figure 1 according to one embodiment; the Figure 5 represents an embodiment of an alarm circuit usable in the circuit of the Figure 1 ; and the Figure 6represents an embodiment of another alarm circuit usable in the circuit of the Figure 1 . Description of the embodiments

[0032] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the usual methods and circuits using an entropy source for the generation of truly random numbers have not been detailed, the embodiments and variants described here being compatible with these usual methods and circuits.

[0034] Unless otherwise specified, when two elements are connected together, this means directly connected without intermediate elements other than conductors, and when two elements are connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0037] It is proposed here to characterize, in an embedded manner, an entropy source based on the jitter of a first ring oscillator. For this, a device is provided comprising the first oscillator, a second oscillator identical to the first and a flip-flop sampling the output signal of the first oscillator at the frequency of the second oscillator. The device comprises a counter configured to measure the duration, in number N of periods T2 of the second oscillator, of each period T of the output signal of the flip-flop. The device further comprises a circuit configured to control, on the basis of the output values ​​of the counter, the period T1 of the first oscillator and / or the period T2 of the second oscillator so that the average number Nm of periods T2 per period T of the output signal of the flip-flop is equal to a target value, i.e. a circuit configured to set the average period Tm of the output signal of the flip-flop to a target value.In other words, the circuit controls the difference between the value of the period T1 and the value of the period T2 to make it equal to a target difference, this target difference being determined at least in part by a ratio between the jitter of the first oscillator and its period T1 and / or by a target precision of measurement of the jitter of the first oscillator by the second oscillator. The device further comprises another circuit configured to characterize, after the period Tm has been set to the desired value, the jitter of the first oscillator from the output values ​​of the counter. More particularly, this circuit is configured to characterize the Allan variance on the output of the counter, that is to say to calculate the coefficients b0, b1 and b2 of a quadratic regression of the Allan variance as a function of the accumulation Nm.As an example, to calculate these coefficients, the circuit uses three Allan variance values ​​to calculate the coefficients b0, b1 and b2, a first value calculated on the output values ​​of the counter, a second value calculated from the output values ​​of the counter, and a third theoretical value or obtained from the output values ​​of the counter.

[0038] Fixing the value Nm, therefore the difference between the values ​​of periods T1 and T2, makes it possible to avoid using a frequency divider which has an influence on the measurement and to control the frequency ratios used to characterize the source of entropy, i.e. the jitter of oscillator RO1.

[0039] There Figure 1 illustrates, schematically and in the form of blocks, an example of an embodiment of a circuit 1.

[0040] Circuit 1 consists of two identical ring oscillators RO1 and RO2. Oscillator RO1, respectively RO2, provides a periodic output signal S1, respectively S2.

[0041] Circuit 1 further comprises a synchronous flip-flop FF (D flip-flop), for example of type D. The FF flip-flop is configured to sample signal S1 at the frequency of signal S2.

[0042] In other words, the FF flip-flop is configured to update an output signal S3 at each start of a period of signal S2 with the binary value of signal S1, each start of a period of signal S2 corresponding to an active edge of signal S2, for example a rising edge. Between two successive updates of signal S3, signal S3 is maintained at its current value, i.e. the value taken by signal S3 during the first of the two successive updates.

[0043] For example, the FF flip-flop includes a data input D configured to receive the signal S1, a synchronization (timing) input CK for updates to the signal S3 configured to receive the signal S2, and a Q output configured to provide the signal S3.

[0044] The two oscillators RO1 and RO2 and the flip-flop FF form an entropy source 100. The randomness extracted from the entropy source 100 is generated from the value of the period T of the signal S3. The signal S3 is a periodic signal having a mean period Tm whose mean duration Nm in number of periods of the signal S2 is inversely proportional to the difference between the periods T1 and T2, according to the formula Nm = T1 / (T1-T2). The signal S3 has an instantaneous period T which varies with the jitter of the signal S1. Thus, the measurement of the period T, that is to say of the duration of the period T, is representative of the jitter of the signal S1.

[0045] The entropy source 100 is a structure, for example, designated by the acronym COSO (from the English "COherent Sampling ring Ocillator"), which is used in coherent sampling ring oscillator true random number generator circuits (COSO TRNG from the English "COherent Sampling ring Ocillator True Random Number Generator").

[0046] To measure the period T of the signal S3, the circuit 1 comprises a circuit (or counter) COUNTER. The circuit COUNTER is configured to provide, for each period T of the signal S3, a value N, for example in the form of a digital word, equal to the number of periods T2 of the signal S2 counted during the period T of the signal S3. In other words, the circuit COUNTER is configured to measure the duration of each period T of the signal S3 in number N of periods T2 of the signal S2.

[0047] For example, the COUNTER circuit comprises a reset input receiving the signal S3, a synchronization input C receiving the signal S2 and an output O providing the counted values ​​N. At each start of period T2 of the signal S2, for example at each rising edge of the signal S2, the COUNTER circuit increments the current counting value by one unit. At each start of period T of the signal S3, for example at each rising edge of the signal S3, the COUNTER circuit resets the current counting value to zero. Preferably, the value N available at the output of the COUNTER circuit, on the output O, is updated from the current counting value at each start of period of the signal S3, just before this current counting value is reset to zero.In other words, the value N available at the output of the COUNTER circuit is updated at the start of each period T of the signal S3 with the value of the number of periods T2 of the signal S2 counted during the previous period T.

[0048] The device 1 further comprises a FB CTRL circuit. The FB CTRL circuit is configured to control or modify the period of at least one of the two oscillators RO1 and RO2 so that the deviation between the periods T1 and T2 is equal to a target deviation. The modification of the period T1 of the oscillator RO1 and / or the period T2 of the oscillator RO2 by the FB CTRL circuit is implemented on the basis of the output values ​​N of the COUNTER circuit. For example, for a target value Nmt of the average number of Nm of periods T2 per period T of the signal S3, if the output value N is less than Nmt, the deviation between the periods T1 and T2 is reduced, and if the output value N is greater than Nmt, the deviation between the periods T1 and T2 is increased.

[0049] According to one embodiment, the two oscillators RO1 and RO2 are implemented in complementary metal-oxide-semiconductor (CMOS) technology on fully depleted semiconductor on insulator (FDSOI), preferably on fully depleted silicon on insulator. In such an embodiment, preferably, the modification of the period T1 of the oscillator RO1, respectively of the period T2 of the oscillator RO2, is implemented by controlling the back gates of at least one delay element, for example an inverter, of the oscillator RO1, respectively RO2.

[0050] In alternative embodiments, whether or not the oscillators RO1 and RO2 are implemented in CMOS on FDSOI, the modification of the period T1 of the oscillator RO1, respectively of the period T2 of the oscillator RO2, is implemented differently, for example by selecting a propagation path of an oscillation among several possible ones, or by modifying the supply conditions of the oscillator. As an example, the article by A. Peetermans, V. Rozic, and I. Verbauwheden entitled "A Highly-Portable True Random Number Generator Based on Coherent Sampling", published in 2019 in the 29th International Conference on Field Programmable Logic and Applications (FPL) describes another example of adjusting the relative periods of two ring oscillators.

[0051] However, the use of back gates to modulate the period of at least one of the oscillators RO1 and RO2 when these are implemented in CMOS on FDSOI allows greater tuning dynamics and better tuning accuracy of the gap between periods T1 and T2.

[0052] In the example of the Figure 1 , the FB CTRL circuit controls only the period T2 of the oscillator RO2 by means of a control signal CTRL T2. In an alternative embodiment, as illustrated by dotted lines in Figure 1 , the FB CTRL circuit further controls the period T1 of the oscillator RO1 by means of a control signal CTRL T1. In another variant not shown, the CTRL FB circuit only controls the period T1 of the oscillator RO1 by means of the signal CTRL T2.

[0053] In device 1, in each of the oscillators RO1 and RO2, the ratio R between the period of the oscillator and its jitter is determinable and depends on the implementation technology of the oscillators. For example, when the oscillators are implemented in CMOS on FDSOI, this ratio R is of the order of 1000. In practice, for a given technology, this ratio can be obtained by a characterization phase, for example of a plurality of circuits.

[0054] Furthermore, in device 1, the measurement accuracy is determined by the difference between periods T1 and T2. More concretely, the measurement accuracy is equal to 1 / Nm.

[0055] Sufficient measurement accuracy is, for example, achieved when Nm is substantially equal to R. However, in other examples, a measurement accuracy where Nm is less than R may be sufficient. The person skilled in the art is able to determine a target measurement accuracy depending on the application. For example, for two oscillators RO1 and RO2 having periods T1 and T2 equal to 2 ps, to have a measurement accuracy of 1 / 1000, the difference between the periods T1 and T2 must be set by the CTRL FB circuit to 2 ns, i.e. the CTRL FB circuit must, for example, set the period of the oscillator RO1 to 2.002 ns and that of the oscillator RO2 to 2.000 ns.

[0056] It is then understood that the control precision of the periods T1 and / or T2 of the oscillators by the CTRL FB circuit is determined by the target measurement precision. Taking the example case described above, for oscillators RO1 and RO2 implemented in CMOS on FDSOI, the control signals CTRL T1 and CTRL T2 of the back gates must be able to be modified with a precision of the order of mV to obtain the target deviation equal to 2 ns in this example.

[0057] The device 1 further comprises a PROCESS circuit. The PROCESS circuit is configured, once the average period Tm has been set by the FB CTRL circuit, to characterize or determine or discriminate the characteristics of the jitter, for example by using the Allan variance on the N output values ​​of the COUNTER circuit from the N output values ​​of the counter, and, more precisely, from several successive N output values ​​of the COUNTER circuit. In practice, determining the characteristics of the jitter by using the Allan variance on the N output values ​​of the COUNTER circuit amounts to characterizing the entropy source 100, that is to say to characterizing the jitter of the oscillator RO1. Furthermore, the characterization of the Allan variance consists of determining the coefficients b0, b1 and b2 of the quadratic curve b0+b1.Q+b2.Q^2 of the evolution of the Allan variance of the output values ​​of the COUNTER circuit as a function of the accumulation Q.

[0058] Indeed, the output values ​​N of the COUNTER circuit vary around the value Nm depending on the jitter of the oscillator RO1 accumulated on Q equal Nm periods of the signal T2, and can therefore be directly used to characterize the Allan variance on the output values ​​N of the COUNTER circuit, i.e. to determine or calculate the coefficients b0, b1 and b2.

[0059] According to one embodiment, a first Allan variance value can be calculated directly on the N outputs of the COUNTER circuit, by calculating the variance on the difference between two successive N values ​​for a set of several successive N values. This first value corresponds to an accumulation Q equal to Nm, therefore to a first point of the quadratic curve b0 + b1.Q + b2.Q^2 of the evolution of the Allan variance as a function of the accumulation.

[0060] According to one embodiment, in order to calculate or determine the coefficients b0, b1 and b2, the PROCESS circuit is configured to calculate at least two other Allan variance values, or two other points, corresponding to two other accumulation Q values, from the N output values ​​of the COUNTER circuit. The PROCESS circuit is then configured to calculate Allan variance values ​​for any accumulation Q value equal to P.Nm, with P being a positive integer. For this, the PROCESS circuit is configured to store successive N values ​​in successive groups of P successive N values, and to sum, in each group, the P values. The result of each sum gives a second value and the PROCESS circuit is then configured to calculate the Allan variance on these second values, the Allan variance thus calculated corresponding to an accumulation Q equal to P.Nm.Preferably, the groups of P first successive values ​​are non-overlapping and adjacent, i.e., when P successive values ​​are arranged in a group, the next P successive N values ​​are arranged in the next group, and no N value is part of two groups at the same time. In this embodiment, the three Allan variance values ​​are all derived from the N values ​​output from the COUNTER circuit, a first Allan variance value being calculated directly on the N values ​​(for an accumulation value Q=Nm), a second Allan variance value being calculated from the N values ​​(using a first value K1 of the factor P, for an accumulation value Q=K1.Nm) and a third Allan variance value being calculated from the N values ​​(using a second value K2 of the factor P, for an accumulation value Q=K2.Nm).

[0061] According to one embodiment, from at least three Allan variance values ​​corresponding to different accumulation values ​​Q, the PROCESS circuit is configured to calculate the coefficients b0, b1 and b2.

[0062] According to one embodiment, the PROCESS circuit determines the coefficients b0, b1 and b2 by calculating three Allan variance values ​​corresponding to three different accumulation Q values ​​including, for example, the value Q = Nm, and by solving a system of three equations with three unknowns.

[0063] According to an alternative embodiment, the PROCESS circuit determines the coefficients b0, b1 and b2 by calculating two Allan variance values ​​corresponding to two different accumulation Q values ​​including, for example, the value Q = Nm, by obtaining a third theoretical Allan variance value for a third accumulation Q value, and by solving a system of three equations with three unknowns. For example, this third theoretical value comes from information stored in the device 1, for example in a memory of the device 1.

[0064] According to an alternative embodiment, the PROCESS circuit determines the coefficients b0, b1 and b2 by performing a quadratic regression from more than three Allan values, each corresponding to a different accumulation value Q. These Allan variance values ​​are all calculated by the PROCESS circuit, except, for example, one of these values ​​which is a theoretical value directly obtained by the PROCESS circuit, for example from information stored in the device 1, for example in a memory of the device 1.

[0065] It should be noted, however, that determining the coefficients b0, b1 and b2 by implementing a quadratic regression from more than three Allan variance values ​​corresponding to different Q values ​​is more complex and requires more computational resources than determining the coefficients b0, b1 and b2 by solving a system of three equations with three unknowns using only three distinct Allan variance values.

[0066] For example, hardware blocks (or circuits) allowing the calculation of an Allan variance value on a set of several successive values ​​are known and presented, for example, on page 202 of the document "Characterization, evaluation and use of clock jitter as a source of randomness in data security" by EN Allini or on page 143 of the document "Characterization and modeling of random number generators in integrated circuits" by P. Haddad.

[0067] When the PROCESS circuit uses three Allan variance values ​​calculated by the PROCESS circuit (or two Allan variance values ​​calculated by the PROCESS circuit and a third theoretical Allan variance value obtained by the PROCESS circuit), and these three Allan variance values ​​correspond to accumulation Q values ​​equal respectively to Nm, K1.Nm and K2.Nm, preferably the coefficients K1 and K2 are chosen to have a logarithmic spread of the three accumulation Q values.

[0068] As an example, calling v1 the Allan variance calculated for Q equal to Nm, v2 the Allan variance calculated for Q equal to K1.Nm and v3 the Allan variance calculated for Q equal to K2.Nm, the system of three equations with three unknowns solved by the PROCESS circuit is the following: v 1 = b 0 + b 1 . Nm + b 2 . Nm ∧ 2 , v 2 = b 0 + b 1 . K 1 . Nm + b 2 . K 1 . Nm ∧ 2 , v 3 = b 0 + b 1 . K 2 . Nm + b 2 . K 2 . Nm ∧ 2 .

[0069] According to one embodiment, to simplify the calculations, K2 is chosen equal to K1 squared, from which it follows that the system to be solved becomes: v 1 = b 0 + b 1 . Nm + b 2 . Nm ∧ 2 , v 2 = b 0 + b 1 . K 1 . Nm + b 2 . K 1 . Nm ∧ 2 , v 3 = b 0 + b 1 . K 1 ∧ 2 . Nm + b 2 . K 1 ∧ 2 . Nm ∧ 2 .

[0070] Once the PROCESS circuit has characterized the Allan variance on the output of the COUNTER circuit, that is to say that it has determined the coefficients b0, b1 and b2, the PROCESS circuit provides a PARAM output indicating the values ​​b0, b1 and b2 calculated by the PROCESS circuit.

[0071] For example, the thermal noise component S_thermique can then be calculated from the coefficients b0, b1 and b2, for example using the following equation: S_thermique / Nm ∧ 2 = b 1 / Nm .

[0072] There Figure 2 illustrates, by means of a flowchart, an exemplary embodiment of a method for characterizing the entropy source 100 of the circuit 1 of the Figure 1 , that is to say the jitter of the oscillator RO1 of circuit 1 of the Figure 1. Unless otherwise stated, everything stated in relation to the Figure 1 applies to the method described in relation to the Figure 2 .

[0073] At a first step, or phase, 200 (block "SET Nm"), the circuit CTRL FB adapts or modifies the period of at least one of the oscillators RO1 and RO2 on the basis of the output values ​​N of the circuit COUNTER so that the difference between the periods T1 and T2 is equal to a target difference, or, in other words, so that the average duration Nm of the period T of the signal S2 in number of periods T2 of the signal S2 is equal to a target value.

[0074] Once this setting is obtained, at a step, or phase, following 202 ("GET PARAM" block), the PROCESS circuit calculates the coefficients b0, b1 and b2 of the function b0 + b1.Q + b2.Q describing the evolution of the Allan variance on the outputs of the COUNTER circuit as a function of the accumulation Q. The coefficients b0, b1, and b2, i.e. the PARAM output of the PROCESS circuit, characterize the Allan variance, i.e. the source of entropy 100 and therefore the jitter of the oscillator RO1.

[0075] There Figure 3 represents implementation details of a part of circuit 1 of the Figure 1 according to one embodiment, and, more particularly, details of implementation of the PROCESS circuit according to one embodiment.

[0076] In the embodiment of the Figure 3 , the PROCESS circuit is configured to calculate: a first value v1 of Allan variance directly on the successive N output values ​​of the COUNTER circuit, the value v1 corresponding to an accumulation value Q equal to Nm; a second value v2 of Allan variance from values ​​derived from the successive N values, i.e. from several sums of K1 successive N values, the value v2 then corresponding to an accumulation value Q equal to K1.Nm; and a third value v3 of Allan variance from other values ​​derived from the successive N values, i.e. from several sums of K2 successive N values, the value v3 then corresponding to an accumulation value Q equal to K2.Nm.

[0077] The PROCESS circuit is then configured to calculate the coefficients b0, b1 and b2 characterizing the Allan variance. More specifically, the coefficients b0, b1 and b2 characterize the evolution of the Allan variance as a function of the accumulation Q, that is to say that they characterize the entropy of the entropy source 100, or, in other words, the jitter of the oscillator RO1.

[0078] For this, the PROCESS circuit receives the successive N output values ​​from the COUNTER circuit (not shown in Figure 3 ).

[0079] These successive N values ​​are supplied to a CALC circuit of the PROCESS circuit configured to calculate, from these successive N values, a value v1 of the Allan variance corresponding to an accumulation Q equal to Nm.

[0080] These successive N values ​​are also supplied to an ACC circuit K1 of the PROCESS circuit. The ACC circuit K1 is configured to calculate several sums SUM1 of K1 successive N values. For example, the ACC circuit K1 is configured, as it receives the successive N values, to sum K1 successive values, supply a SUM1 value resulting from this summation, and then to repeat this operation of summing K1 successive N values ​​to produce a SUM1 value on each subsequent group of K1 successive N values.

[0081] The CALC circuit receives the SUM1 values. The CALC circuit is configured to calculate, from the successive SUM1 values ​​produced, by the ACC circuit K1, from the successive N values, a value v2 of the Allan variance corresponding to an accumulation Q equal to K1.Nm.

[0082] The successive N values ​​received by the PROCESS circuit are also provided to an ACC circuit K2 of the PROCESS circuit. The ACC circuit K2 is configured to calculate several sums SUM2 of K2 successive N values. For example, the ACC circuit K2 is configured, as it receives the successive N values, to sum K2 successive values, provide a SUM2 value resulting from this summation, and then repeat this operation of summing K2 successive N values ​​to produce a SUM2 value on each subsequent group of K2 successive N values.

[0083] The CALC circuit receives the SUM2 values. The CALC circuit is configured to calculate, from the successive SUM2 values ​​produced, by the ACC circuit K2, from the successive N values, a value v3 of the Allan variance corresponding to an accumulation Q equal to K2.Nm.

[0084] Finally, the CALC circuit is configured to calculate the coefficients b0, b1 and b2 from the Allan variance values ​​v1, v2 and v3. For example, the CALC circuit is configured to solve the system of three equations with three unknowns presented previously in relation to the Figure 1 .

[0085] The PROCESS circuit, for example its CALC circuit, then provides the PARAM output indicating the value of the coefficients b0, b1 and b2.

[0086] As an alternative embodiment not shown, when the CALC circuit is configured to calculate the value v1, the value v2 and the coefficients b0, b1 and b2 from the values ​​v1, v2 and a third value v3' where the value v3' is a theoretical Allan variance value directly supplied to the CALC circuit, the ACC circuit K2 is omitted. This simplifies the implementation of the CALC circuit but can in return introduce a measurement error in the calculation of the coefficients b0, b1 and b2.

[0087] Although not illustrated here, in yet another alternative embodiment, the PROCESS circuit is configured to calculate more than three Allan variance values ​​corresponding to different accumulation Q values, and to determine the coefficients b0, b1 and b2 from these Allan variance values ​​by implementing quadratic regression. However, in this case, the PROCESS circuit will be more cumbersome and more complex than that of the Figure 5 or the implementation variant with three values ​​v1, v2 and v3' of Allan variance.

[0088] An advantage of having characterized the Allan variance is that it is then possible to determine a positive integer value K for which the accumulation Q = K.Nm of the jitter of the oscillator RO1 is sufficient to produce a random bit with a minimum target entropy Htarget. This value K can be calculated by applying the Baudet model presented in the paper "On the Security of Oscillator-Based Random Number Generators", by M. Baudet, D. Lubicz, J. Micolod, and A. Tassiaux, published in J Cryptol, vol. 24, no. 2, pp. 398-425, Apr. 2011.

[0089] For example, it is possible to link the target minimum entropy Htarget, the factors K1 and K2, the value K and the values ​​v1, v2 and v3 by means of the following inequality: K > In 1 − Htarget / 0.584 . Nm + 1 . v 2 − v 1 . K 2 ∧ 2 − 1 − v 3 − v 1 . K 1 ∧ 2 − 1 / 39.478 . Nm ∧ 3 . k 1 − 1 . k 2 − 1 . k 2 − k 1

[0090] Once this value K is fixed, to obtain a random RN bit with an entropy greater than or equal to the target entropy Htarget, it is sufficient to sum K successive N values ​​and the RN bit is then the least significant bit of the result of this sum.

[0091] The optional step of determining the value K on the basis of a target minimum entropy Htarget, and of summing K successive values ​​N to obtain the random bit RN is for example implemented following step 202 of the Figure 2 . This optional step is further, for example, implemented by the PROCESS circuit of circuit 1 as shown in Figure 1 where the PROCESS circuit provides the random bit RN.

[0092] There Figure 4 represents implementation details of another part of circuit 1 of the Figure 1 according to one embodiment. More particularly, the Figure 4illustrates implementation details of the PROCESS circuit according to an embodiment in which the PROCESS circuit is configured to provide the RN bit corresponding to the least significant bit of the sum of K successive N values.

[0093] The PROCESS circuit then includes an ACC circuit K. The ACC K circuit is configured to receive the successive N output values ​​of the COUNTER circuit (not shown in Figure 4 ), to sum the K values ​​of each set of K successive N values, and to provide the SUM result of this operation. As an example, the ACC K circuit is controlled by a Kctrl signal indicating the K value to use.

[0094] The RN bit then corresponds to the least significant bit of the SUM result. For example, the PROCESS circuit then implements a function for selecting the least significant bit of the SUM result, for example by means of an LSB circuit receiving the SUM signal and supplying the RN bit.

[0095] These implementation details of the PROCESS circuit when the latter is configured to provide the RN bit are compatible with the implementation details of the PROCESS circuit described in relation to the Figure 3 .

[0096] Optionally, according to one embodiment, the device 1 further comprises one or more alarm circuits configured to detect one or more malfunctions of the device 1. Each step of detecting a malfunction is, for example, implemented in the method described in relation to the Figure 2 , for example following step 202.

[0097] There Figure 5 represents an embodiment of an alarm circuit 500 implemented in circuit 1 of the Figure 1 .

[0098] In this embodiment, the circuit 500 (block "N ≥ TH" in Figure 5) is configured to detect a blockage of the signal S3, i.e. when the signal S3 no longer varies with time in a periodic manner with an average period Tm as previously described. This situation results for example from the fact that one of the two oscillators RO1 and RO2 locks onto the other of the two oscillators RO1 and RO2, which leads to a signal S3 whose state is constant (high or low). This situation can also be the result of an attack on the device 1 by a hacker.

[0099] To detect such a blocking of the signal S3, the circuit 500 is configured to receive the output values ​​N of the circuit COUNTER, and to compare each value N received to a threshold TH. The threshold is greater than the value Nm, for example at least twice greater than the value Nm. In other words, the threshold TH is determined by the target deviation used in step 200 ( Figure 2 ).

[0100] If one of the received N values ​​exceeds the threshold TH, this means that the signal S3 is in a blocking situation, and the circuit 500 is then configured to provide an alarm signal ALARM1.

[0101] For example, when an ALARM1 signal is emitted by the circuit 500, the circuit 1 is configured to reset the oscillators RO1 and RO2, for example by blocking with a control signal the propagation of oscillations in these oscillators before allowing this propagation again. After such a step of resetting the oscillators RO1 and RO2, at least step 200 of the method for characterizing the entropy source 100 is implemented.

[0102] There Figure 6 represents an embodiment of another alarm circuit 600 implemented in circuit 1 of the Figure 1 .

[0103] In this embodiment, circuit 600 ("ALLAN VAR IN RANGE?" block in Figure 6) is configured to detect a change in the operation of oscillators RO1 and RO2 resulting, for example, from variations in operating temperature, aging of the circuit.

[0104] For this, the circuit 600 receives the successive N output values ​​from the COUNTER circuit, and is configured to calculate sums SUM3 of K3 successive values, and to calculate an Allan variance value v4 on the successive SUM3 values. The circuit 600 is further configured to compare the value v4 with a variance value V4 calculated from the coefficients b0, b1 and b2 determined in step 200 and an accumulation value Q equal to K3.Nm. If the difference between the values ​​v4 and V4 is greater than a threshold, this means that the operation of the oscillators RO1 and RO2 has been modified since the implementation of step 200 and that the coefficients b0, b1 and b2 determined during this step are no longer valid.

[0105] According to one embodiment, the value K3 is chosen equal to the value K used to generate the RN bit. This makes it possible to reuse the ACC K circuit of the PROCESS circuit, which then directly provides the SUM values. In alternative embodiments, the value K3 is different from the value K, but is preferably chosen to correspond to an accumulation value Q for which the Allan variance determined in step 200 is in the region dominated by thermal noise.

[0106] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0107] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above.

Claims

1. Electronic device (1) comprising: an entropy source (100) comprising: - a first ring oscillator (RO1) and a second ring oscillator (RO2) identical to the first ring oscillator, and - a synchronous flip-flop (FF) configured to supply an output signal (S3) corresponding to a sampling of an output (S1) of the first oscillator (RO1) at a frequency of an output (S2) of the second oscillator (RO2); a counter (COUNTER) configured to supply, for each period of the output signal (S3) of the flip-flop (FF), a value (N) equal to a number of periods of the second oscillator (RO2) counted during said period of the output signal (S3) of the flip-flop (FF); a first circuit (FB CTRL) configured to modify, during a first phase (200), a period of at least one of the two oscillators (RO1, RO2) based on the values (N) supplied by the counter (COUNTER) so that an average difference between the periods of the two oscillators is equal to a target difference; and a second circuit (PROCESS) configured to receive the values (N) supplied by the counter and to characterize, during a second phase (200) and based on said values (N), an Allan variance on the output (O) of the counter.

2. Device according to claim 1, wherein the target difference is at least partly determined by a ratio of the jitter to the period of the first oscillator (RO1) and / or by a target measurement accuracy.

3. Device according to claim 1 or 2, wherein the two oscillators (RO1, RO2) are implemented in complementary metal-oxide semiconductor technology on fully depleted semiconductor on insulator, preferably on fully depleted silicon on insulator.

4. Device according to claim 3, wherein the first circuit (FB CTRL) is configured to control (CTRL T1, CTRL T2) back gates of at least one delay element of at least one of the two oscillators (RO1, RO2) to modify the average difference between the periods of the two oscillators.

5. Device according to any of claims 1 to 4, wherein the second circuit (PROCESS) is configured, during the characterization of the Allan variance, to: compute a first Allan variance value over a plurality of successive values (N) supplied by the counter (COUNTER); compute (ACC K1) a second Allan variance value over a plurality of sums (SUM1) of K1 successive values (N) supplied by the counter (COUNTER); receive a third theoretical Allan variance value or compute (ACC K2) a third Allan variance value over a plurality of sums (SUM2) of K2 successive values (N) supplied by the counter; and compute (CALC) three coefficients of quadratic curve characterizing the Allan variance based on at least said first, second, and third Allan variance values.

6. Device according to any of claims 1 to 5, wherein the second circuit (PROCESS; ACC K, LSB) is configured to add K successive values (N) supplied by the counter (COUNTER) and to deliver (LSB) a least significant bit (RN) of said sum (SUM), K being determined by a minimum target entropy.

7. Device according to any of claims 1 to 6, wherein the device further comprises: a first alarm circuit (500) configured to compare with a first threshold each value (N) supplied by the counter (COUNTER) and to trigger a first alarm (ALARM 1) when said value is greater than the first threshold; and / or a second alarm circuit (600) configured to compute an Allan variance value based on the output values (N) of the counter (COUNTER) and a corresponding Allan variance value by using the Allan variance characterized by the second circuit (PROCESS), and then to compare a difference between these two computed values with a second threshold and to trigger a second alarm (ALARM 2) if the difference between these two computed values is greater than the second threshold.

8. Method for characterizing an entropy source comprising: - a first ring oscillator (RO1) and a second ring oscillator (RO2) identical to the first ring oscillator, and - a synchronous flip-flop (FF) delivering an output signal (S3) corresponding to a sampling of an output (S1) of the first oscillator (RO1) at a frequency of an output (S2) of the second oscillator (RO2), the method comprising: the supplying, with a counter (COUNTER) and at each period of the output signal (S3) of the flip-flop (FF), a value (N) equal to a number of periods of the second oscillator (RO2) counted during said period of the output signal (S3) of the flip-flop (FF); a first phase (200) comprising modifying, with a first circuit (FB CTRL) and based on the values (N) supplied by the counter (COUNTER), a period of at least one of the two oscillators (RO1, RO2) so that an average difference between the periods of the two oscillators (RO1, RO2) is equal to a target difference; and a second phase (202) comprising the characterization, by a second circuit (PROCESS) and based on the values (N) supplied by the counter (COUNTER), of an Allan variance of the output (O) of the counter (COUNTER).

9. Method according to claim 8, wherein the target difference is at least partly determined by a ratio of the jitter to the period of the first oscillator (RO1) and / or by a target measurement accuracy.

10. Method according to claim 8 or 9, wherein the two oscillators (RO1, RO2) are implemented in complementary metal-oxide semiconductor technology on fully depleted semiconductor on insulator, preferably on fully depleted silicon on insulator.

11. Method according to claim 10, wherein the first circuit (FB CTRL) controls back gates of at least one delay element of at least one of the two oscillators (RO1, RO2) to modify the average difference between the periods of the two oscillators.

12. Method according to any of claims 8 to 11, wherein the Allan variance characterization comprises: the computing, by the second circuit (PROCESS), of a first Allan variance value over a plurality of successive values (N) supplied by the counter (COUNTER); the computing, with the second circuit (PROCESS), of a plurality of sums (SUM1) of K1 successive values (N) supplied by the counter (COUNTER) and a second Allan variance value over said plurality of sums (SUM1) of K1 successive values; the receiving, by the second circuit (PROCESS), of a third theoretical variance value or the computing, with the second circuit (PROCESS), of a plurality of sums (SUM2) of K2 successive values (N) supplied by the counter (COUNTER) and a third Allan variance value over said plurality of sums (SUM2) of K2 successive values; and the computing, by the second circuit (PROCESS), of three coefficients of a quadratic curve characterizing the Allan variance based on at least said first, second, and third Allan variance values.

13. Method according to any of claims 8 to 12, wherein the method further comprises a computing by the second circuit (PROCESS) of a sum of K successive values (N) supplied by the counter (COUNTER) and a delivery by the second circuit (PROCESS) of a least significant bit (RN) of the sum (SUM), K being determined by a minimum target entropy.

14. Method according to any of claims 8 to 13, wherein the method further comprises: the comparing, by a first alarm circuit (500), of each value (N) supplied by the counter with a first threshold and the triggering, by the first alarm circuit (500), of a first alarm (ALARM 1) if a value (N) supplied by the counter (COUNTER) is greater than the threshold; and / or the computing, by a second alarm circuit (600), of an Allan variance value based on the output values (N) of the counter (COUNTER) and a corresponding Allan variance value by using the characterized Allan variance, the comparing, by the second alarm circuit (600), of a difference between the two computed Allan variance values with a second threshold, and the triggering, by the second alarm circuit (600), of a second alarm (ALARM 2) if the difference is greater than the second threshold.