Substrate with vias and associated manufacturing processes

Description

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to the field of substrates for manufacturing electronic devices, and more particularly microelectronic devices. These substrates can enable in fine An electrical and mechanical connection of electrical components. The invention finds advantageous, but not limiting, application in the manufacture of microelectronic devices. STATE OF THE ART

[0002] There is interest in fabricating microelectronic devices using vias extending perpendicularly to the main extension plane of the substrate. This can be particularly interesting for the fabrication of microelectromechanical systems (MEMS). MicroElectroMechanical SystemsThis can also be particularly useful for manufacturing component assemblies on substrates with vias to form through-hole contacts, allowing these components to be interconnected on the front and back sides of a substrate to create a microelectronic device. The components can then be connected to a printed circuit board, for example, via a package. These substrates can include semiconductor substrates, such as semiconductor-on-insulator (SOI), and in particular silicon-on-insulator (SOI). Silicon-On-Insulator ).

[0003] The engraving and filling of these vias (commonly referred to as TSV, abbreviation of English Through-Silicon-Via for silicon-based substrates) by an electrically conductive or semiconductor material, are fairly specific process steps and are often carried out by assemblers (commonly referred to as OSATs, from the English Out-sourced Semiconductor Assembly and Test)and not the foundry workers.

[0004] US 2021 / 407890 A1 discloses a plurality of vias through silicon.

[0005] Two types of vias are distinguished according to their stage of manufacture in the microelectronic device production chain. So-called "TSV-middle" vias are generally manufactured in the middle of the process, after the fabrication of the component's patterns during the Front-end-of-line (abbreviated FEOL, which can be translated as start of production line) but before the deposition of the metallic layers of Back-end-of-line(abbreviated BEOL, which can be translated as end of production line). This generally requires transferring the substrate and components from the foundry to the assembler for via fabrication, then returning them to the foundry for the BEOL steps, and finally transferring them back to the assembler to complete the process. These manufacturing steps are highly constrained in terms of flatness and contamination, which is poorly suited to these back-and-forth movements between the foundry and the assembler.

[0006] TSV-last vias can be manufactured at the end of the process, after the FEOL and BEOL stages. This generally requires only one transfer from the foundry to the assembler, after the BEOL stages. However, the geometries of vias that can be produced in this way are limited. In particular, the density of vias that can be achieved is limited.

[0007] Therefore, there is a need to obtain these structures without depending on the other manufacturing stages of the chain.

[0008] One object of the present invention is therefore to facilitate the fabrication of vias in a microelectronic device.

[0009] The other objects, features, and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY OF THE INVENTION

[0010] To achieve this objective, a first aspect involves planning a substrate, particularly for microelectronic devices, comprising: a first layer based on, and preferably made of, a semiconductor material, a second layer on top of the first layer.

[0011] The substrate comprises a plurality of buried vias extending from the second layer over a portion of the first layer, each via being bounded by a side wall, a bottom wall, and a top wall opposite the bottom wall, and at least one set of the plurality of vias forms a pattern repeating along at least one direction of the main extension plane of the first and second layers.

[0012] Thus, the substrate is generic and includes pre-filled, non-through vias, or vias configured for subsequent filling by an electrically conductive or semiconducting component. This allows the vias to be supplied independently of other microelectronic device fabrication steps. The substrate, including the buried vias, can be used for layer deposition, for example, FEOL and BEOL, and then the vias can be used to fabricate the desired electrically conductive or semiconducting component, such as electrical interconnects. Furthermore, since the vias are fabricated in advance, their geometries are not limited.

[0013] The substrate includes a matrix of vias that can be selected in whole or in part to fabricate the desired electrically conductive or semiconducting components with the most suitable geometry. This generic substrate, incorporating these vias, thus facilitates the fabrication of both the vias and the conductive or semiconducting component, and can be adapted to various microelectronic devices.

[0014] It is therefore understandable that the fabrication of vias is facilitated, particularly compared to other manufacturing steps of a microelectronic device, by allowing adaptation to different microelectronic devices using the same generic substrate. The fabrication of vias filled by the electrically conductive or semiconductor component is especially simplified.

[0015] A second aspect concerns a substrate manufacturing process, including: a supply of a support sub-substrate comprising at least a first layer based on a semiconductor material, the support sub-substrate having an exposed surface, the formation of a plurality of vias such that the vias extend from the exposed surface over a portion of the first layer, each via being delimited by a side wall and a bottom wall, at least one set of vias forming a repeating pattern along at least one direction of the principal extension plane of the first and second layers, a supply of a donor sub-substrate comprising a surface layer having an exposed surface, an assembly of the support sub-substrate and the donor sub-substrate by their exposed surfaces, so as to cover the vias, each via then being delimited by the side wall, the bottom wall, and a top wall opposite the bottom wall.

[0016] This process allows for the fabrication of the via matrix embedded in the substrate. This process exhibits the effects and advantages described in relation to the first aspect.

[0017] A third aspect concerns a manufacturing process for a microelectronic device comprising: a supply of a substrate according to the first aspect and / or a substrate manufactured by the process according to the second aspect, having a front exposed surface and a rear exposed surface, a formation of at least one layer portion of the device by deposition of said portion on at least one of the front or rear exposed surfaces of the substrate, for example a first exposed surface, and for example the front exposed surface, and / or an etching of at least one of the front or rear exposed surfaces of the substrate, for example the first exposed surface, and for example the front exposed surface, configured to form said portion, at the level of at least one via, an etching by one of the front or rear exposed surfaces of the substrate, for example a second exposed surface distinct from the first, and for example the rear exposed surface, until reaching the via,and: ∘ continue the etching to reach at least one portion of the device layer, or ∘ at at least one via, etch through another among the front or rear exposed surfaces of the substrate, for example through the first exposed surface, and for example the front exposed surface, until reaching the via, the deposition of at least one electrically conductive or semiconducting component so as to establish electrical continuity between at least the via and the portion of the device layer, for example also with the front and / or rear surface of the substrate.

[0018] Thus, the provided substrate allows for the formation of a microelectronic device, followed by the opening of buried vias to create the desired electrically conductive or semiconducting component. This can be achieved more easily compared to existing solutions. BRIEF DESCRIPTION OF THE FIGURES

[0019] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which: THE Figures 1A and 1B These represent, respectively, cross-sectional and sectional views in the principal extension plane of the first and second layers of the substrate, according to an example embodiment. figures 2A to 2C represent cross-sectional views of different via configurations. Figures 3A and 3B represent, respectively, cross-sectional and sectional views in the principal extension plane of the first and second layers of the substrate, according to another embodiment. figures 4A to 4E They represent cross-sectional views of the steps in the substrate manufacturing process, according to a specific implementation. Figures 5A to 5Drepresent cross-sectional views of the steps in the substrate manufacturing process according to another embodiment. figures 6A to 6D They represent cross-sectional views of the steps in the microelectronic device manufacturing process, according to an example embodiment. figures 7 And 8A to 8D represent cross-sectional views of the steps in the microelectronic device manufacturing process according to two other embodiment examples. figures 9A to 9C represent cross-sectional views of the steps in the microelectronic device manufacturing process, according to an example in which a via comprises several portions, each with a different configuration.

[0020] The drawings are provided by way of example and are not intended to limit the scope of the invention. They are schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the relative dimensions of the sub-substrates and substrate, layers, vias, and walls are not representative of reality. DETAILED DESCRIPTION OF THE INVENTION

[0021] Before beginning a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are stated below.

[0022] According to an example, for at least some of the vias, and for example for each via, the vias are at least partially filled with material(s).

[0023] In one example, each via has at least one transverse dimension between 1 µm and 30 µm. In another example, all the transverse dimensions of each via are between 1 µm and 30 µm.

[0024] As an example, at least some of the vias, and preferably each via, have an aspect ratio greater than or equal to 10, with the longest dimension oriented along a thickness dimension of the first and second layers. This aspect ratio is particularly well-suited for achieving a high density of vias on the substrate, especially in synergy with the pitch ranges described later.

[0025] According to an example, within a set of vias, two via patterns, for example two vias, repeating successively are separated by a constant step following at least one direction of the main extension plane of the first and second layers.

[0026] As an example, the pitch is typically between 50 µm and 300 µm, preferably between 100 µm and 200 µm. This pitch allows for a higher density of vias within the substrate, thus enabling greater interconnection density. Furthermore, the substrate's adaptability to different microelectronic devices is improved.

[0027] As an example, the substrate comprises several sets of vias, each forming a repeating pattern along at least one direction of the principal extension plane of the first and second layers. The generic substrate can thus include different arrangements of via patterns to suit a variety of microelectronic devices.

[0028] According to one example, at least one via, and preferably at least some part of the plurality of vias, and preferably each via, has at least one via configuration in which: the side wall of the via is made of a dielectric material, and the via is filled with an electrically conductive or semiconductive material or the via is hollow, the side wall of the via is made of a dielectric material, and the via is filled with the material of the first layer, the side wall of the via is made of the material of the first layer and the via is hollow.

[0029] Vias can therefore be solid or hollow, and may already be electrically insulated from the first layer. When the via's side wall is made of a dielectric material, the vias formed in the substrate have at least one dielectric layer on their side wall prior to the substrate being used in a microelectronic device fabrication process. Because the dielectric material wall is formed beforehand, it provides good insulation for the vias once they are filled with the conductive or semiconducting material, while also being compatible with FEOL (Fused End-on-Loop) or temporary substrate mounting steps.

[0030] As an example, at least one via, and preferably at least some of the plurality of vias, and preferably each via in at least one set, has a first via configuration on a first portion, and a second via configuration distinct from the first via configuration on a second portion, the first and second portions extending successively along a thickness dimension of the first and second layers. As an example, one portion of these vias may be hollow, and another portion may be solid. This type of via allows for narrower via widths for the solid portion, and therefore more vias for a given area. Their accessibility is facilitated by the pre-formed hollow portion.

[0031] As an example, the substrate comprises several sets of vias, each forming a repeating pattern along at least one direction of the principal extension plane of the first and second layers. At least one set, and preferably each set, exhibits at least one via configuration distinct from any other set. The generic substrate can thus include different via structures to accommodate a variety of microelectronic devices.

[0032] In one example, the substrate also includes a marker configured to allow substrate alignment. This further simplifies the fabrication of the microelectronic device by facilitating substrate alignment, particularly for the photolithography steps necessary for constructing the FEOL and BEOL, and thus opening the vias.

[0033] According to one example, the vias are parallel to each other.

[0034] According to one example, the vias have a longitudinal dimension oriented along a thickness dimension of the first and second layers.

[0035] In one example, the vias extend in a direction parallel to the normal to the main extension plane of the first and second layers.

[0036] According to one example, at least some of the vias, and preferably each via of at least one set, have a cross-section, for example in a plane substantially parallel to the main extension plane of the first and second layers, of square, polygonal or cylindrical shape.

[0037] In one example, the second layer is placed on top of the first layer by being in direct contact with it.

[0038] According to one example, at least part of the vias, and preferably each via, has a cross-section, for example in a plane substantially parallel to the main extension plane of the first and second layers, whose ratio of the largest dimension to the smallest dimension is less than or equal to 3, preferably less than or equal to 2. The vias are therefore quite distinct from other structures such as trenches.

[0039] As an example, at least some of the vias, and preferably each via in at least one set, exhibit rotational symmetry about an axis substantially parallel to a thickness dimension of the first and second layers. Preferably, at least some of the vias, and preferably each via in at least one set, are cylindrical. Thus, the bottom wall of the vias is more homogeneous than for non-cylindrical shapes, for example, a square shape where the corners will be shallower than the center due to the via etching. A cylindrical shape minimizes this effect. Furthermore, the mechanical stresses are lower for cylindrical vias, which lack corner singularities. This is advantageous for heat treatments during circuit fabrication.

[0040] As an example, at least one via, and preferably each via in at least one assembly, is completely enclosed over at least a portion of a longitudinal dimension of said via by a groove extending from the second layer over a portion of the first layer. The groove improves electrical insulation between the vias. The groove is thus prefabricated independently of the other manufacturing steps of the microelectronic device. This makes the groove compatible with FEOL steps performed at high temperatures. Furthermore, because the groove is prefabricated, its geometry is not limited by the other manufacturing steps of the microelectronic device.

[0041] In one example, each groove is not filled with a solid material. Each groove is preferably filled with an electrically insulating gaseous atmosphere, for example air.

[0042] In one example, each groove is defined by a bottom wall, a side wall, and a top wall opposite the bottom wall. For at least one groove, and preferably for each groove, at least part of the side wall and the bottom wall can be made of the same material as the first layer. The insulation of the vias is sufficient due to the insulating atmosphere contained within the groove. Alternatively, for at least one groove, and preferably for each groove, at least part of the side wall and the bottom wall can be made of a dielectric material, for example, the same dielectric material as the via walls. This further improves the electrical insulation of the via.

[0043] In one example, the groove is concentric with the via. This notably reduces the parasitic capacitance between the via and the substrate and increases the breakdown voltage.

[0044] In one example, the groove extends from the second layer into the first layer over a longitudinal dimension less than a longitudinal dimension of the via; preferably, the longitudinal dimension of the groove is less than or equal to the longitudinal dimension of the via, preferably within µm or ±5 µm. Thus, the groove surrounds the via over at least a portion and preferably substantially the entire longitudinal dimension.

[0045] According to one example, the semiconductor material is chosen from the group consisting of silicon Si, germanium Ge, SiGe, a III-V material (e.g. GaN, InN, InGaAs, GaP, InP, InAs, AsGa...), a II-VI material, wide band-gap materials, e.g. greater than 3 eV.

[0046] According to one example, the semiconductor material comprises, and preferably is, silicon.

[0047] According to one example, the piezoelectric material is chosen from lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium-sodium niobate (KxNa1-xNbO3 or KNN), barium titanate (BaTiO3), quartz, lead zirconate titanate (PZT), a lead-magnesium niobate and lead titanate compound (PMN-PT), zinc oxide (ZnO), aluminum nitride (AIN) or aluminum-scandium nitride (AIScN).

[0048] According to one example, the dielectric material is a semiconductor oxide, and preferably silica with the chemical formula SiO2.

[0049] According to an example of the substrate fabrication process, the formation of the plurality of vias is configured such that at least a portion of the plurality of vias exhibits at least one of the following via configurations: the side wall of the via is made of a dielectric material, and the via is filled with an electrically conductive or semiconductive material or the via is hollow, the side wall of the via is made of a dielectric material, and the via is filled with the material of the first layer, the side wall of the via is made of the material of the first layer and the via is hollow.

[0050] According to one example, via configurations differ for at least one of the following properties: the dielectric or non-dielectric nature of the via's side wall; the shape of the via (and in particular the cross-section), the dimension, the via's filling material, the hollow or solid nature of the via.

[0051] According to one example, the formation of the plurality of vias includes, for at least one set of vias and on at least a first portion of said vias, an engraving of at least one perimeter of the via.

[0052] In one example, the etching process is configured to etch only the perimeter of the via. Alternatively, the etching process can be configured to etch a groove forming the perimeter of the via. Thus, after an oxide forms in the groove, the side wall of the via is made of a dielectric material, and the via is filled with the first-layer material.

[0053] In another example, the etching process is configured to etch the via over virtually its entire volume. Thus, the side wall of the via can be made of the material from the first layer, and the via can be hollow. Alternatively, after the formation of an oxide around the perimeter of the cavity, the side wall of the via can be made of a dielectric material, and the via can be either hollow or filled.

[0054] According to one example, the formation of the plurality of vias includes, following the etching of at least the perimeter of the via, the formation of a dielectric material on at least the etched perimeter of the via so as to form the lateral wall of the via in dielectric material.

[0055] As an example, during the etching of at least the periphery of the via, the via is etched over substantially its entire volume, and the formation of the plurality of vias comprises, following the formation of a dielectric material on at least the etched periphery of the via so as to form the lateral wall of the via in dielectric material, a deposition of an electrically conductive or semiconducting material so as to at least partially fill the via. Thus, the lateral wall of the via is made of the dielectric material, and the via is filled with the electrically conductive or semiconducting material.

[0056] It is therefore understood that these different steps lead to the via configurations described previously.

[0057] As an example, the formation of the plurality of vias includes the formation of several sets of vias, each forming a repeating pattern along at least one direction of the main extension plane of the first and second layers.

[0058] According to one example, the formation of via sets is configured so that each set has at least one via configuration distinct from another set.

[0059] According to one example, the formation of the plurality of vias is configured such that at least one via, and preferably at least a part of the plurality of vias, has a first via configuration on a first portion, and a second via configuration distinct from the first via configuration on a second portion, the first and second portions extending along a thickness dimension of the first and second layers.

[0060] According to one example, the formation of a dielectric material at least at the bottom wall and side wall of the plurality of vias includes: thermal oxidation so as to oxidize the semiconductor material of the first layer at least at the bottom wall and side wall, and / or a deposition of the dielectric material at least at the bottom wall and side wall.

[0061] These techniques, and thermal oxidation in particular, allow for good conformity of the dielectric material walls. Because thermal oxidation is conformal, it produces a dense oxide layer of uniform thickness on both the bottom and side walls. Thermal oxidation is therefore particularly advantageous when used in conjunction with high via aspect ratios. Compared to deposition, thermal oxidation also smooths the walls of etched vias and minimizes the presence of defects between the first layer of semiconductor material and the dielectric.

[0062] According to one example, when the side wall is made of dielectric material, the side wall of the plurality of vias has a transverse dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0063] According to an example, when the bottom wall is made of dielectric material, the wall has a longitudinal dimension approximately between 50 nm and 600 nm, preferably approximately equal to 400 nm.

[0064] According to one example, the surface layer of the donor sub-substrate is a base layer, and preferably made of a material chosen from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material.

[0065] For example: the supporting sub-substrate further comprises a surface layer based on, and preferably made of, a dielectric material, for example an oxide, overlying the first layer, the surface layer presenting the exposed surface, and / or the surface layer of the donor sub-substrate is a layer based on, and preferably made of, a dielectric material, for example an oxide, overlying a layer based on a material selected from a semiconductor material or a piezoelectric material.

[0066] It is therefore understood that the buried oxide layer of the substrate can originate from the donor sub-substrate and / or the supporting sub-substrate.

[0067] As an example, the surface layer of the donor substrate is based on, or preferably made of, either a semiconductor material or a dielectric material. Depending on whether the surface layer is based on a semiconductor material or a dielectric material, it is understood that the upper wall of the vias, and where applicable, the grooves, is based on or made of a semiconductor material or a dielectric material.

[0068] As an example, the substrate manufacturing process further includes, prior to the assembly of the support sub-substrate and the donor sub-substrate, the engraving of a groove completely surrounding at least one via over at least a portion of a longitudinal dimension of said via, the groove extending from the surface layer into the first layer. The effects and advantages described with respect to the groove are thus obtained.

[0069] According to one example, the process includes the formation of a weakening zone at a depth of the surface of the superficial layer of the donor substrate, followed by separation of the donor substrate at the level of the weakening zone.

[0070] As an example, the microelectronic device fabrication process involves selecting at least one via to be etched from among a plurality of vias, with only a subset of the plurality of vias being selected for etching. Thus, it is possible to select the vias to be etched from among those present in the substrate. The process is therefore adaptable to the desired microelectronic device configuration for different microelectronic devices. This selection can be made prior to etching by one of the exposed front or rear surfaces of the substrate.

[0071] In one example, selecting the at least one via to be etched involves applying a mask with openings directly above the at least one via to the exposed front or rear surface of the substrate. This mask is then etched to reach the at least one via. This avoids potential weakening of the via walls compared to extensive thinning of the substrate face. The etching process thus removes the layer directly above the at least one via until it reaches the at least one via.

[0072] As an example, when the process involves etching through the other exposed front or rear surfaces of the substrate until the via is reached, the selection of the at least one via to be etched from among the plurality of vias includes applying, to said other exposed front or rear surface of the substrate, a mask comprising openings located directly above the at least one via to be etched, and the process further includes etching to reach the at least one via to be etched. This is particularly advantageous when the via is filled with an electrically conductive or semiconducting material, including the material of the first layer. This allows the via to be accessed from both the rear and front faces of the substrate, thus establishing electrical continuity with the via.

[0073] According to one example, the deposition of the electrically conductive or semiconductive component is configured so as to further cover with an electrically conductive or semiconductive layer at least a portion of the exposed front and / or rear surface of the substrate.

[0074] According to one example, the process includes creating patterns in the electrically conductive or semiconductive back layer.

[0075] According to one example, the process includes passivation of the exposed rear surface of the substrate.

[0076] For example, the manufacturing process for a microelectronic device includes: between the formation of at least one portion of the device layer, and the etching by the rear exposed surface of the substrate, the mounting of a support on the front exposed surface of the substrate, and after the deposition of the electrically conductive or semiconductive element so as to fill the electrical cavity, the removal of the support.

[0077] The support thus makes it easier to handle the substrate.

[0078] A microelectronic device is defined as any type of device manufactured using microelectronic techniques. These devices include, in addition to purely electronic devices, micromechanical or electromechanical devices, as well as optical or optoelectronic devices. It may be a device designed to perform an electronic, optical, mechanical, or other function. It may also be of a productAn intermediate component solely intended for the implementation of another microelectronic device. It can also be a passive electrical interconnection structure.

[0079] It is specified that, within the framework of the present invention, the term "on" or "above" does not necessarily mean "in contact with". Thus, for example, the deposition of one layer on another does not necessarily mean that the two layers are directly in contact with each other, but it means that one of the layers at least partially covers the other, either by being directly in contact with it, or by being separated from it by a film, yet another layer, or another element.

[0080] A layer can also be composed of several sub-layers of the same material or of different materials.

[0081] An element "based" on a material A is understood to be an element comprising only that material A or that material A and possibly other materials.

[0082] In the detailed description that follows, terms such as "longitudinal" and "transverse" may be used. These terms should be interpreted in relation to the substrate or the thickness dimension of the devices. Thus, a longitudinal dimension, height, depth, or thickness of an element or layer refers to a dimension relative to the thickness of the substrate that supports or contains it. A width, cross-section, or transverse dimension refers to a dimension perpendicular to the thickness of the substrate.

[0083] Certain parts of the substrate or device of the invention may have an electrical function. Some are used for electrical conductivity properties, and electrically conductive or equivalent parts are understood to be elements made of at least one material having sufficient conductivity, in the application, to perform the desired function. Other parts, on the contrary, are used for electrical insulation properties, and all materials having sufficient resistivity to achieve this insulation are concerned and are specifically called dielectrics or electrically insulators.

[0084] The term "dielectric" specifically describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 4.

[0085] "Direct bonding" refers to bonding without the addition of adhesive material (such as glue or polymer) which consists of bringing relatively smooth surfaces (with a root mean square roughness RMS, typically less than 5 Å, 10⁻¹⁰ m) into contact, for example carried out at room temperature and under ambient atmosphere, in order to create adhesion between them.

[0086] According to one embodiment, the direct bonding of two substrates means that the bonding is achieved through chemical bonds that form between the two surfaces brought into contact. These chemical bonds can be, for example, Van der Waals forces and / or strong, covalent chemical bonds, particularly when the bonding is assisted by plasma activation or followed by a strengthening heat treatment (typically 200 to 1200°C for 1 hour).

[0087] Direct bonding can be achieved without applying significant pressure to the structure being assembled. Light pressure is all that is needed to initiate the bond. Thermal annealing can then be performed to further strengthen the bond.

[0088] A parameter that is "approximately equal to / greater than / less than" a given value means that this parameter is equal to / greater than / less than the given value, to within 10% or even 5% of that value.

[0089] Substrate 3 is now described according to several embodiment examples with reference to Figures 1A to 2C .

[0090] As illustrated, for example, by the Figure 1AThe substrate 3 comprises a first layer 30, based on or made of a semiconductor material. In one example, the semiconductor material comprises, and preferably is, silicon. Note that, as described later, other semiconductor materials are possible. The first layer 30 has a thickness L30, for example, approximately between 100 µm and 800 µm.

[0091] Substrate 3 further comprises a second layer 31. As illustrated by the Figures 1A And 2A The second layer 31 may be based on, or made of, a dielectric material. In one example, the dielectric material comprises, and preferably is, a semiconductor oxide, for example, silica with the formula SiO₂. The second layer 31 is placed on top of the first layer 30, preferably in direct contact with it. As illustrated by the figure 2BThe second layer 31 may alternatively be based on or made of a semiconductor material, preferably single-crystal, or of a piezoelectric material. The second layer 31 may have a thickness L31, for example, greater than or equal to 10 nm, preferably 100 nm. The thickness L31 may be less than or equal to 3000 nm. The second layer 31 of the substrate 3 is preferably free of metallic portions. The second layer 31 is preferably continuous in the principal extension plane of the substrate 3.

[0092] For example, which can be illustrated by the Figures 1A And 2AThe second layer 31 is surmounted by a third layer 33 based on or made of a semiconductor material, preferably single-crystal, or a piezoelectric material. In one example, the semiconductor material comprises, and preferably is, silicon. It should be noted here again that, as described later, other semiconductor materials are possible. The third layer 33 has a thickness L 33, for example, approximately between 10 nm and 20,000 nm. The substrate 3 can therefore comprise a semiconductor-on-insulator structure, and in particular a silicon-on-insulator (SOI) structure. It should be noted that the second layer 31 may not be surmounted by a third semiconductor layer. The third layer 33 of the substrate 3 is preferably free of metallic portions. The third layer 33 is preferably continuous in the principal extension plane of the substrate 3.

[0093] According to one example, the material from which a layer 30, 31, 33 is formed is preferably continuous in the plane of extension of the layer. At least one, and preferably each layer(s) 30, 31, 33 is preferably continuous over at least 80%, preferably over at least 90%, and even more preferably over the entire length, of the main plane of extension of the substrate 3.

[0094] The first layer 30 and / or the second layer 31 is / are preferably monolithic. The first layer 30 is preferably monolithic over at least the portion over which the vias 32 extend.

[0095] In the following, unless explicitly stated otherwise, substrate 3 is considered, for non-limiting purposes, to be an SOI substrate, the first layer 30 being monocrystalline silicon, the second layer being SiO2 and the third layer being monocrystalline silicon.

[0096] The substrate 3 comprises vias 32 extending from the second layer 31 into the first layer 30. The vias 32 preferably extend along a longitudinal dimension L 32 oriented in the direction of the thickness of the first 30 and second 31 layers. The vias 32 may be parallel to each other. The vias 32 are buried in the substrate 3, that is, they do not open onto either of the exposed surfaces 3a, 3b of the substrate 3. The vias 32 therefore define a closed volume.

[0097] Thus, substrate 3 includes vias 32 for their subsequent use in a microelectronic device fabrication process. This allows the vias to be supplied independently of the other fabrication steps of a microelectronic device 4, as described later with reference to the microelectronic device fabrication process.

[0098] The longitudinal dimension L 32 can be chosen so that the vias 32 are flush with the surface of the first layer 30, at the interface with the second layer 31, as illustrated for example in the figures 1A to, 2A and 2C Alternatively, not illustrated here, the vias 32 can also extend over a portion of the thickness L 31 of the second layer 31. This is the case for example when the donor sub-substrate 2 and the support sub-substrate 1 each have a surface layer based on a dielectric material, these surface layers together forming the second layer 31 after assembly.

[0099] Since the vias 32 are not through-holes, they are delimited by a side wall 320, a bottom wall 321, and a top wall 322 opposite the bottom wall 321. Note that the front surface 3a and the rear surface 3b of the substrate 3 can be defined interchangeably with respect to the bottom walls 321 and top walls 322 of the vias. In the following, and including for the manufacturing process of the microelectronic device described later, it is assumed, for the sake of completeness, that the bottom wall 321 faces the rear surface 3b of the substrate 3 and the top wall 322 faces the front surface 3a of the substrate 3. The processes described later can, however, be adapted to the case where the bottom wall 321 faces the front surface 3a of the substrate 3 and the top wall 322 faces the rear surface 3b of the substrate 3.

[0100] One or both of the surfaces exposed on substrate 3 can be based on a semiconductor material, preferably single-crystal. The vias 32 can be topped with a layer or stack of layers comprising at least one layer based on a semiconductor material, preferably single-crystal. It is therefore understood that the second layer 31 and / or the second layer 33 can be based on a semiconductor material, preferably single-crystal, as described previously. Thus, the generic substrate 3 comprising the vias is compatible with the FEOL and BEOL steps.

[0101] For example, the selection of vias to be etched can be made from the front panel, and for example after etching substrate 3 of the 32 vias on the rear panel. The selection of vias to be etched can be made from the rear panel, and for example before or after etching substrate 3 of the 32 vias on the front panel.

[0102] According to an example that can be illustrated by the Figures 1A and 1B The vias 32 form at least one set 32a comprising a pattern 32b that repeats at least once along at least one direction, preferably two directions, of the main extension plane of the first 30 and second 31 layers. These directions are preferably perpendicular. It may be assumed that these directions are not perpendicular to each other. Thus, there is at least one pattern 32b of vias 32 and one or more sets 32a of vias 32 repeating a pattern 32b. Each set comprises a repeated pattern 32b of vias 32. The patterns 32b may differ between several sets 32a.

[0103] A 32b motif may consist of only one via 32, or several vias 32 as illustrated in figure 1BThe 32b via pattern can be of any shape. For example, several 32 vias can form a polygonal pattern in a plane parallel to the main extension plane of the first 30 and second 31 layers. The 32b via patterns can be arranged at regular intervals in the main extension plane of the first 30 and second 31 layers.

[0104] Thus, substrate 3 can be a generic substrate comprising a via matrix, in which vias to be etched 32 will be chosen according to the electrically conductive or semiconductive parts to be formed, as described in more detail later.

[0105] To achieve this, the 32b patterns of vias 32 can be successively separated by a first step A along a first direction contained in the main extension plane of the first 30 and second 31 layers. The 32b patterns of vias 32 can be successively separated by a second step B along a second direction contained in the main extension plane of the first 30 and second 31 layers, distinct from the first. Preferably, these first and second directions are perpendicular. These steps are taken center to center between a via of pattern 32b and the corresponding via of the following pattern 32b, as illustrated in the figure 1B . Steps A and / or B are preferably constant, that is to say, essentially identical for each repetition of patterns.

[0106] One or both of these pitches A and B can be substantially between 50 µm and 300 µm, preferably between 100 µm and 200 µm. These pitches can be different from each other or equal to each other, depending on the desired matrix geometry.

[0107] According to a preferred example, substrate 3 comprises a single 32b pattern of via 32, preferably consisting of only one via 32. According to this example, each via 32 is separated from its neighboring via(s) 32 by substantially identical steps A and B for each pattern repetition. The steps A and B are preferably equal to each other.

[0108] According to an example illustrated by the Figures 3A and 3B The vias 32 form several sets 32a, 32a', 32a", that is, at least two or more sets. Each set 32a, 32a', 32a" may include a repeating via pattern 32b as described above. The patterns 32b, 32b', 32b" of different sets may be different, as illustrated, for example, by the figure 3B .

[0109] The motif(s) 32b may be repeated along one direction, preferably one of the two distinct directions above, of the principal extension plane of the first 30 and second 31 layers, over at least 80% of the dimension of the substrate 3 in that direction(s). The motif(s) 32b of vias 32 are preferably repeated, in the principal extension plane of the first layer 30, over at least 80%, preferably at least 90%, and more preferably at least 95%, of the principal extension plane of the first layer 30. The motif(s) 32b of vias 32 are further preferably repeated, in the principal extension plane of the substrate 3, over at least 80%, preferably at least 90%, and more preferably at least 95%, of the principal extension plane of the substrate 3.Generic substrate 3 thus comprises one or more arrays of generic vias 32 over a large portion of its surface, to facilitate the fabrication of a microelectronic device as described in detail later. These vias 32 can be selected according to the desired architecture, with a generic substrate 3 that can be adapted to the fabrication of different microelectronic devices.

[0110] According to one example, at least part of the vias 32 and preferably each via, extends over a height greater than or equal to 50% of the thickness of the substrate 3, preferably greater than or equal to 70% of the thickness of the substrate 3.

[0111] The vias 32 may also exhibit one of several configurations, or equivalently, one of several structures. For example, the vias 32 may be at least partially hollow and / or at least partially filled with a solid material. These configurations are now described with reference to the figures 2A to 2C , which illustrate different possible via configurations. The 32b pattern of repeated vias is not shown.

[0112] As an example, the side wall 320 of the via 32 can be made of a dielectric material, and the via 32 can be filled with an electrically conductive material 323 or a semiconductor. This configuration is compatible with the FEOL steps.

[0113] The side wall 320 of the via 32 can be made of a dielectric material, and the via 32 can be hollow. Preferably, according to these examples, at least the side wall 320 and the bottom wall 321 are made of a dielectric material. The top wall 320 can be made of a dielectric material, a semiconductor material, or a piezoelectric material, as will become clearer during the description of the substrate fabrication process 3.

[0114] In another example, the side wall 320 of the via 32 can be made of a dielectric material, and the via 32 is filled with the material of the first layer 30. According to this example, the bottom wall 321 of the via can be located at the normal to the side wall 320 at its end. This bottom wall may not be physically materialized by a change in material, as illustrated by the dashed lines in figure 2A .

[0115] In another example, the via 32 can be hollow and not delimited by a side wall of dielectric material. The side wall 320 of the via 32 can be made of the material of the first layer 30.

[0116] When the via 32 is hollow, it is not filled with a solid material. The via 32 is preferably filled with a gaseous atmosphere such as air, nitrogen, or argon, possibly at a pressure less than or equal to ambient pressure.

[0117] When at least the bottom wall 321 and the side wall 320 are made of dielectric material, the via 32, once filled with an electrically conductive or semiconducting material, will be electrically insulated from the first layer 30 and from the other vias 32. Alternatively, the walls of the vias 32, and in particular the side wall 320, may be made of semiconducting material, and more particularly of the same material as that of the first layer 30. The electrical insulation of the vias 32 may be carried out subsequently during the fabrication process of the microelectronic device from the substrate 3, described later.

[0118] The vias can have a transverse dimension D 32, for example a diameter, substantially less than or equal to 30 µm, preferably substantially between 1 µm and 30 µm, preferably substantially between 5 µm and 15 µm, and even more preferably between 8 and 12 µm. Thus, the lateral dimension D 32 is smaller than the typical dimensions of TSV-last, which allows for a greater number of vias 32 for the same surface area of ​​the substrate 3 in the main extension plane of the first 30 and second 31 layers, i.e., a greater density of vias 32. The longitudinal dimension of the vias L 32 can be on the order of the thickness L 30 of the layer 30, the vias 32 being non-through. L 32 may be substantially less than or equal to 200 µm, preferably substantially between 50 and 150 µm, for example substantially equal to 100 µm.These length ranges make it easier to form an electrically conductive or semiconducting through-hole component, for example a through-hole interconnection via the via 32, of the substrate 3 during the fabrication of the microelectronic device 4.

[0119] A via 32 can also have several segments, each with a different configuration, with the configurations differing between segments. For example, a via can have a first segment 32c with one configuration, and a second segment 32d with a different configuration, as illustrated for example in the Figures 2A and 2B The lateral dimension D 32 of a via can differ between sections, for example, the first section 32c and the second section 32d. Specifically, a first section can be filled and a second section can be hollow. This allows for a smaller via while facilitating access through the hollow section.

[0120] The vias 32 may have a form factor substantially greater than or equal to 5, and preferably greater than or equal to 10. A form factor is defined as the ratio of the longest dimension to the shortest dimension. Here, the form factor F is such that F = L 32 / D 32. This form factor facilitates the formation of an electrically conductive or semiconducting through-hole component, for example, a through-hole interconnect via the via 32, during device fabrication, and increases the density of the vias 32 on the substrate.

[0121] As illustrated in figure 2C A via may have a cross-section, for example in a plane substantially parallel to the main extension plane of the first 30 and second 31 layers, of square, polygonal, or cylindrical shape. Preferably, the vias 32 are cylindrical.

[0122] According to an example illustrated in Figures 2A and 2BA via 32 may include a groove 35 configured to improve the electrical insulation of the vias 32. The substrate 32 is thus particularly suitable for high-frequency applications and / or as a replacement for high-resistivity substrates in applications requiring them. For this purpose, the via 32 has a cross-section entirely enclosed by the groove 35, which lies in the principal extension plane of the first 30 and second 31 layers. The groove 35 may enclose the via 32 over at least a portion of its longitudinal dimension L 32. The grooves 35 are preferably arranged to isolate the vias 32 from one another, with each groove 35 preferably enclosing only one via 32. The grooves 35 preferably do not touch each other. The groove 35 may, more specifically, extend from the second layer 31 over a portion of the first layer 30.Note that the groove 35 can be positioned around a via 32 regardless of its configuration as described above. The groove provides better dielectric insulation to the via configuration it surrounds.

[0123] Each groove 35 is preferably buried, meaning it does not open onto either of the exposed surfaces 3a, 3b of the substrate 3. Each groove 35 thus defines an enclosed volume. Each groove 35 may be hollow, meaning it is not filled with a solid material. In this case, each groove 35 is preferably filled with a gaseous atmosphere such as air, nitrogen, or argon, possibly at a pressure less than or equal to ambient pressure. Each groove 35 may also be filled, preferably entirely, with a solid material, such as a dielectric material.

[0124] Each groove 35 can be delimited by a side wall 350, a bottom wall 351, and a top wall 352 opposite the bottom wall 351. The bottom wall 351 is disposed towards the rear surface 3b of the substrate, and the top wall 352 is disposed towards the front surface 3a of the substrate 3. Of these walls, at least the bottom wall 351 and the side wall 350 can be made of a dielectric material, for example, SiO2. As illustrated in the figure 2A All the walls can be made of dielectric material. It can be provided that the groove 35 is flush with the surface of the first layer 30, like the vias 32 illustrated in Figures 2A and 2B The upper wall 352 can be of the same material as the second layer 31. All walls can be of the same material as the layer in which or against which they extend, in dielectric, semiconducting or piezoelectric material depending on the layer considered.

[0125] As illustrated, for example, by the Figures 2A and 2B , each groove 35 can have a longitudinal dimension, or equivalently a depth, L 35 substantially equal to or less than that of the via L 32, according to an example equal to plus or minus 5 µm.

[0126] As illustrated, for example, by the Figures 2A and 2BEach groove 35 can have a transverse dimension D 35, measured on either side of the via 32, for example a diameter, substantially less than or equal to 50 µm, preferably substantially between 20 µm and 30 µm. Each groove 35 can have a width substantially less than or equal to 5 µm, for example substantially between 2 and 4 µm. Thus, similarly to the dimensions of the vias 32, improved electrical insulation can be achieved while allowing for a high density of vias 32. Synergistically, it is particularly advantageous to use these grooves 35 when the vias 32 are close to each other, as is the case for a high density of vias 32 on the substrate 3, in order to improve their electrical insulation. By high density, for example, pitches A and / or B are less than or equal to 100 µm. It can be predicted that the grooves 35 will have equal or distinct dimensions between the different grooves 35.

[0127] Depending on the dimensions of the grooves 35 in the main extension plane of the first 30 and second 31 layers, the pitch can be adjusted so that the grooves 35 are distinct from each other. Each groove 35 can be cylindrical, and preferably concentric with the via 32 that it surrounds.

[0128] When the substrate 3 comprises several assemblies 32a, each assembly may have one via configuration, or, where applicable, several configuration segments. The via configurations 32 of different assemblies 32a may differ from each other. Preferably, each via 32 of the same assembly 32a has the same via configuration, or, where applicable, several configuration segments. The dimensions of the vias 32 may also vary between the different assemblies 32a. Preferably, each via 32 of the same assembly 32a has the same dimensions. The cross-section of the vias 32 may also vary between the different assemblies 32a. Preferably, each via 32 of the same assembly 32a has the same cross-section.

[0129] As illustrated, for example, by Figures 1A, 1B , And 3A, 3BThe substrate 3 may include at least one mark or, equivalently, a marker 34 enabling alignment of the substrate 3 with other elements. This ensures reliable placement of the vias 32 during the microelectronic device manufacturing process. This marker 34 may be formed by one or more portions of a dielectric material layer in the first layer 30 and / or the second layer 31. It should be noted that those skilled in the art may well consider other marker variations, such as a marking located on the front surface 3a or the rear surface 3b of the substrate 3.

[0130] The manufacturing process for substrate 3 is now described with reference to figures 4A to 5D .

[0131] The process includes the provision of a sub-substrate 1. The sub-substrate 1 comprises at least a first layer 10, intended to form the first layer 30 of the substrate 3 that will be obtained, as illustrated for example by the Figures 4A And5A According to an example not shown, the sub-substrate 1 may further comprise a surface layer intended to form at least part of the second layer 31 of the substrate 3. The surface layer is preferably based on or made of a dielectric material. The sub-substrate 1 further has an exposed surface 1a, at the level of the first layer 10 or the surface layer 11.

[0132] As illustrated, for example, by the Figures 4A And 5A , the 32 vias can be formed by etching, and preferably by deep reactive ion etching (commonly abbreviated DRIE, from the English " Deep Reactive On Etching " . For this, the etching step may include the application of a mask 12 comprising openings 120 from which the vias 32 will be etched, as illustrated for example by the figure 5AThe mask 12 is preferably a resin mask. It can be made hard, for example, by applying a resin mask 12, then etching the surface layer 11 of dielectric material, removing this mask, and etching the first layer 10 using the resulting "hard" oxide mask. Note that the surface layer 11 can be removed after the vias 32 have been etched, and the vias 32 can then be electrically insulated by deposition of a dielectric layer.

[0133] The etching process is preferably configured to achieve the characteristics of the vias 32 described previously, and in particular their dimensions and the spacing between them. For example, the dimensions of mask 12 and / or the etching time and speed are adjusted accordingly.

[0134] The engraving is configured to engrave only the perimeter of the 32 vias. As illustrated, for example, by the figure 4AA groove 320' can be engraved, this groove 320' being intended to form the lateral wall 320 of the via 32. Alternatively, as illustrated for example by the figure 5A The Via 32 can be engraved over virtually its entire volume.

[0135] To form the dielectric material side wall 320, the process can then include forming a dielectric material to form the side wall 320. As illustrated, for example, by the figure 4B The 320' groove can be filled, preferably entirely, with a dielectric material. For this purpose, the dielectric material, for example silica SiO2, can be deposited. This deposit can be a chemical vapor deposition (commonly abbreviated CVD, from English Chemical Vapor Deposition ) from gaseous precursors comprising oxygen and silicon, for example tetraethyl orthosilicate (commonly abbreviated TEOS from English tetraethyl orthosilicate) or silane with the chemical formula SiH4, possibly combined with dioxygen. The deposit is, for example, a subatmospheric pressure CVD deposit (commonly abbreviated SACVD, from English Sub-Atmospheric CVD ), or plasma-enhanced chemical deposition (commonly abbreviated PECVD, from the English Plasma-Enhanced CVD.

[0136] When the via 32 is etched over substantially its entire volume, the formation of the dielectric material can be carried out on the side wall 320 and the bottom wall 321, as illustrated for example by the figure 5B This formation can be achieved by deposition of the dielectric material as described above. Alternatively, this formation can be achieved by thermal oxidation, for example at a temperature of approximately 1050 °C in an oxygen-containing atmosphere.

[0137] Preferably, the formation of the walls 320, 321 is configured so that the dielectric material walls 320, 321 have a dimension substantially between 50 nm and 600 nm, and preferably substantially equal to 400 nm. For the side wall 320, this dimension is the transverse dimension. For the bottom wall 321, this dimension is the longitudinal dimension. For example, the thermal oxidation time or the deposition time and / or the deposition rate can be adjusted accordingly.

[0138] When the via 32 is etched over substantially its entire volume, and preferably following the formation of the walls 320, 321 in dielectric material, the via 32 can be filled with an electrically conductive or semiconducting material 323, as illustrated for example in figure 5CThe conductive material can be a metal, for example copper or tungsten. The semiconductor material can be polycrystalline silicon (usually designated Poly-Si). This filling is preferably done by depositing the material 323 in the via 32. For example, Poly-Si deposition is usually done by LPCVD (abbreviated English Low Pressure Chemical Vapor Deposition, which can be translated as chemical vapor deposition at sub-atmospheric pressure).

[0139] Depending on the via formation stages described above, the different via configurations described previously can be obtained. For example, one can go from the figure 5A to the assembly with the donor sub-substrate 2 to obtain hollow vias 32 without sidewalls 320 made of dielectric material. For example, one can go from the figure 5B to the assembly with the donor sub-substrate 2 to obtain hollow vias 32 with side wall 320 and bottom 321 of dielectric material.

[0140] To obtain a via with several portions each presenting a configuration, it is possible to make a combination of etching and deposition, or even to transfer a layer of substrate 1 to plug the via in the rear part of the substrate.

[0141] The mask 12 can be removed after the formation of the dielectric material, or even after the via 32 has been filled with the material 323. Alternatively, the mask 12 can be removed before the formation of these walls with dielectric material. If the layer 11 has served as a hard mask, it is preferable to remove it as well.

[0142] The process may include, concurrently with or following the formation of the vias, a step for forming the datum 34. For this purpose, the mask may further include openings, not shown here, for etching, for example, openings in the second layer 31 down to the first layer 30. The openings may be filled with the dielectric material during the wall formation. The formation of the datum 34 may be separate from these steps, for example, by applying a mask specifically designed for this datum 34, etching, and filling the openings. If the formation of the datum 34 is separate from these steps, it is advantageously carried out beforehand to serve as a reference for positioning the vias 32.

[0143] The formation of the grooves 35 can include the same steps as for the etching of the vias 32 and, where applicable, for the formation of the walls in dielectric material. The grooves 35 can be formed simultaneously with the vias 32, the mask 12 then comprising openings corresponding to the grooves 35 to be etched. Alternatively, the grooves 35 can be etched before or after the etching of the vias 32, for example, by applying a mask and etching specifically for the grooves 35. As an example, once the grooves 35 and vias 32 have been etched, a dielectric material can be formed at the walls 350, 351, 320, 321 as previously described. Alternatively, the grooves 35 can be formed after the formation of the dielectric material at the walls 320 and 321. It can be envisaged that a further formation of dielectric material will be carried out at the walls 350, 351, according to the previously described methods.The engraving of the grooves 35 may otherwise not be followed by the formation of dielectric material at the walls 350 and 351. The grooves 35 and the vias 32 may not have a wall of dielectric material, according to one variant.

[0144] Following the formation of the vias 32 and, where applicable, the grooves 35, these structures can be covered for burial during the assembly of the sub-substrate 1 with a donor sub-substrate 2. The process can therefore include the provision of a donor sub-substrate 2 having an exposed surface 2a'. The assembly methods described below can be applied to all the examples described previously.

[0145] As illustrated, for example, by the figure 4DThe sub-substrates support 1 and donor 2 can be assembled by directly bonding their respective surfaces 1a, 2a. The donor substrate 2 can then be thinned, for example by cleaving using the process known as Smart-Cut ®.

[0146] The assembly may therefore include, before the surfaces 1a and 2a are brought into contact, the formation of a weakened zone 22 at a non-zero depth of the surface 2a of the donor sub-substrate 2. This weakened zone 22 is formed, for example, by the implantation of ions, such as hydrogen and / or helium ions. It should be noted that any other technique for forming a weakened zone, and in particular any other technique used in SOI-type stack fabrication processes, may be considered.

[0147] Following the assembly of the support sub-substrate 1 and the donor sub-substrate 2, the process may include the separation of a surface layer of the donor sub-substrate 2, at the level of the embrittlement zone 22, as illustrated by the passage of the figure 4D to the figure 4E This separation can be done thermally or mechanically, according to steps known to the person in the trade.

[0148] Following separation, the resulting surface 3a may be irregular. Chemical polishing, smoothing, or chemical and / or mechanical and / or thermal and / or ion beam healing of the surface 3a can be performed, resulting in a crystalline quality and roughness suitable for further processing. Any chemical-mechanical polishing (CMP) method is applicable. Chemical Mechanical Polishing) or thermal treatment intended to smooth a semiconductor-based surface, particularly silicon-based, can be considered.

[0149] As an example, the donor sub-substrate 2 comprises a layer 20 based on or made of a semiconductor material, for example silicon, and more particularly single-crystal silicon, or a piezoelectric material. The donor sub-substrate 2 may further comprise a layer 21 based on or made of a dielectric material, for example silica (SiO2).

[0150] As an example, layer 21, made of a dielectric material, can form the surface layer of the donor sub-substrate 2. In particular, direct bonding of a dielectric material, for example silicon oxide, to another dielectric material, for example silicon oxide, can be achieved. Following their assembly, layer 21 and layer 11 will form the second layer 31 of the substrate 3. Their respective thicknesses can therefore be chosen to obtain the desired thickness L 31. From this example, it is understood that the upper wall 322 of the vias 32 and, where applicable, the upper wall 352 of the grooves 35 can be formed of a dielectric material.

[0151] Alternatively, a direct bonding of dielectric material, for example silicon oxide, can be made against the semiconductor of layer 10 of the sub-substrate support 1. Following their assembly, layer 21 will form the second layer 31 of the substrate 3. According to this example, it is understood that the upper wall 322 of the vias 32 and where applicable the upper wall 352 of the grooves 35 can be formed of a dielectric material.

[0152] As an example, layer 20 can form the surface layer of the donor sub-substrate 2. Direct bonding of a dielectric material, for example silicon oxide, to a counter-semiconductor or piezoelectric material can be achieved. Following their assembly, layer 20 will form the second layer 31 of the substrate 3, and an intermediate dielectric layer is placed between the first layer 30 and the second layer 31. From this example, it is understood that the upper wall 322 of the vias 32 and, where applicable, the upper wall 352 of the grooves 35 can be formed from a semiconductor or piezoelectric material.

[0153] As an example, layer 20 can form the surface layer of the donor sub-substrate 2. Direct bonding of a semiconductor or piezoelectric material to a semiconductor, particularly silicon, is possible when layer 20 is based on a semiconductor or piezoelectric material. Following their assembly, layer 20 will form the second layer 31 of the substrate 3.

[0154] Note that it is preferable to have a thickness of dielectric material, and in particular oxide, of at least 10 nm at the bonding interface for the assembly to avoid the appearance of defects.

[0155] The manufacturing process for a microelectronic device 4 is now described with reference to figures 6A à 8D .

[0156] In this process, the 32 vias can be used to establish interconnections. Alternatively or in addition, the 32 vias can be used to form portions of a microelectronic device without necessarily being metallic interconnects, for example in a MEMS device.

[0157] The process may include the provision of substrate 3. The process may include the deposition of component layers, for example, transistors, diodes, or memory chips. This deposition may, for example, include FEOL steps.

[0158] As illustrated, for example, on the figure 6D The process may include depositing at least one portion of a layer 40, also called a portion 40 of the device, onto the front surface 3a of the substrate 3. In the following, it is considered, for the sake of completeness, that several portions 40 are deposited. Alternatively or in addition, the portion(s) of the device may be etched into the front exposed surface 3a of the substrate 3.

[0159] These sections can be metallic and can form metallic interconnection lines. Typically, these metallic sections can be used to redistribute electrical signals. These metallic sections can also be referred to as metallization levels. There can be several metallic sections with interconnections between them. This deposit can, for example, include the BEOL stages.

[0160] In the following, it is assumed, for the sake of completeness, that these portions 40 are metallic and that the engraved via 32 serves to establish an interconnection. The following steps apply equally to the case where non-metallic portions 40 of device 4 are deposited and / or engraved.

[0161] The deposition of at least a portion of layer 40 can be done after the formation of the vias 32 as illustrated, and where appropriate after the formation of the conductive or semiconducting parts 45, or before.

[0162] To facilitate handling of the substrate 3, the process may include mounting a support 41 on the exposed front surface 3a and / or rear surface 3a of the substrate 3, depending on the manufacturing steps. This mounting may be achieved, for example, by means of an adhesive 410, as illustrated by the figure 6B This also helps to protect the deposits made on the surface of the substrate 3. The process may also include dismantling this support 41, for example when it is necessary to access the surface re-covered by the support 41 or at the end of the process

[0163] The process involves etching at least one via 32 to establish at least one electrical connection between a portion 40, the via 32, and the back surface 3b of the substrate. Several examples are possible and are now described. For the sake of simplicity, the portions 40 are not shown in all the figures. In the following, it is assumed, for non-limiting purposes, that several vias 32 are etched.

[0164] Preferably, the process includes a selection of only a subset of the vias 32, to define a group of vias to be etched 32'. Thus, from the generic substrate 3, only the vias of interest for the fabrication of the microelectronic device 4 can be used. In the following, it is assumed, for non-limiting reasons, that the process includes this selection and that only a subset of the vias 32 are used, and not all of them.

[0165] According to a first example, as illustrated by the figure 6A à 6D From the front surface 3a, a cavity 43 can be created to reach the vias 32'. For this purpose, a mask 42 can be applied to the front surface of the substrate 3. The mask may include openings 420 or be etched to present the openings 420. The mask can be a hard mask, for example, based on or made of SiO2. The mask is, for example, deposited by PECVD.

[0166] Cavities 43 can be engraved so as to reach the vias 32', and more particularly so as to reach and preferably exceed their upper wall 322, as illustrated for example by the figure 6A For this purpose, a silicon etch in SF6 is performed, for example. Preferably, the etch does not expose the conductive material of via 32' at this stage to avoid substrate contamination. This could indeed be detrimental if active devices are subsequently fabricated. To expose the conductive material 323 of the via, the process may include an RIE etch (short for RIE). Reactive lon Etching, (which can be translated as reactive ion etching) to open the bottom of the cavity, also known as " etch back » . It is preferable that the electrically conductive material of the via be discovered only after the formation of the dielectric walls 450, described later.

[0167] Once the cavities 43 are formed, the process may include the deposition of an electrically conductive or semiconducting element 45. This element 45 may be based on or made of a metallic material 45, for example, electrolytic copper or CVD tungsten. Alternatively, this element 45 may be based on or made of a semiconducting material, for example, poly-Si. The deposition may be configured to fill these cavities 43 with the metallic material to form an electrical interconnection or a portion of a device 40, as illustrated, for example, by the figure 6D .

[0168] Starting from the rear surface 3b of the substrate 3, the first layer 30 can be etched until it is flush with, or extends beyond, the bottom wall 321 of the vias 32. To achieve this, the first layer 30 can be thinned and etched by removing material from the first layer 30. The entire rear surface 3b of the substrate 3 can be etched. All the vias 32 will thus be reached.

[0169] This etching can, for example, be a selective etching of the material in layer 30 relative to the dielectric material of the via walls 32. The etching could, for instance, be a selective etching of silicon relative to silica (SiO₂) using reactive ion etching with a precursor such as SF₆. By "selective etching of material A relative to material B," we mean that the etching rate of material A is 10, and preferably 100 times, greater than that of material B. Alternatively, one could consider performing a partial mechanical thinning of the substrate 3, completed by selective plasma or chemical etching. The dielectric wall can then be selectively etched relative to the material of the first layer 30, leading into the via 32'. Only certain vias 32' may be subjected to this selective etching. For example, the etching of the dielectric material could be reactive ion etching.The etching of the semiconductor material can be similar to that done to etch layer 30.

[0170] As an alternative or complement, one can also consider a localized engraving from the rear surface 3b by means of a mask having openings in line with the vias 32' to be engraved, and the filling of the engraved cavities by an electrically conductive or semiconductive element.

[0171] Preferably, prior to depositing the electrically conductive or semiconductive element on the front surface 3a and / or rear surface 3b of the substrate 3, the process includes forming a wall 450 of dielectric material so as to isolate this element from the layers it passes through, as illustrated in the figure 6C For example, the walls 450 can be formed by a PECVD deposit, for example of SiO2. This deposit is preferably sufficiently conformable to cover the sides of the cavity 43. This prevents a short circuit through the substrate 3.

[0172] The method may then include a deposition configured to cover at least a portion of the rear exposed surface 3b of the substrate 3 with a metallic or semiconducting layer 46, in order to create continuity between the device portion 40, the via 32 and the rear face 3b of the substrate 3, as illustrated for example by the figure 6D .

[0173] The process may further include at least one of, preferably between the formation of cavities 43 and the deposition of layer 46: The removal of the mask 42 involves passivation of the exposed rear surface 3b of the substrate 3, for example by forming a layer of dielectric material 44, also called the passivation layer 44. This formation can be achieved by depositing a dielectric material, for example, as described previously, by etching the layer 44 to remove any oxide layer that may have formed at the via 32'. This potential oxide layer can indeed limit the re-establishment of electrical contact on the portion 40.

[0174] According to the example illustrated by the figure 7 This process can also be applied to a via having a side wall made of dielectric material and filled with the same material as the first layer 30. The same steps as described previously can be applied.

[0175] THE figures 8A à 8D They describe another example in which the vias 32 are hollow. As previously described, a cavity 43 can be formed directly above the vias to be engraved 32', so as to open into the via 32.

[0176] When the walls of the vias 32' to be etched are not made of dielectric material, the process may include the formation of a dielectric layer at least on the side wall 320, according to the modalities previously described with reference to the substrate fabrication process 3. This example may be illustrated by the figure 8B . Walls 450 made of dielectric material are further advantageously formed at the level of the engraved cavities 43.

[0177] The vias 32' can then be filled with the electrically conductive or semiconductive component 45. The steps described below with reference to the previous examples can be applied.

[0178] Alternatively, the etching can be carried out from one face of the substrate 3 until it opens into the via 32', and continued to form at least one cavity 43, for example an electrical connection cavity 43, and reach the other face of the substrate 3, either from the front or the rear face. The method may further include the other steps described above to obtain the device illustrated in figure 8D .

[0179] As illustrated by the figures 9A à 9C The examples described can also be applied to the example where the vias 32 have several configuration segments along the same via 32. For example, a portion filled with an electrically conductive or semiconducting material can be connected by the element 45. A hollow portion of the via 32 can be at least partially filled by the layer 46 and / or another element 45, after the formation of a wall of dielectric material so as to insulate the via 32.

[0180] The examples described can also be applied to the example in which the vias 32 include grooves 35. In order to avoid filling the grooves of the conductive or semiconductive element, the openings 420 of the mask 42 can be arranged so as not to allow the grooves 35 to be engraved. During the steps subsequent to the formation of the cavities 43, the grooves 35 preferably remain closed and are therefore not filled by the element 45.

[0181] In view of the preceding description, it is clear that the invention proposes a substrate, its manufacturing process and a manufacturing process for a microelectronic device to facilitate the fabrication of vias in a microelectronic device.

[0182] The invention is not limited to the embodiments described above and extends to all embodiments covered by the invention. The present invention is not limited to the examples described above. Many other embodiments are possible, for example, by combining features described above, without departing from the scope of the invention. Furthermore, the features described with respect to one aspect of the invention can be combined with another aspect of the invention.

[0183] Specifically, the substrate can exhibit any characteristic resulting from its fabrication process, and conversely, this process can include any step configured to obtain a characteristic of the substrate. The fabrication process of a microelectronic device can utilize any characteristic of the substrate.

[0184] In the examples described, the semiconductor material is silicon. It should be noted that the invention can be applied to other monocrystalline or polycrystalline semiconductors, possibly doped, and in particular to Si, Ge, SiGe, SiC semiconductors, III-V materials (e.g., AIN, GaN, InN, InGaAs, GaP, InP, InAs, AsGa...), and II-VI materials. The dielectric material can be a semiconductor oxide or nitride, for example, SiO₂, SiN, Al₂O₃. The piezoelectric material may, for example, be chosen from lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium-sodium niobate (KxNa1-xNbO3 or KNN), barium titanate (BaTiO3), quartz, lead zirconate titanate (PZT), a lead-magnesium niobate and lead titanate compound (PMN-PT), zinc oxide (ZnO), aluminium nitride (AIN) or aluminium-scandium nitride (AIScN), other materials being of course also possible.

Claims

1. Substrate (3) comprising: • a first layer (30) based on a semiconductive material, • a second layer (31) surmounting the first layer (30), the substrate (3) comprising a plurality of buried vias (32) extending from the second layer (31) over a portion of the first layer (30), each via (32) being delimited by a side wall (320), a bottom wall (321), and an upper wall (322) opposite the bottom wall (321), and in that at least one assembly (32a) of the plurality of vias (32) forms a pattern (32b) repeated along at least one direction of the main extension plane of the first (30) and second (31) layers.

2. Substrate (3) according to the preceding claim, wherein at least some of the vias (32) has an aspect ratio greater than or equal to 10, of the longest dimensions oriented along a dimension in thickness of the first (30) and second (31) layers.

3. Substrate (3) according to any one of the preceding claims, wherein, within a via (32) assembly (32a), two via (32) patterns (32b) repeated successively are separated by a constant pitch along at least one direction of the main extension plane of the first (30) and second (31) layers, the pitch being between 50µm and 300µm.

4. Substrate (3) according to any one of the preceding claims, wherein the substrate (3) comprises several via (32) assemblies (32a, 32a', 32a"), each forming a pattern (32b, 32b', 32b") repeated along at least one direction of the main extension plane of the first (30) and second (31) layers.

5. Substrate (3) according to any one of the preceding claims, wherein at least one via (32) has at least one via configuration from among the following: • the side wall (320) of the via (32) is made of a dielectric material, and the via (32) is filled with an electrically or semiconductive material or the via (32) is hollow, • the side wall (320) of the via (32) is made of a dielectric material, and the via (32) is filled with the material of the first layer (30), • the side wall (320) of the via (32) is made of the material of the first layer (30) and the via is hollow.

6. Substrate (3) according to the preceding claim, wherein at least one via (32) has a first via configuration on a first portion (32c), and a second via configuration distinct from the first via configuration on a second portion (32d), the first (32c) and second (32d) portions extending successively along a dimension in thickness of the first (30) and second (31) layers.

7. Substrate (3) according to any one of the two preceding claims combined with claim 4, wherein at least one assembly (32a, 32a', 32a") has at least one via configuration distinct from another assembly (32a, 32a', 32a").

8. Method for manufacturing the substrate (3) according to any one of the preceding claims, comprising: • a provision of a support sub-substrate (1) comprising at least one first layer (10) based on a semiconductive material, the support sub-substrate (1) having an exposed surface (1a), • the formation of a plurality of vias (32) such that the vias (32) extend from the exposed surface (1a) over a portion of the first layer (10), each via being delimited by a side wall (320) and a bottom wall (321), at least one via (32) assembly (32a) forming a pattern (32b) repeated along at least one direction of the main extension plane of the first (30) and second (31) layers, • a provision of a donor sub-substrate (2) comprising a superficial layer (20, 21) having an exposed surface (2a), • an assembly of the support sub-substrate (1) and of the donor sub-substrate (2) by their exposed surfaces (1a, 2a), so as to cover the vias (32), each via thus being delimited by the side wall (320), the bottom wall (321), and an upper wall (322) opposite the bottom wall (321).

9. Method according to the preceding claim, wherein the formation of the plurality of vias (32) comprises, for at least one via (32a) assembly, and on at least one first portion (32c) of said vias (32), an etching of at least one perimeter of the via (32).

10. Method according to the preceding claim, wherein the formation of the plurality of vias (32) comprises, following the etching at least of the perimeter of the via (32), a formation of a dielectric material over at least the etched perimeter of the via (32), so as to form the side wall (320) of the dielectric material via (32).

11. Method according to the preceding claim, wherein during the etching of at least the perimeter of the via (32), the via (32) is etched over substantially its entire volume, and the formation of the plurality of vias (32) comprises, following the formation of a dielectric material over at least the etched perimeter of the via (32), so as to form the side wall (320) of the dielectric material via (32), a deposition of an electrically conductive or semiconductive material (323), so as to fill the via at least partially.

12. Method for manufacturing a microelectronic device (4) comprising: • a provision of a substrate (3) according to any one of claims 1 to 7 and / or a substrate (3) manufactured by the method according to any one of claims 8 to 11, having a front exposed surface (3a) and a back exposed surface (3b), • a formation of at least one layer portion (40) of the device (4) by a deposition, on at least one from among the front (3a) or back (3b) exposed surfaces of the substrate (3), of said portion, and / or an etching of at least one from among the front (3a) or back (3b) exposed surfaces of the substrate (3), configured so as to form said portion (40), • at at least one via, an etching by one from among the front (3a) or back (3b) exposed surfaces of the substrate (3), until reaching the via, and: ∘ continuing the etching to reach the at least one layer portion (40) of the device (4), or ∘ at the at least one via, an etching by the other from among the front (3a) or back (3b) exposed surfaces of the substrate (3), until reaching the via, • the deposition of at least one electrically conductive or semiconductive member (45), so as to provide electrical continuity to at least the via (32) and the device layer portion (40).

13. Method according to the preceding claim, wherein the method comprises, a selection of at least one via (32') to be etched from among the plurality of vias (32), only some of the plurality of vias (32) being selected as the via (32') to be etched.

14. Method according to the preceding claim, wherein the selection of the at least one via (32') to be etched comprises the application, on said front (3a) or back (3b) exposed surface of the substrate (3), of a mask (42) comprising openings (420) located in vertical alignment with the at least one via (32') to be etched, followed by the etching, so as to reach the at least one via (32') to be etched.

15. Method according to any one of the two preceding claims, wherein, when the method implements the etching by the other from among the front (3a) or back (3b) exposed surfaces of the substrate (3), until reaching the via, the selection of the at least one via (32') to be etched from among the plurality of vias (32) comprises the application, on said other front (3a) or back (3b) exposed surface of the substrate (3), of a mask (42) comprising openings (420) located in vertical alignment with the at least one via (32') to be etched, and the method further comprises an etching so as to reach the at least one via (32') to be etched.