ELECTRONIC CHIP WITH CONNECTION PILLARS

Description

Domaine technique

[0001] This description relates to the field of electrical connection between an electronic chip and a package or between two electronic chips, and more particularly relates to connection pillars of the electronic chip. Technique antérieure

[0002] To connect an electronic chip to an external element, connection pillars or pads may be provided on one side of the electronic chip and connected to conductive tracks of the electronic chip. Thus, it is possible to bring the connection pillars into contact with areas or conductive tracks located on an external element, for example a package or another electronic chip.

[0003] The use of bonding pillars may have certain disadvantages, including the fragility of the bonding pillars when they are small or when they have a high aspect ratio, the aspect ratio being the ratio between the height and the diameter of the bonding pad, the high duration and cost of the bonding pad manufacturing process when the aspect ratio is high, and the risk of the bonding pillars being torn off the face of the electronic chip on which they are formed. Document US 2021 / 082846 describes an electronic circuit comprising conductive pillars extending into a semiconductor substrate. Résumé de l'invention

[0004] The embodiment overcomes all or part of the disadvantages of electronic chips comprising known connection pillars.

[0005] The embodiment provides an electronic circuit comprising a semiconductor substrate having first and second opposing faces and electrically conductive pillars, for connection to an element external to the electronic circuit, extending through the semiconductor substrate from the second face to the first face and projecting from the first face.

[0006] the electronic circuit comprises, for each electrically conductive pillar, an electrically insulating layer located in the semiconductor substrate and completely surrounding the electrically conductive pillar in the semiconductor substrate.

[0007] According to one embodiment, the electronic circuit comprises an active area extending into the semiconductor substrate from the second face and containing at least one electronic component, each electrically conductive pillar further comprising a connection track extending on the second face and electrically connected to the active area.

[0008] The electronic circuit further comprises at least one electrically insulating wall extending through the semiconductor substrate from the second face to the first face and delimiting a semiconductor portion of the semiconductor substrate containing the active zone.

[0009] According to one embodiment, the electrically insulating wall is separated from the electrically insulating layers surrounding the electrically conductive pillars by semiconductor substrate material.

[0010] The electrically insulating layers surrounding the electrically conductive pillars are part of the electrically insulating wall.

[0011] According to one embodiment, each electrically conductive pillar projects from the first face to a height greater than 25 µm.

[0012] An embodiment also provides a method for manufacturing an electronic circuit as defined previously, comprising, for each electrically conductive pillar, the formation in the semiconductor substrate of a first opening extending into the semiconductor substrate from the second face over a portion of the thickness of the semiconductor substrate, and the filling of the first opening with an electrically conductive material.

[0013] According to one embodiment, the method comprises a step of thinning the semiconductor substrate on the side of the first face so that each electrically conductive pillar projects from the first face.

[0014] According to one embodiment, the method comprises, before filling the first openings with the electrically conductive material, a step of forming an electrically insulating layer on the walls of each first opening.

[0015] According to one embodiment, the method comprises forming at least one second opening extending into the semiconductor substrate from the second face over a portion of the thickness of the semiconductor substrate, the second opening being shallower than the first openings, and completely filling the second opening with an electrically insulating material. Brève description des dessins

[0016] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 is a partial, schematic, sectional view of an example of an electronic chip; figure 2 is a partial and schematic sectional view of an embodiment of an electronic chip; the figure 3 , there figure 4 , there figure 5 , there figure 6 , there figure 7 , there figure 8 , there figure 9 , there figure 10 , there figure 11 , there figure 12 , and the figure 13 are each a partial and schematic sectional view of a structure obtained at a step of an embodiment of a method of manufacturing the electronic chip represented in figure 2 ; there figure 14 is a partial, schematic sectional view illustrating the deposition of conductive material from a connection pillar of the electronic chip of the figure 1 ; there figure 15 is a partial, schematic sectional view illustrating the deposition of conductive material from a connection pillar of the electronic chip of the figure 2 ; there figure 16 , there figure 17 , there figure 18 , and the figure 19 are partial and schematic top sectional views of embodiments of the electronic chip of the figure 2 at a stage of the manufacturing process, the embodiments illustrated on the figures 16 And 18 not forming part of the invention; and the figure 20 is a partial, schematic sectional view of an embodiment of an electronic circuit. Description des modes de réalisation

[0017] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0018] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed.

[0019] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0020] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0021] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%. In addition, the terms "insulator" and "conductor" are considered here to mean "electrically insulating" and "electrically conducting", respectively.

[0022] There figure 1 is a partial, schematic, sectional view of an example of an electronic chip 10.

[0023] The 10 electronic chip includes: a semiconductor substrate 12 comprising a lower face 14 and an upper face 16; an insulating layer 18 covering the lower face 14; an active area 20 in the substrate 12 flush with the upper face 16, one or more electronic components, not shown, being formed in and / or on the active area 20; an interconnection structure 22 covering the upper face 16, comprising a stack of insulating layers 24 and conductive tracks 26 in and / or between the insulating layers 24, some of the conductive tracks 26 being in contact with the active area 20; openings 28 in the stack of insulating layers 24 each exposing a portion of one of the conductive tracks 26; and connection pillars or pads 30, two connection pillars being shown by way of example in figure 1 , each pillar being connected to one of the conductive tracks 26.

[0024] Each connection pillar 30 comprises a trunk 32 which extends along an axis A substantially orthogonal to the upper face 16. The trunk 32 comprises a base 34 on the side closest to the substrate 12, an end face 36 opposite the base 34 on the side furthest from the substrate 12, and a side wall 38 connecting the base 34 to the end face 36. The connection pillar 30 further comprises an interface layer 40 interposed between the base 34 and the interconnection structure 22. The pillar 30 further comprises a finishing layer 42 covering the end face 36 and a block 44 of a bonding material covering the finishing layer 42.

[0025] The use of connecting pillars 30 as shown in figure 1 may have certain drawbacks. The connection pillars 30 may be fragile when they are small in size or when they have a high aspect ratio, also called form factor. In addition, each connection pillar 30 is mechanically linked to the interconnection structure 22 only by the interface layer 40. The method for manufacturing the connection pillar 30 may include etching steps that may result in partial etching of the interface layer 40 from its periphery. This weakens the connection between the trunk 32 and the interconnection structure 22. An increased risk of the connection pillar 30 being torn off from the connection structure 22 may then be observed. In addition, when the trunk 32 of the connection pillar 30 is made of copper, the trunk 32 is generally manufactured by electrodeposition by depositing copper from the interface layer 34.A disadvantage is then the high duration and cost of the manufacturing process of the connection pad 30 when the aspect ratio of the connection pad 30 is high.

[0026] There figure 2 is a partial and schematic sectional view of an example of an electronic chip 50. The electronic chip 50 comprises all of the elements of the electronic chip 10 of the figure 1 with the difference that the connection pillars 30 are replaced by connection pillars or pads 60.

[0027] According to one embodiment, each connection pillar 60 comprises: a trunk 62 which extends along an axis Δ substantially orthogonal to the upper face 16 and which passes through the substrate 12 from the upper face 16 to the lower face 14 and projects out of the substrate 12 from the lower face 14, the trunk 62 having a base 64 on the side closest to the upper face 16 of the substrate 12, an end face 66 opposite the base 64 on the side closest to the lower face 14 of the substrate 12, and a side wall 68 connecting the base 64 to the end face 66; an interface layer 70 covering the side wall 68 of the trunk 62 and in direct physical contact with the side wall 68; a finishing layer 72 covering the end face 66 and in direct physical contact with the end face 66; a block 74 of a bonding material covering the finishing layer 72;a connection track 76 on the interconnection structure 22 and connecting the base 64 of the trunk 62 to one of the conductive tracks 26 in one of the openings 28, the interface layer 70 also being present between the connection track 76 and the interconnection structure 22; and an insulating layer 77 covering each connection track 76.;

[0028] The electronic chip 50 further comprises, for each pillar 60, an insulating layer 78 located in the substrate 12 and surrounding the trunk 62 over the entire part of the trunk 62 extending into the substrate 12 and interposed between the trunk 62 and the substrate 12. The insulating layer 78 extends into the substrate 12 over the entire thickness of the substrate 12, from the lower face 14 to the upper face 16. The insulating layer 78 is in direct physical contact with the interface layer 70.

[0029] The electronic chip 50 further comprises a lateral electrical insulation wall 80 which extends in the substrate 12 over the entire thickness of the substrate 12, from the lower face 14 to the upper face 16. The wall 80 electrically insulates a portion of the substrate 12 containing the active zone 20 from the rest of the substrate 12.

[0030] Each pillar 60 is anchored in the substrate 12 over the entire thickness of the substrate 12. The mechanical strength of the connection pillar 60 is therefore advantageously improved compared to the pillar 30. In addition, the risk of the connection pillar 60 being torn off is reduced.

[0031] According to one embodiment, the substrate 12 is made of silicon (Si), silicon carbide (SiC), a III-V compound, in particular gallium nitride (GaN), or a II-VI compound. The substrate 12 may have a single-layer or multi-layer structure, for example a silicon-on-insulator (SOI) type structure. For example, the substrate 12 may comprise a GaN layer covering a silicon support. According to one embodiment, the thickness of the substrate 12 is between 50 µm and 300 µm.

[0032] The trunk 62 may have a substantially cylindrical shape with axis Δ with a circular, square, rectangular base, etc. The average diameter D of the trunk 62 is between 10 µm and 150 µm, the average diameter corresponding to the diameter of a trunk with a circular base whose surface is the same as that of the trunk 62. According to one embodiment, the end face 66 is substantially perpendicular to the axis Δ. The trunk 62 and the connection track 76 are made of metal, for example copper, nickel, silver, gold, or an alloy of these metals. The total height H of the trunk 62 from the end face 66 to the upper face of the connection track 76 is between 75 µm and 400 µm. The height of the trunk 62 projecting relative to the insulating layer 18 is between 25 µm and 100 µm. The aspect ratio of the trunk 62, which corresponds to the ratio between the total height H of the trunk 62 and the average diameter D of the trunk 62, is between 0.5 and 40.

[0033] The metal tracks 26 are for example made of materials chosen from copper, a copper alloy, titanium, a titanium alloy, titanium nitride, platinum, and a platinum alloy. According to one embodiment, the thickness of each metal track 26 is between 0.5 µm and 1.5 µm.

[0034] Each insulating layer 18, 24, 77, 78 and each insulating wall 80 may be made of a dielectric material, for example silicon oxide (SiO 2 ), silicon nitride (for example Si 3 N 4 ), silicon oxynitride (for example Si 2 ON 2 ), or hafnium oxide (HfO 2 ). According to one embodiment, the thickness of the insulating layer 18 is between 0.1 µm and 0.5 µm. According to one embodiment, the thickness of each insulating layer 24 is between 0.5 µm and 1.5 µm. According to one embodiment, the thickness of the insulating layer 77 is between 0.5 µm and 1.5 µm. According to one embodiment, the thickness of the insulating layer 78 is between 0.2 µm and 1 µm. According to one embodiment, the thickness of the wall 80 is between 1 µm and 3 µm.

[0035] The thickness of the interface layer 70 is between 10 nm and 1 µm. The interface layer 70 acts as a primer for the formation of the trunk 62 and the connection track 76 of the connection pillar 60. The interface layer 70 may comprise a layer of titanium or chromium, acting as an adhesion layer, and a layer of copper acting as a primer layer for the subsequent formation of the trunk 62 and the connection track 76.

[0036] The thickness of the finishing layer 72 is between 10 nm and 5 µm, for example equal to 3 µm. The finishing layer 72 is made of a conductive material which improves the adhesion of the block 74. The finishing layer 72 is for example made of metal, in particular gold or silver, and optionally comprises one or more bonding layers and / or one or more barrier layers, comprising for example platinum (Pt), palladium (Pd), nickel (Ni), titanium (Ti), chromium (Cr), and / or tantalum (Ta), between the material of the trunk 62 and the material of the block 74 which is deposited on the trunk 62. The finishing layer 72 also makes it possible to avoid oxidation of the end face 66 of the trunk 62 in the case where the assembly process is not carried out in a neutral or reducing atmosphere.

[0037] The material composing the block 74 depends in particular on the assembly method implemented for fixing the electronic chip 50 to another element. The assembly method may in particular comprise a welding step or a sintering step. The material composing the block 74 may comprise an active filler comprising particles of a metallic material, for example silver, copper, tin, or an alloy of these metals. The active filler may further comprise gold and other additives, for example polymers and / or ceramics, not participating in the fixing of the connection pillar but facilitating the methods of implementing the block 74. The height of the block 74, measured from the finishing layer 72 may be approximately 25 µm.

[0038] There figure 3 , there figure 4 , there figure 5 , there figure 6 , there figure 7 , there figure 8 , there figure 9 , there figure 10 , there figure 11 , there figure 12 , and the figure 13 are each a partial and schematic sectional view of a structure obtained at a step of an embodiment of a method of manufacturing the electronic chip 50 shown in figure 2 .

[0039] There figure 3 represents the structure obtained after the formation of the active zone 20 and the formation of the interconnection structure 22 on the upper face 16 of the substrate 12. One or more electronic components, not shown, are formed in and / or on the active zone 20. According to one embodiment, at this stage of the procedure, the substrate 12 corresponds to a plate, and the active zones 20 of several electronic chips are formed in and / or on the substrate 12, the active zones 20 possibly being identical or different. figure 3 , a single active area 20 is shown and the interconnection structure 22 comprises two conductive tracks 26 connected to the active area 20 and an insulating layer 24 covering the conductive tracks 26 and the upper face 16 of the substrate 12 around the conductive tracks 26. At this stage of the process, the thickness of the substrate 12 is greater than the desired final thickness of the substrate 12. The thickness of the substrate 12 at this stage of the process may be between 500 µm and 1.3 mm.

[0040] There figure 4 represents the structure obtained after forming an opening 82 at the desired location of each connection pillar 60 and forming an opening 84 at the desired location of each wall 80. The openings 82 and 84 pass completely through the interconnection structure 22 and extend over a portion of the thickness of the substrate 12 from the upper face 16. The openings 82 have the same depth and the openings 84 have the same depth. The depth of the openings 82 is greater than the depth of the openings 84. According to one embodiment, the depth of the openings 84 is substantially equal to the desired final thickness of the substrate 12. The depth of the openings 84 can be between 50 µm and 300 µm. According to one embodiment, the openings 82 and 84 are produced by deep reactive ion etching (DRIE) steps.Depending on the method used for forming the openings 82 and 84, the openings 82 and the openings 84 may be formed simultaneously or may be formed in separate steps. In particular, with deep reactive ion etching, the etching rate depends on the diameter of the opening such that openings 84 that have a width less than the average diameter of the openings 82 may be formed simultaneously with the openings 82.

[0041] There figure 5 represents the structure obtained after the formation of the insulating layer 78 in each opening 82 and the formation of the insulating wall 80 in each opening 84. At this stage of the method, the insulating layer 78 covers the side walls and the bottom of the opening 82. This step may comprise the deposition of an insulating layer simultaneously on the walls of the opening 84 and on the walls of the opening 82, the thickness of the insulating layer being such that it completely fills the opening 84 but does not completely fill each opening 82 so that a cavity 86 is present in each opening 82 after the formation of the insulating layer.

[0042] There figure 6 represents the structure obtained after the formation, for each connection pillar to be produced, of the opening 28 in the insulating layer 24 to expose one of the conductive tracks 26, the deposition of a mask 88 on the insulating layer 24 comprising, for each connection pillar to be produced, an opening 90 exposing the cavity 86, the opening 28 and the part of the insulating layer 24 connecting the cavity 86 to the opening 28, and the formation of the interface layer 70 in each opening 90. At this stage of the method, the interface layer 70 covers all the walls of the cavity 86, in particular the side walls and the bottom of the cavity 86, the walls of the opening 28, and the exposed part of the insulating layer 24 connecting the cavity 86 to the corresponding opening 28. The mask 88 may correspond to a film which is applied to the insulating layer 24.

[0043] There figure 7 represents the structure obtained after, for each connection pillar to be produced, the complete filling of each cavity 86 with a conductive material, thus forming the trunk 62 of the connection pillar, and the formation of the connection portion 76 of each connection pillar. The conductive material making up the trunk 62 can be deposited by electrodeposition on the interface layer 70. In this case, the deposition of the conductive material is carried out from the interface layer 70 in a direction substantially perpendicular to the interface layer 70. This advantageously makes it possible to fill the cavity 86 even if the form factor of the cavity 86, i.e. the ratio between the height of the cavity and the diameter of the cavity, is high, since the deposition of the conductive material is carried out in particular from the side walls of the cavity 86.

[0044] There figure 8 represents the structure obtained after the removal of the film 88 and the formation, for each connection pillar, of the insulating layer 77 covering the connection track 76.

[0045] There figure 9 represents the structure obtained after etching the substrate 12 from the lower face 14 of the substrate 12. At the end of the etching step, for each connection pillar, a part of the trunk 62, surrounded by the interface layer 70 and the insulating layer 78, projects from the substrate 12 from the lower face 14 over a height H'. The etching step may comprise a selective chemical etching with respect to the material composing the insulating layer 78. According to one embodiment, the etching of the substrate 12 is stopped when the end of the wall 80 is flush with the lower face 14. The height H' is fixed by the etching step.

[0046] There figure 10 represents the structure obtained after the formation of the insulating layer 18 on the lower face 14 of the substrate 12. According to one embodiment, the insulating layer 18 is composed of the same material as the insulating layer 78 and the thickness of the insulating layer 18, at this stage of the method, is substantially equal to the sum of the thickness of the insulating layer 78 and the desired final thickness of the insulating layer 18, for example equal to twice the thickness of the insulating layer 78.

[0047] There figure 11 represents the structure obtained after the complete etching of the portion of the insulating layer 78 which is exposed on the side of the lower face 14 of the substrate 12. This step can further result in the etching of the insulating layer 18 over the thickness of the insulating layer 78. The insulating layer 18 having the desired final thickness is then obtained.

[0048] There figure 12 represents the structure obtained after, for each connection pillar 60, the etching of the interface layer 70 covering the end face 66, the formation of the finishing layer 72 and the formation of the block 74 of the connecting material.

[0049] There figure 13 represents the structure obtained after a cutting step to separate the electronic chips 50. According to one embodiment, the cutting lines 91 are located between the walls 80 of adjacent electronic chips 50.

[0050] Each electronic chip 50 thus individualized can then be attached to an external element, for example a housing or another electronic chip. The wall 80 protects the active zone 20 of the electronic chip 50 in particular against electrostatic discharges at the side walls of the electronic chip 50 during handling and attachment of the electronic chip 50 to the external element.

[0051] There figure 14 is a partial and schematic sectional view illustrating the formation of a connection pillar 30 of the electronic chip of the figure 1 . There figure 14 represents the structure obtained after the deposition of a mask 92 on the interconnection structure 22 comprising, for each connection pillar to be produced, an opening 94 exposing the opening 28, the formation of the interface layer 40 on the part of the interconnection structure 22 exposed in the opening 94, and the deposition of the conductive material to form the trunk 32 of the connection pillar. The conductive material making up the trunk 32 can be deposited by electrodeposition on the interface layer 70. In this case, the deposition of the conductive material is carried out from the interface layer 70 in a direction substantially perpendicular to the interface layer 70, as illustrated by the arrows F1 parallel to the axis A of the trunk 32. To form the trunk 32, it is thus necessary to deposit the conductive material substantially over a height H" measured along the axis A.The accuracy of the height H" of the trunk 62 that can be achieved depends essentially on the accuracy that can be achieved with the electroplating process.

[0052] There figure 15 is a partial, schematic sectional view illustrating the formation of a connection pillar 60 of the electronic chip of the figure 2 corresponding to the step described previously in relation to the figure 7 The conductive material making up the trunk 62 can be deposited by electrodeposition on the interface layer 70. In this case, the deposition of the conductive material is carried out from the interface layer 70 in a direction substantially perpendicular to the interface layer 70 as illustrated by the arrows F2. To form the trunk 62, it is thus necessary to deposit the conductive material substantially over a thickness equal to half the average diameter D of the trunk 62. The duration of the step of forming the trunk 62 is therefore substantially independent of the total height of the trunk 62, and also of the height of the trunk 62 which, on the electronic chip once finished, is protruding from the side of the lower face 14 of the substrate 12. Indeed, this height is defined by the step of thinning the substrate 12 described previously in relation to the figure 9 . As half of the average diameter D of the trunk 62 is less than the height H" indicated in figure 14 , the duration of the step of forming the trunk 62 by electrodeposition can advantageously be reduced compared to the duration of forming the trunk 32.

[0053] The precision on the height H of the trunk 62 that can be achieved depends essentially on the precision that can be achieved by the etching method used to form the opening 82. Advantageously, the precision that can be achieved on the height H of the trunk 62 is greater than the precision that can be achieved on the height H" of the trunk 32. Furthermore, the precision that can be achieved on the height of the part of the trunk 62 projecting from the side of the lower face 16 depends essentially on the precision that can be achieved by the etching method used to form the opening 82 and the precision that can be achieved by the method used for thinning the substrate 12. Advantageously, the precision that can be achieved on the height of the part of the trunk 62 projecting from the side of the lower face 16 is greater than the precision that can be achieved on the height H" of the trunk 32.The homogeneity of the heights of the projecting parts of the connection pillars 60 is improved.

[0054] There figure 16 , there figure 17 , there figure 18 , and the figure 19 are each a partial and schematic top sectional view of the structures obtained in the step described previously in relation to the figure 5 for different embodiments of the electronic chip of the figure 2 . For the figures 16 à 19 , the cutting plane is located between the lower face 14 and the upper face 16 of the substrate 12 and is parallel to the upper face 16. The embodiments illustrated in the figures 16 And 18 are not part of the invention.

[0055] On the figures 16 et 17 , the openings 82 are of circular cross-section. On the figures 18 et 19 , the openings 82 are rectangular in section with rounded corners.

[0056] On the figures 16 And 18, the wall 80 is separated from each insulating layer 78 by a portion of the substrate 12 and surrounds the two openings 82. On the figures 17 And 19 , the wall 80 comprises two sub-walls 80A and 80B, each sub-wall 80A and 80B joining at its ends the insulating layer 78 intended to surround a connection pillar. The insulating layers 78 intended to surround the connection pillars then form part of the wall 80.

[0057] Advantageously, according to the embodiment described previously in relation to the figures 3 à 13 , the wall 80 is formed simultaneously with the openings 82 and the insulating layers 78. There are therefore no additional steps to be provided for the formation of the wall 80.

[0058] There figure 20 is a partial and schematic sectional view of an embodiment of an electronic circuit 100.

[0059] The electronic circuit 100 comprises a stack of two electronic chips 50A and 50B each having the structure illustrated in figure 2 . The active areas 20 of the electronic chips 50A and 50B may contain different and / or differently arranged electronic components. The connection pads 60 of the electronic chip 50A are fixed to the electronic chip 50B on the side of the upper face 16 of the electronic chip 50B. In figure 20 , the connection pads 60 of the electronic chip 50A are fixed to the connection tracks 76 of the electronic chip 50B through openings 102 provided in the insulating layer 77 covering the connection tracks 76 of the electronic chip 50B.

[0060] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0061] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. An electronic circuit (50) comprising: - a semiconductor substrate (12) having opposed first and second faces (14, 16); - electrically conductive pillars (60), intended to be connected to an element external to the electronic circuit, extending through the semiconductor substrate (12) from the second face (16) to the first face (14) and projecting from the first face (14); - for each electrically conductive pillar (60), an electrically insulating layer (78) located in the semiconductor substrate (12) and completely surrounding the electrically conductive pillar in the semiconductor substrate (12); - at least one electrically insulating wall (80) extending through the semiconductor substrate (12) from the second face (16) to the first face (14), and delimiting a semiconductor portion of the semiconductor substrate (12) containing the active area (20), characterized in that the electrically insulating layers (78) surrounding the electrically conductive pillars (60) are part of the electrically insulating wall (80)2. The electronic circuit according to claim 1, comprising an active area (20) extending into the semiconductor substrate (12) from the second face (16) and including at least one electronic component, each electrically conductive pillar (60) further comprising a connection track (76) extending over the second face (16) and electrically connected to the active area (20).

3. The electronic circuit according to claim 1 or 2, wherein each electrically conductive pillar (60) projects from the first face (14) to a height greater than 25 µm.

4. A method of manufacturing an electronic circuit (60) according to claim 1, comprising, for each electrically conductive pillar (60), forming in the semiconductor substrate (12) a first opening (82) extending into the semiconductor substrate (12) from the second face (16) over a part of the thickness of the semiconductor substrate (12), and filling the first opening (82) with an electrically conductive material.

5. The method according to claim 4, comprising a step of thinning the semiconductor substrate (12) on the side of the first face (14) so that each electrically conductive pillar (60) projects from the first face (14).

6. The method according to claim 4 or 5, comprising, prior to filling the first openings (82) with the electrically conductive material, a step of forming an electrically insulating layer (78) on the walls of each first opening (82).

7. The method according to any one of claims 4 to 6, comprising forming at least one second opening (84) extending into the semiconductor substrate (12) from the second face (16) over part of the thickness of the semiconductor substrate (12), the second opening (84) being shallower than the first openings (82), and completely filling the second opening (84) with electrically insulating material.