Microelectronic die including swappable phy circuitry and semiconductor package including same

EP4457861A4Pending Publication Date: 2026-01-21INTEL CORP
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Patent Information

Application Number
EP2022917424
Authority / Receiving Office
EP · EP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2022-05-26
Filing Date
2022-11-30
Publication Date
2026-01-21

AI Technical Summary

Technical Problem

Current microelectronic die-to-die interconnect technologies face challenges in achieving high interconnect wire densities, with standard interconnect regimes offering lower bandwidth compared to advanced regimes, and existing PHY configurations are tailored to specific interconnect regimes, limiting flexibility and efficiency.

Method used

The implementation of a microelectronic die with swappable PHY circuitry that can be configured for either standard or advanced interconnect regimes by enabling/disabling electrical pathways, allowing the same die to be used in both configurations with compatible electrical contact structures, thereby supporting identical PHY circuit designs for both standard and advanced package interconnects.

Benefits of technology

This approach enables the reuse of the same die in various interconnect regimes, increasing reusability and reducing development costs, while allowing for faster time-to-market and mixed-mode chiplet/SOC customizations, thereby enhancing the die's technical advantages and longevity.

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Abstract

A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.
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Citation Information

Patent Citations

  • Multi-die memory device

    US20160225431A1

  • Scalable and interoperable phyless die-to-die IO solution

    US20210398906A1