Charger for wide input / output voltage regulation

Abstract

A charger configured for wide input / output voltage regulation. The charger includes a low- frequency half-bridge switching device circuit, a high-frequency half-bridge switching device circuit and a controller configured to receive an output DC voltage reference. The controller is configured to determine a DC-bus voltage reference and determine a switching frequency based on the DC-bus voltage reference. The controller is configured to determine if the switching frequency is above a threshold frequency and if so, perform pulse power transfer control, else perform variable frequency modulation control. The controller is configured to receive an output charging current and determine if the output charging current is under a current threshold, and if so, disable the low-frequency half-bridge switching device circuit. The charger may also be referred to as an efficient single-stage resonant AC / DC converter that provides a wide input AC voltage regulation and a wide output DC voltage regulation.

Description

[0001] CHARGER FOR WIDE INPUT / OUTPUT VOLTAGE REGULATION

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of alternating current (AC) to direct current (DC) converter; and more specifically, to a charger configured for wide input / output voltage regulation.

[0004] BACKGROUND

[0005] With increasing demands for more powerful smartphones, tablets, and laptops with larger screens and fifth generation (5G) features, a huge market for next generation of alternating current (AC) to direct current (DC) adapters has been created to quickly charge larger lithium (Li)-ion batteries. The quick charging means higher power density is required with smaller size. Conventionally, two-stage AC / DC converters have been used but these converters have their own limitations. In the conventional two-stage AC / DC converters, high efficiency is achieved due to increased number of semiconductors, improved magnetic components designs and reduced switching frequency. However, the aforementioned factors lead to a decrease in power density due to the input energy being processed in two steps which further increase the cost of power conversion when compared with low power level applications.

[0006] Currently, various attempts have been made to design an AC / DC converter with low-cost, small form-factor and high efficiency. For example, a conventional single stage AC / DC converter incorporates a diode bridge at an input stage and a control technique that combines asymmetric duty cycle (or asymmetric pulse width modulation, APWM) with DC-bus voltage regulation and pulse frequency modulation (PFM) with output voltage regulation. The control technique resolved the high DC-bus voltage stress but the duty cycle reduces as the amplitude of the input voltage increases leading to more losses. This means to achieve a higher duty cycle, the DC-bus voltage has to increase and such increase causes a decrease in efficiency as the input voltage increases. Therefore, the conventional single stage AC / DC converter together with the APWM control technique is only suitable for low input grid voltages owing to higher duty cycle at an operating point. Moreover, the conventional single stage AC / DC converter manifests a flat gain characteristics curve and therefore, it becomes difficult to provide wide output voltage regulation. Additionally, the conventional single stage AC / DC converter comprises the diode bridge at the input stage which also contributes to a reduced efficiency by additional conduction losses which occur on the diode bridge itself. Thereafter, another conventional single stage AC / DC converter is proposed with use of additional components to an inductor-inductor-capacitor (LLC) resonant converter in order to create a third harmonic injection resonant tank. The third harmonic injection resonant tank partially solves the technical challenge of the wide output voltage regulation by making the flat gain characteristics curve of the conventional single stage AC / DC converter a little sharp. However, a few limitations are also associated with the other conventional single stage AC / DC converter, such as the use of more magnetic components leads to more losses, a bulky size and a high cost. Thus, there exists a technical problem of an inefficient AC / DC converter which has low input and output voltage regulation, high cost, and high conduction losses and therefore, manifests a low power density and peak efficiency.

[0007] Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional single stage AC / DC converters.

[0008] SUMMARY

[0009] The present disclosure provides a charger configured for wide input / output voltage regulation. The present disclosure provides a solution to the existing problem of an inefficient AC / DC converter which has low input and output voltage regulation, high cost, and high conduction losses and therefore, manifests a low power density and peak efficiency. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art, and provide an improved charger configured for wide input / output voltage regulation.

[0010] The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

[0011] In one aspect, the present disclosure provides a charger configured for wide input / output voltage regulation. The charger comprises a low-frequency half-bridge switching device circuit, a high-frequency half-bridge switching device circuit and a controller configured to receive an output DC voltage reference. The controller is further configured to determine a DC-bus voltage reference and determine a switching frequency based on the DC-bus voltage reference. The controller is further configured to determine if the switching frequency is above a threshold frequency and if so, perform pulse power transfer (PPT) control, and if not perform variable frequency modulation (VFM) control. The controller is further configured to receive an output charging current and determine if the output charging current is under a current threshold, and if so, disable the low-frequency half-bridge switching device circuit.

[0012] The disclosed charger may also be referred to as an efficient single-stage resonant AC / DC converter that provides a wide range of input AC voltage regulation (e.g., 85-265 Vac) and a wide range of output DC voltage regulation (e.g., 5-20 Vdc). The disclosed charger also regulates the power as low as 1 Watt (W) to 75W in PPT mode and up to 150W in average current mode (ACM) or VFM mode without using third harmonic injection resonant tank which requires additional components as used in a conventional AC / DC converter. The disclosed charger enables a bridgeless solution due to the use of the low-frequency halfbridge switching device circuit replacing a conventional bridge of input diodes which reduces the conduction losses. Moreover, the charger manifests low cost, small size and high-power density and peak efficiency. Therefore, the charger may be used as a smart phone or a laptop charger and even for general household appliances, such as a smart television (TV), vacuum cleaners, and the like.

[0013] In an implementation form, the controller is further configured to, if the switching frequency is above the threshold frequency, determine a PPT mode duty cycle. The controller is further configured to determine if the PPT mode duty cycle is equal to 1, and if so, perform variable frequency modulation (VFM) control else, perform pulse power transfer (PPT) control.

[0014] By virtue of performing the controller in the VFM control mode or the PPT control mode depending on the switching frequency, the threshold frequency and the duty cycle, the charger achieves a controlled PFC duty cycle, high power density, high peak efficiency and small root mean square (RMS) current flowing through the switching device circuits.

[0015] In a further implementation form, the controller is further configured to set gates of the low- frequency half-bridge switching device circuit to low if the output charging current is under the current threshold.

[0016] This is advantageous to set the gates of the low-frequency half-bridge switching device circuit to low in an extreme light load condition (e.g., power<10W) in order to block reverse power flow which further prevents production of excessive power in the extreme light load condition.

[0017] In a further implementation form, the controller is further configured to set the high frequency duty cycle to a constant value.

[0018] The fixing of the duty cycle to the constant value ensures the production of an exact energy required at the extreme light load condition and at the same time keeps the DC-bus voltage low.

[0019] In a further implementation form, the controller is further configured to set the switches of the low-frequency half-bridge switching device circuit based on a grid frequency.

[0020] In a further implementation form, the controller is further configured to set the switches of the low-frequency half-bridge switching device circuit to turn-off during the zero-crossing area and set to turn-on complementarily in each half-cycle of the grid frequency after the zero-crossing area.

[0021] This is advantageous as it allows to operate the charger in a discontinuous conduction mode (DCM) and in a continuous conduction mode (DCM), respectively, and ensures zero-voltage switching (ZVS) at all operating points.

[0022] In a further implementation form, the controller is further configured to, when performing pulse power transfer (PPT) control, disable the VFM control loop and set the switching frequency to the highest allowable frequency.

[0023] In a further implementation form, the controller is further configured to adapt the switching frequency in steps as the output load and output voltage of the charger changes.

[0024] This is advantageous to change the switching frequency in steps as the output load and output voltage of the charger changes in order to reduce the switching losses and achieve enough gain.

[0025] In a further implementation form, the controller is further configured to adapt a DC-bus voltage linearly based on the output power and voltage.

[0026] The adaptation of the DC-bus voltage linearly based on the output power and voltage reduces the switching losses. In a further implementation form, the charger further comprises an AND gate configured to combine a high frequency PWM signal and a pulse PWM signal to supply a combined PWM signal for the high frequency half-bridge switching device circuit during the PPT mode.

[0027] The AND gate is used to generate a high frequency PWM signal (i.e., the combined PWM signal) which is used to regulate the switches of the high frequency half-bridge switching device circuit during the PPT mode.

[0028] In a further implementation form, the charger further comprises a bridgeless rectifier stage comprising a boost inductor, and a DC-bus capacitor coupled with a switching resonant stage.

[0029] The DC-bus capacitor acts as a power decoupler hence, the charger requires no additional components for cancellation of low frequency ripples (e.g., 100Hz).

[0030] In a further implementation form, the switching resonant stage comprises a resonant inductor, a resonant capacitor and a high frequency transformer connected to the output synchronous rectification switching devices.

[0031] In a further implementation form, the controller further comprises a modulation controller for an integrated power factor correction (PFC)+LLC stage and the output stage regulation uses variable frequency modulation (VFM) controller in normal operation and pulse power transfer (PPT) controller in PPT operation mode to simultaneously achieve wide AC input voltage and wide DC output voltage regulation, respectively.

[0032] The modulation controller enables the charger to achieve the wide input AC voltage regulation (e.g., 85-265 Vac) and the wide output DC voltage regulation (e.g., 5-20 Vdc). Moreover, the modulation controller enables the charger to have an increased power factor (e.g., 95%) and a reduced total harmonic distortion (e.g., below 10%).

[0033] In a further implementation form, the modulation controller comprises a PFC stage with an outer loop for the DC-bus voltage control, an inner current loop and zero-crossing compensation algorithm for generating the converter duty cycle.

[0034] The Zero-crossing compensation algorithm maintains the converter gain in the zero-crossing region which is incorporated into the ACM control that regulates the DC-bus voltage and produce an output PFC duty cycle which is known as the HF duty cycle in this case. It is to be appreciated that all the aforementioned implementation forms can be combined.

[0035] It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

[0036] Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

[0037] BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

[0039] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

[0040] FIG. 1 is a circuit diagram of a charger, in accordance with an embodiment of the present disclosure; FIG. 2 is a block diagram that illustrates various exemplary components of a controller, in accordance with an embodiment of the present disclosure;

[0041] FIG. 3 is a graphical representation that illustrates pulse power transfer (PPT) control technique of a controller, in accordance with an embodiment of the present disclosure;

[0042] FIG. 4 illustrates a control technique used by a controller in detail, in accordance with an embodiment of the present disclosure;

[0043] FIG. 5 is a flowchart that illustrates a control technique performed by a controller during normal and PPT mode of operation, in accordance with an embodiment of the present disclosure;

[0044] FIG. 6A illustrates measured efficiency curves obtained at a range of an output voltage and at a low input AC voltage, in accordance with an embodiment of the present disclosure;

[0045] FIG. 6B illustrates measured efficiency curves obtained at a range of an output voltage and at a high input AC voltage, in accordance with an embodiment of the present disclosure;

[0046] FIG. 7 illustrates the performance of a converter in terms of power factor (PF) against load, in accordance with an embodiment of the present disclosure;

[0047] FIG. 8 illustrates variation of measured total harmonic distortion values of a converter with an increase in harmonic number at high input AC voltage, in accordance with an embodiment of the present disclosure; and

[0048] FIG. 9 is a circuit diagram of a charger, in accordance with another embodiment of the present disclosure.

[0049] In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the nonunderlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

[0050] DETAILED DESCRIPTION OF EMBODIMENTS

[0051] The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

[0052] FIG. 1 is a circuit diagram of a charger, in accordance with an embodiment of the present disclosure. With reference to FIG. 1, there is shown a circuit diagram of a charger 100 that comprises a low-frequency half-bridge switching device circuit 102, a high-frequency halfbridge switching device circuit 104, a controller 106, a bridgeless rectifier stage 108 and a switching resonant stage 110. The bridgeless rectifier stage 108 includes a boost inductor 112 and a DC-bus capacitor 114. The switching resonant stage 110 includes a resonant inductor 116, a resonant capacitor 118 and a high-frequency transformer 120 connected to an output synchronous rectification switching device circuit 122 before connection to an output capacitor 124 which is configured to power an output load 126. There is further shown an input electromagnetic interference (EMI) filter 128. Each of the charger 100, the controller 106, the switching resonant stage 110, the boost inductor 112, the DC-bus capacitor 114, the resonant inductor 116, the resonant capacitor 118, the high-frequency transformer 120, the output synchronous rectification switching device circuit 122 and the output capacitor 124 is represented by a dashed box, which is used for illustration purpose only and does not form a part of the circuitry.

[0053] The charger 100 is configured for wide input / output voltage regulation. The charger 100 may also be referred to as a single-stage resonant alternating current (AC) to direct current (DC) converter. The charger 100 is configured to use a new control technique that uses a mix of average current mode (ACM), variable frequency modulation (VFM) and pulse power transfer (PPT) control modulation. The new control technique provides the benefits of wide input and wide output voltage regulation, high efficiency due to zero voltage switching (ZV S) which makes it possible to increase power density and switching frequency leading to a smaller size of the charger 100. The new control technique is described in detail, in a following way.

[0054] The charger 100 comprises the low-frequency half-bridge switching device circuit 102, the high-frequency half-bridge switching device circuit 104 and the controller 106. The low- frequency half-bridge switching device circuit 102 includes two low-frequency metal oxide semiconductor field effect transistor (MOSFET) switches (may also be represented as Sa and Sb) which, are used as low-frequency (e.g., 50Hz) switching elements. Each of the low- frequency MOSFET switches (i.e., Sa and Sb) has a gate terminal (may also be represented as gsa and gsb), a drain terminal and a source terminal. Similarly, the high-frequency halfbridge switching device circuit 104 includes two high-frequency MOSFET switches (may also be represented as Si and S2) which, are used as high-frequency (e.g., above 200kHz) switching elements. Each of the high-frequency MOSFET switches (i.e. , Si and S2) has a gate terminal (may also be represented as gsi and gS2), a drain terminal and a source terminal. Moreover, each of the high-frequency MOSFET switches (i.e., Si and S2) may also be referred to as a gallium-nitride (GaN) transistor. The controller 106 is configured to control the functioning of the low-frequency half-bridge switching device circuit 102 (i.e., Sa and Sb), and the high-frequency half-bridge switching device circuit 104 (i.e., Si and S2). The controller 106 is configured to control the ACM, VFM and PPT modulation as well. Alternatively stated, the controller 106 is configured to execute the new control technique which is described in detail, for example, in FIG. 2.

[0055] The controller 106 is configured to receive an output DC voltage reference and determine a DC-bus voltage reference. In order to control the various operating modes of the charger 100 (i.e., the single stage resonant AC / DC converter), the controller 106 is configured to receive the output DC voltage reference (may also be represented as Voref) and determine the DC- bus voltage reference (may also be represented as Vbusref) based on the received output DC voltage reference (i.e., Voref).

[0056] The controller 106 is further configured to determine a switching frequency based on the DC-bus voltage reference and determine if the switching frequency is above a threshold frequency and if so, perform pulse power transfer (PPT) control, and if not perform variable frequency modulation (VFM) control. Based on the DC-bus voltage reference (i.e., Vbusref), the controller 106 is configured to determine the switching frequency (may also be represented as fsw). The controller 106 is further configured to determine if the switching frequency (i.e., fsw) is above the threshold frequency (may also be represented as fth) or not. In a case, if the switching frequency (i.e., fsw) is above the threshold frequency (i.e., fth) then, the controller 106 is configured to perform the PPT control, described in detail, for example, in FIGs. 2 and 4. Otherwise, the controller 106 is configured to perform the VFM control, described in detail, for example, in FIGs. 2 and 4.

[0057] The controller 106 is further configured to receive an output charging current and determine if the output charging current is under a current threshold, and if so, disable the low- frequency half-bridge switching device circuit 102. Furthermore, the controller 106 is configured to receive the output charging current (may also be represented as io) and determine if the output charging current (i.e., io) is under the current threshold or not. In a case, if the output charging current (i.e., io) is under the current threshold, then the controller 106 is configured to disable the low-frequency half-bridge switching device circuit 102 (i.e., Sa and Sb).

[0058] In accordance with an embodiment, the charger 100 further comprises the bridgeless rectifier stage 108 comprising the boost inductor 112, and the DC-bus capacitor 114 coupled with the switching resonant stage 110. In addition to the low-frequency half-bridge switching device circuit 102 (i.e., Sa and Sb), the high-frequency half-bridge switching device circuit 104 (i.e., Si and S2) and the controller 106, the charger 100 comprises the bridgeless rectifier stage 108. The bridgeless rectifier stage 108 includes the boost inductor 112 (may also be represented as Lb) and the DC-bus capacitor 114 (may also be represented as Cb). The DC- bus capacitor 114 (i.e., Cb) is coupled with the switching resonant stage 110 and used as a power decoupler.

[0059] In accordance with an embodiment, the switching resonant stage 110 comprises the resonant inductor 116, the resonant capacitor 118 and the high-frequency transformer 120 connected to the output synchronous rectification switching device circuit 122. The switching resonant stage 110 includes the resonant inductor 116 (may also be represented as Lr), the resonant capacitor 118 (may also be represented as Cr), the high-frequency transformer 120 (may also be represented as T12) and the output synchronous rectification (SR) switching device circuit 122. The output synchronous rectification switching device circuit 122 includes two output synchronous rectification MOSFET switches (may also be represented as SRi and SR2).

[0060] In an implementation, the charger 100 (i.e., the single stage resonant AC / DC converter) is configured to receive an input power from an AC source (may also be represented as Vac) through the input EMI filter 128. The input EMI filter 128 can be realized either as a single- stage or as a two stage common mode (CM) filter or a differential filter (DF). The input EMI filter 128 includes two output terminals, such as a first output terminal (e.g., a positive terminal) and a second output terminal. The first output terminal of the input EMI filter 128 is connected at a point A to the bridgeless rectifier stage 108 (may also be referred to as an input stage) which is comprised of the boost inductor 112 (i.e., Lb), connected to a midpoint B of the high-frequency half-bridge switching device circuit 104 (i.e., Si and S2). The midpoint B connects to the switching resonant stage 110 consisting of the resonant inductor 116 (i. e. , Lr) and the resonant capacitor 118 (i.e., Cr). One of the terminals of the resonant inductor 116 (i.e., Lr) is connected to the midpoint B and another terminal is connected to one terminal of the resonant capacitor 118 (i.e., Cr). Another terminal of the resonant capacitor 118 (i.e., Cr) is connected to primary windings of the high-frequency transformer 120 (i.e., T12) and secondary windings are connected to the output SR switching device circuit 122 (i.e., SRi and SR2) which is further connected to the output capacitor 124 (may also be represented as Co). The output capacitor 124 (i.e., Co) is configured to power the output load 126 (may also be represented as Ro). Moreover, the second output terminal (e.g., a negative terminal) of the input EMI filter 128 is connected to a midpoint C of the low- frequency half-bridge switching device circuit 102 (i.e., Sa and Sb).

[0061] FIG. 2 is a block diagram that illustrates various exemplary components of a controller, in accordance with an embodiment of the present disclosure. FIG. 2 is described in conjunction with elements from FIG. 1. With reference to FIG. 2, there is shown a block diagram of the controller 106 (of FIG. 1) that includes a modulation controller 202 for a power factor correction (PFC) stage 204 and the switching resonant stage 110, a variable frequency modulation (VFM) controller 206 and a pulse power transfer (PPT) controller 208. The PFC stage 204 is represented by a dashed box, which is used for illustration purpose only, and does not form a part of circuitry.

[0062] Initially, the controller 106 is configured to receive the output DC voltage reference (i.e., Voref). Based on the received output DC voltage reference (i.e., Voref), the controller 106 is configured to determine the DC-bus voltage reference (i.e., Vbusref).

[0063] In accordance with an embodiment, the controller 106 further comprises the modulation controller 202 for the integrated PFC stage 204 + LLC stage and the output stage regulation uses variable frequency modulation (VFM) controller 206 in normal operation and pulse power transfer (PPT) controller 208 in PPT operation mode to simultaneously achieve wide AC input voltage (85-265Vrms) and wide DC output voltage (5-20Vdc) regulation respectively. Alternatively stated, the controller 106 comprises the modulation controller 202 (may also be referred to as a PWM modulator) for the PFC stage 204 and the switching resonant stage 110 (may also be referred to as inductor-inductor-capacitor (LLC)), the VFM controller 206 and the PPT controller 208. The modulation controller 202 (may also be referred to as an average current mode, ACM, controller) regulates the PFC stage 204 required from an input to DC-bus voltage (may also be represented as Vb). The VFM controller 206 is used to regulate an output voltage and at the same time, generates the switching frequency (i.e., fsw) during normal operation mode from 75 Watts (W) to 150W. The ACM and VFM control technique provides the voltage regulation from 11 -20V (power>20W) for low AC input voltage (120Vac) and for only 20V (power>60W) for high AC input voltage (230Vac) without the switching frequency (i.e., fsw) exceeding the set threshold frequency (i.e., fth). The PPT controller 208 provides a wide output voltage regulation from 5Vdc to 20Vdc and extreme light load control from 1W to 75W.

[0064] In accordance with an embodiment, the modulation controller 202 comprises a PFC stage with an outer loop for DC-bus voltage control, an inner current loop and zero crossing compensation algorithm for generating the converter duty cycle (HF duty). The modulation controller 202 comprises the PFC stage 204, the outer loop for the DC-bus voltage control, the inner current loop and zero crossing compensation algorithm for generating the converter (i.e., the single stage resonant AC / DC converter) duty cycle (or high frequency duty cycle). The converter (i.e., the single stage resonant AC / DC converter) duty cycle is saturated between 0.2 and 0.8 according to the converter gain. The zero-crossing compensation algorithm is used to maintain the converter (i.e., the single stage resonant AC / DC converter) gain near zero-crossing region by saturating the duty cycle to have a limit of 0.2<duty<0.8, clamp and turn off the low-frequency half-bridge switching device circuit 102 (i.e., Sa and Sb) to stop reverse power flow and change the duty cycle at the clamp region in order to prevent the current spike.

[0065] In accordance with an embodiment, the controller 106 is further configured to, if the switching frequency (fsw) is above the threshold frequency (fth), determine a PPT mode duty cycle (dl) and determine if the PPT mode duty cycle (dl) is equal to 1, and if so, perform variable frequency modulation (VFM) control else perform pulse power transfer (PPT) control. The controller 106 is further configured to determine if the switching frequency (i.e., fsw) generated by the VFM controller 206 is above the threshold frequency (i.e., fth), for example, 500kHz, or not. In a case, if the switching frequency (i.e., fsw) is above the threshold frequency (i.e., fth), then the controller 106 is further configured to determine the converter PPT mode duty cycle (dl) and check if the converter PPT mode duty cycle (dl) is equal to or greater than 1 or not. If the converter PPT mode duty cycle (dl) is equal to or greater than 1 , then the controller 106 is configured to perform the VFM control otherwise perform the PPT control. In another case, if the generated switching frequency (i.e., fsw) is less than the threshold frequency (i.e., fth), then the controller 106 is configured to perform the VFM control. Alternatively stated, the VFM control operation continues if the generated switching frequency (i.e., fsw) is less than the threshold frequency (i.e., fth), and this may be otherwise known as normal mode operation of the converter (i.e., the single stage resonant AC / DC converter). The ACM control in this case, maintains the DC-bus voltage within the specified limit of 300-430 Vdc by using the inner current loop of the PFC stage 204 that derives a PFC duty cycle (i.e., high frequency (HF) duty cycle). The PFC duty cycle (i.e., HF duty cycle) is saturated from 0.2-0.8 before it is fed into the zero-crossing compensation algorithm which maintain the converter (i.e., the single stage resonant AC / DC converter) gain along the zerocrossing area and allow the converter to operate in a discontinuous conduction mode (DCM) in the zero-crossing area. The PFC duty cycle after the zero-crossing compensation algorithm is compared with the switching frequency (i.e., fsw) or a carrier waveform, to generate a HF pulse width modulation (PWM) signal for controlling the HF switches (i.e., Si and S2), while the pulse PWM signal of the PPT mode is set high as it is connected to an AND gate 210, described in detail, for example, in FIG. 4.

[0066] In accordance with an embodiment, the controller 106 is further configured to, when performing pulse power transfer (PPT) control, disable the VFM control loop and set the switching frequency (fsw) to the highest allowable frequency. In the case, when the switching frequency (i.e., fsw) is above the threshold frequency (fth), the PPT controller 208 begins operation by disabling the VFM controller 206 and fixing the switching frequency (i.e., fsw) to the highest allowable frequency (e.g., 500kHz).

[0067] In accordance with an embodiment, the charger 100 further comprises the AND gate 210 configured to combine a high frequency PWM signal and a pulse PWM signal to supply a combined PWM signal for the high-frequency half-bridge switching device circuit 104 during the PPT control mode. During the PPT control mode, the PPT controller 208 is enabled and the pulse frequency (i.e., fpuise) is set to around 30kHz. The pulse frequency (i.e., fpuise) is compared with PPT mode duty cycle (i.e., dl) of the PPT controller 208 to generate the pulse PWM signal (e.g., 30kHz), which is then multiplied with the high frequency PWM signal by use of the AND gate 210. The resulting PWM signal (i.e., high frequency PWM signal multiplied with the pulse PWM signal) is used to control the high-frequency halfbridge switching device circuit 104 (i.e., Si and S2), described in detail, for example, in FIG. 3. In accordance with an embodiment, the controller 106 is further configured to adapt the switching frequency in steps as the output load 126 and output voltage of the charger 100 changes. The switching frequency (i. e. , fsw) changes to a lower value as the output load 126 (i.e., Ro), of FIG. 1, and the output voltage (i.e., Vo) increase, as shown in Table 1. Alternatively stated, the switching frequency (i.e., fsw) decreases / increases piece- wisely as the output load 126 (i.e., Ro) and output voltage (i.e., Vo) increases / decreases. The increase in the output load 126 (i.e., Ro) and the output voltage (i.e., Vo) means the switching frequency (i.e., fsw) is changed to a lower value thus, results in low switching losses and provides a suitable or enough gain for the converter (i.e., the single stage resonant AC / DC converter) when the output load 126 (i.e., Ro) and the output voltage (i.e., Vo) increases.

[0068] The Table 1 may be used as a look up table for fixing the switching frequency (i.e., fsw) after disabling the VFM controller 206 according to the converter load gain in PPT control mode.

[0069] In accordance with an embodiment, the controller 106 is further configured to adapt the DC- bus voltage linearly based on an output power and voltage. The DC-bus voltage (i.e., Vt>) is reduced linearly based on the output power that is, reducing the input AC current reference (i.e., iac ref) by decreasing the DC-bus voltage reference (i.e., Vbusref) which also allows the output voltage (i.e., Vo) to be reduced.

[0070] In accordance with an embodiment, the controller 106 is further configured to set the switches of the low-frequency half-bridge switching device circuit 102 based on a grid frequency. The controller 106 is configured to control the low-frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102 based on the grid frequency (e.g., 50Hz / 60Hz). In accordance with an embodiment, the controller 106 is further configured to set the switches of the low-frequency half-bridge switching device circuit 102 to turn-off during the zero-crossing area and set to turn-on complementarily in each half-cycle of the grid frequency after the zero-crossing area. During the zero-crossing area when the converter (i.e., the single stage resonant AC / DC converter) is allowed to operate in the DCM, the controller 106 is configured to turn-off the low-frequency half-bridge switching device circuit 102 (i.e., Sa and Sb). Furthermore, controller 106 is configured to turn-on the low- frequency half-bridge switching device circuit 102 (i.e., Sa and Sb) complementarily in each half-cycle of the grid frequency after the zero-crossing area during the continuous conduction mode (CCM) operation of the converter.

[0071] In accordance with an embodiment, the controller 106 is further configured to set gates of the low-frequency half-bridge switching device circuit 102 to low if the output charging current (io) is under the current threshold (ith). Moreover, the gates (i.e., gsa and gsb) of the low-frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102 are turned off at extreme light load of power<10W or when the output load current (i.e., io) is less than the threshold current (ith), for example, 2A. By doing so, the body diodes of the low-frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102, block reverse power flow in order to prevent production of an excessive power in the extreme light load condition.

[0072] In accordance with an embodiment, the controller 106 is further configured to set the HF duty cycle to a constant value. During the extreme light load condition, in addition to turnoff the gates (i.e., gsa and gsb) of the low-frequency switches (i.e., Sa and Sb) of the low- frequency half-bridge switching device circuit 102, the ACM controller is disabled and the high frequency duty cycle is changed to the constant value (e.g., 15%). The fixing of the high frequency duty cycle to the constant value (i.e., 15%) ensures that the exact energy required at the extreme light load condition is produced and at the same time, keeps the DC- bus voltage low. This control technique allows power regulation to as low as 1W and thus, enables the charger 100 (i.e., the single stage resonant AC / DC converter) suitable for charger application and ensures the required minimum load (i.e., 1W) for regulation.

[0073] Thus, the charger 100 (i.e., the single stage resonant AC / DC converter) achieves high efficiency due to use of the low frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102, zero voltage switching (ZVS) of the high frequency GaN switches (i.e., Si and S2) of the high-frequency half-bridge switching device circuit 104, and zero current switching (ZCS) of the output synchronous rectification MOSFET switches (i.e., SRi and SR2) of the output synchronous rectification switching device circuit 122, respectively at all operating points. The low frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102 are used to replace input diodes (e.g., Di and D2) of a conventional single stage AC / DC converter in order to further reduce the losses. Similarly, the output synchronous rectification MOSFET switches (i.e., SRi and SR2) of the output synchronous rectification switching device circuit 122 are used to replace output rectification diodes (e.g., Doi and D02) of the conventional single stage AC / DC converter. The ZVS and ZCS feature of the charger 100 make it possible to increase the switching frequency (i.e., fsw) while having smaller size of the reactive components. The wide gain at the input is achieved due to use of the ACM control technique in which different input and DC-bus voltage combinations (e.g., 120Vac / 340Vdc to 230Vac / 405Vdc) vary the duty cycle in a wide range. In this way, the duty cycle follows the shape of the input current and the DC-bus voltage regulation pushes the converter gain to the required level for easy regulation by the VFM control stage when the switching frequency (i.e., fsw) is less than the set threshold frequency (i.e., fth) of 500kHz. Moreover, the PPT control technique enhances the converter regulation further to provide wide output voltage regulation from 5V to 20V and power regulation from 1W to 75 W. The PPT control technique is used when the switching frequency (i.e., fsw) is greater than the threshold frequency (i.e., fth). When the switching frequency (i.e., fsw) is less than the threshold frequency (i.e., fth) during normal mode operation, the ACM control technique is applied to the converter using PWM driving signals. The PWM driving signals follow the sinusoidal waveform of the input current, therefore, the converter achieves a power factor of above 95% and a total harmonic distortion of value below 10%. Owing to these conditions, the converter behaves as a resistor from grid point of view and a single input current sensor is required. This further reduces the root mean square (RMS) current flow through the low frequency switches (i.e., Sa and Sb) as well as the high frequency switches (i.e., Si and S2), and the converter manifests a low cost as well. This way, the charger 100 (i.e., the single stage resonant AC / DC converter) manifests wide input and wide output voltage regulation, high efficiency due to ZVS, and high-power density due to integration of a bridge-less PFC totem pole (i.e., the PFC stage 204) with the switching resonant stage 110 (or the LLC power stage). The wide output voltage regulation and the power level >=1W is required because a phone or a laptop battery charges with constant current and increasing power at the beginning and constant voltage and decreasing power. Therefore, the charger 100 may be used as a smart phone or laptop charger and for general household electronic devices like smart TV, vacuum cleaners, and the like. The reason being the charger 100 manifests low cost, small size and high efficiency.

[0074] FIG. 3 is a graphical representation that illustrates pulse power transfer (PPT) control technique of a controller, in accordance with an embodiment of the present disclosure. FIG. 3 is described in conjunction with elements of the FIGs. 1 and 2. With reference to FIG. 3, there is shown a graphical representation 300 that includes a first waveform 302, a second waveform 304, a third waveform 306, a fourth waveform 308, and a fifth waveform 310.

[0075] The first waveform 302 represents a high frequency (HF) PWM signal applied to the gate terminals (i.e., gsi and gS2) of the high-frequency switches (i.e., Si and S2) of the high- frequency half-bridge switching device circuit 104 in the normal operation mode. The first waveform 302 may also be referred to as a HF gate signal. The second waveform 304 represents a low frequency (LF) pulse PWM signal (e.g., 30kHz). The third waveform 306 represents a resultant gate signal for the high-frequency switches (i.e., Si and S2) of the high- frequency half-bridge switching device circuit 104 in the PPT mode. The resultant gate signal is obtained by multiplying the first waveform 302 and the second waveform 304, that is multiplying the HF PWM signal and the LF pulse PWM signal. The fourth waveform 308 represents a boost inductor current (i.e., ii b) flowing through the boost inductor 112 (i.e., Lb). The fifth waveform 310 represents the output voltage (i.e., Vo) of the converter (i.e., the single stage resonant AC / DC converter).

[0076] During the PPT control mode of the converter, the PPT controller 208 is enabled and the pulse frequency (i.e., fpuise) is set to around 30kHz, as shown in the second waveform 304. The pulse frequency (i.e., fpuise) is compared with the PPT mode duty cycle (i.e., dl) of the PPT controller 208 to generate the pulse PWM signal (e.g., 30 kHz), which is then multiplied with the high frequency PWM signal represented by the first waveform 302 by use of the AND gate 210. The resulting PWM signal (i.e., high frequency PWM signal multiplied with the pulse PWM signal) represented by the third waveform 306 is used to control the high frequency switches (i.e., Si and S2) of the high-frequency half-bridge switching device circuit 104. The high frequency switches (i.e., Si and S2) are controlled by stopping the supply of the HF PWM signal represented by the first waveform 302 to the respective gate terminals (i. e. , gsi and gS2) when the pulse PWM signal represented by the second waveform 304 is low.

[0077] FIG. 4 illustrates a control technique used by a controller in detail, in accordance with an embodiment of the present disclosure. FIG. 4 is described in conjunction with elements of FIGs. 1, 2, and 3. With reference to FIG. 4, there is shown a control technique 400 used by the controller 106 (of FIG. 1) of the charger 100.

[0078] When the switching frequency (i.e. , fsw) is less than the threshold frequency (i.e. , fth), then the controller 106 is configured to perform the VFM control or the normal operation mode. In the VFM control, In the outer loop of the PFC stage 204 of the ACM controller (or the modulation controller 202), the measured DC-bus voltage (i.e., Vt>) is compared with the constant DC-bus reference value (i.e., Vbusref) to generate an error signal. The generated error signal is applied to a voltage proportional-integral (PI) controller of low bandwidth (8- 10Hz). The output of the voltage PI controller is divided by square of the RMS of the input AC voltage (i.e., Vac) and then, multiplied with the measured AC voltage (i.e., Vac) to generate the input reference current (iac ref). The inner loop of the ACM controller (i.e., the modulation controller 202) is the fast current loop of bandwidth> 1kHz which compares the input reference current (iac_ref) with the measured input AC current (i.e., iac) to generate an error signal fed into a PI controller to generate an output PFC duty cycle (i.e., HF duty cycle). The converter duty cycle (i.e., HF duty cycle) is saturated between 0.2 and 0.8 according to the converter gain. The PFC duty cycle (i.e., HF duty cycle) is compensated around the zerocrossing area using the zero-crossing compensation algorithm. The zero-crossing compensation algorithm maintains the converter gain near zero-crossing region. Moreover, the controller 106 is configured to turn-off the low-frequency (LF) switches (i.e., Saand Sb) of the low-frequency half-bridge switching device circuit 102 to prevent reverse power flow. The generated PFC duty cycle (i.e., HF duty cycle) combines the CCM and DCM mode duty cycle before and after the zero-crossing region, respectively. The output voltage loop of bandwidth >2kHz of the VFM controller 206 is configured to regulate the output voltage using VFM control and then compare with the unique converter duty cycle (or HF duty cycle) to produce the HF PWM signals, while the pulse PWM signal remains at a high signal level. The HF PWM signal and the pulse PWM signal are passed through the AND 210 gate. Since, the pulse PWM signal is at high level, only, the HF PWM signal controls the high frequency switches (i.e., Si and S2) of the high-frequency half-bridge switching device circuit 104. Moreover, the controller 106 is configured to turn off the low frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102 during the DCM operation and turn-on complementarily in each half-cycle of the grid frequency (i.e., 50Hz / 60Hz).

[0079] Moreover, the inductor current (i.e., iu>) has its magnitude below zero during normal mode of operation. Therefore, the boost inductor 112 (i.e., Lb) should be small enough to have a negative current value. The inductance value of the boost inductor 112 (i.e., Lb) is calculated using the equation (1).

[0080] Where Vac, Vb, Pac, and fsware the root mean square (RMS) value of the input voltage, DC- bus voltage, input power and the switching frequency, respectively.

[0081] The negative value of the inductor current (i.e., ii.b) may make the converter suitable for higher power level due to high efficiency owing to an ensured ZVS at all operating points. Another advantage is the possibility to operate the switching resonant stage 110 (or the resonant tank) below the resonant frequency by a large margin and still retain ZVS across the switches and not incur higher conduction losses in both the primary (i.e., the bridgeless rectifier stage 108) and secondary (i.e., the switching resonant stage 110) sides of the converter. The behavior of the switching resonant stage 110 (i.e., the resonant tank) operating below the resonant frequency without a hard switch make it possible for the converter to satisfy the wide input grid requirement without a much change in efficiency in contrast to the conventional single stage AC / DC converters. The wide input voltage regulation and high efficiency is achieved due to following reasons that is wide duty cycle variation, the operation of the switching resonant stage 110 (i.e., the resonant tank) below and above the resonant frequency region through different combinations of the input voltage (i.e., Vac) to the DC bus voltage control (120Vac / 340Vdc to 230Vac / 405Vdc).

[0082] When the switching frequency (i.e., fsw) is greater than the threshold frequency (i.e., fth), then the controller 106 is configured to perform the PPT control, as illustrated by a dotted box 402 of the FIG. 4. in form of a mathematical expression.

[0083] If fsw>fth enable Cpvidisable Cpv2

[0084] 11X Isw—iswmax end

[0085] If dl>=l enable Cpv2 disable C^i set dl = 1 end

[0086] In this mode of operation of the converter (i.e., the single stage resonant AC / DC converter), the ACM controller (i.e., the modulation controller 202) is still running, however, the VFM controller 206 is disabled and the switching frequency (i.e., fsw) is set to the highest allowable frequency (e.g., 500kHz). Moreover, the switching frequency (i.e., fsw) decreases / increases piece-wisely as the output load 126 (i.e., Ro) and the output voltage increases / decreases and the DC-bus voltage is reduced linearly based on the output power and voltage. The PPT voltage loop is enabled and the pulse frequency (i.e., fpuise) is set. The pulse frequency (i.e., fpuise) is compared with the PPT mode duty cycle (i.e., dl) to generate the pulse PWM signal (e.g., 30kHz). The high frequency PWM signal and the pulse PWM signal are passed through the AND gate 210 to provide a combined PWM signal for the high frequency switches (i.e., Si and S2) of the high-frequency half-bridge switching device circuit 104, as illustrated in the FIG. 3. Additionally, the low frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102 are turned off at the extremely light load condition (i.e., power < 10W) when the input current (i.e., io) is less than the threshold current (i.e., it), for example, 2A. The ACM controller is disabled and the HF duty cycle is set to the constant value of 15%.

[0087] Moreover, the PPT controller 208 (of FIG. 2) is able to regulate the DC output voltage as low as possible (e.g., 5Vdc) for low as well as high input AC voltages while maintaining high efficiency for both type of input AC voltages. Alternatively stated, the charger 100 (i.e., the single stage resonant AC / DC converter) with the PPT control technique attains the wide output voltage regulation (e.g., 5-20Vdc).

[0088] FIG. 5 is a flowchart that illustrates a control technique performed by a controller during normal and PPT mode of operation, in accordance with an embodiment of the present disclosure. FIG. 5 is described in conjunction with elements of FIGs. 1, 2, 3, and 4. With reference to FIG. 5, there is shown a flowchart 500 of the control technique used by the controller 106 (of FIG. 1) of the charger 100. The controller 106 is configured to execute the operations from 502 to 518.

[0089] At an operation 502, the flowchart 500 is initiated, indicated by “Start”.

[0090] At an operation 504, the controller 106 is configured to determine the output DC voltage reference (i. e. , Voref).

[0091] At an operation 506, the controller 106 is configured to determine the DC-bus voltage reference (i. e. , Vbusref).

[0092] At an operation 508, the controller 106 is configured to determine if the switching frequency (i.e., fsw) is above the threshold frequency (i.e., fth) or not. In a case, if the switching frequency (i.e., fsw) is above the threshold frequency (i.e., fth), the controller 106 is configured to execute an operation 510, else the controller 106 is configured to execute an operation 512.

[0093] At the operation 510, the controller 106 is configured to perform the PPT control mode.

[0094] At the operation 512, the controller 106 is configured to perform the VFM control mode.

[0095] At an operation 514, the controller 106 is configured to determine the converter PPT mode duty cycle (dl), if the converter PPT mode duty cycle (dl) is equal to or greater than 1, then the controller 106 is configured to execute the operation 512, else, the controller 106 is configured to execute an operation 516.

[0096] At the operation 516, the controller 106 is configured to determine if the input current (i.e., io) is under the threshold current (i.e., ith) or not. If the input current (i.e., io) is under the threshold current (i.e., ith) then, the controller 106 is configured to execute an operation 518 else, the controller 106 is configured to execute the operation 508 again. At the operation 518, the controller 106 is configured to turn-off the low frequency switches (i.e., Sa and Sb) of the low-frequency half-bridge switching device circuit 102 and set the HF duty cycle to the constant value of 15%.

[0097] FIG. 6A illustrates measured efficiency curves obtained at a range of an output voltage and at a low input AC voltage. FIG. 6A is described in conjunction with elements of FIGs. 1, 2, 3, 4, and 5. With reference to FIG. 6A, there is shown a graphical representation 600A that illustrates the measured efficiency curves of the charger 100 (i.e., the single stage resonant AC / DC converter) obtained at a range of an output voltage (e.g., 5-20 Vdc) and at a low input AC voltage (e.g., 120 Vac).

[0098] The graphical representation 600A includes an X-axis 602 and a Y-axis 604. The X-axis 602 represents a range of output power in Watts (W) and the Y-axis 604 represents a range of measured efficiency in percentage (%). Moreover, the graphical representation 600A includes a first curve 606, a second curve 608, a third curve 610, a fourth curve 612 and a fifth curve 614.

[0099] The first curve 606 illustrates a range of measured efficiency at an output voltage of 5 Vdc. Similarly, the second curve 608, the third curve 610, the fourth curve 612 and the fifth curve 614 illustrate a range of measured efficiency at an output voltage of 1 IVdc, 12Vdc, 15Vdc and 20 V de, respectively. Moreover, a shaded portion (e.g., left side portion of a dashed line) indicates the measured efficiency curves in the PPT control mode of the converter (i.e., the single stage resonant AC / DC converter) and a portion (e.g., right side portion of the dashed line) indicates the measured efficiency curves in the normal mode of operation of the converter (i.e., the single stage resonant AC / DC converter).

[0100] FIG. 6B illustrates measured efficiency curves obtained at a range of an output voltage and at a high input AC voltage, in accordance with an embodiment of the present disclosure. FIG. 6B is described in conjunction with elements of FIGs. 1, 2, 3, 4, and 5. With reference to FIG. 6B, there is shown a graphical representation 600B that illustrates the measured efficiency curves of the charger 100 (i.e., the single stage resonant AC / DC converter) obtained at a range of an output voltage (e. g. , 5 -20 V de) and at a high input AC voltage (e. g. , 230 Vac). The graphical representation 600B includes an X-axis 616 and a Y-axis 618. The X-axis 616 represents a range of output power in Watts (W) and the Y-axis 618 represents a range of measured efficiency in percentage (%). Moreover, the graphical representation 600B includes a first curve 620, a second curve 622, a third curve 624, a fourth curve 626 and a fifth curve 628.

[0101] The first curve 620 illustrates a range of measured efficiency at an output voltage of 5 Vdc. Similarly, the second curve 622, the third curve 624, the fourth curve 626 and the fifth curve 628 illustrate a range of measured efficiency at an output voltage of 1 IVdc, 12Vdc, 15Vdc and 20 V de, respectively. Moreover, a shaded portion (e.g., left side portion of a dashed line) indicates the measured efficiency curves in the PPT control mode of the converter (i.e., the single stage resonant AC / DC converter) and a portion (e.g., right side portion of the dashed line) indicates the measured efficiency curves in the normal mode of operation of the converter (i.e., the single stage resonant AC / DC converter).

[0102] Moreover, Table 2 shows the DC-bus voltage set point for low and high input AC voltage and the peak efficiency for different power levels with the respective output voltage from 5- 20V de. FIGs. 6A and 6B shows the measured efficiency curves for low input AC voltage (e.g., 120 Vac) and high input AC voltage (e.g., 230 Vac), at a full load of 150W, 20V de, respectively. A peak efficiency of 95.44% and 95.18% is achieved for low and high input AC voltages, respectively showing the similarity in the efficiencies in contrast to the conventional single stage AC / DC converters.

[0103] FIG. 7 illustrates the performance of a converter in terms of power factor (PF) against load, in accordance with an embodiment of the present disclosure. FIG. 7 is described in conjunction with elements of FIGs. 1, 2, 3, 4, and 5. With reference to FIG. 7, there is shown a graphical representation 700 that illustrates the performance of the converter (i.e., the single stage resonant AC / DC converter) in terms of PF against load.

[0104] The graphical representation 700 includes an X-axis 702 and a Y-axis 704. The X-axis 702 represents an output power in Watts (W) and the Y-axis 704 represents PF. Moreover, the graphical representation 700 includes a first curve 706, a second curve 708, and a shaded portion 710.

[0105] The first curve 706 represents the behavior of the power factor at low input AC voltage (e.g., 120 Vac_rms). Moreover, the first curve 706 represents that the PF is greater than 96% at a full power load (e.g., 150W). At the full power load, the converter (i.e., the single stage resonant AC / DC converter) achieves a low total harmonic distortion, THD, (e.g., <10%), high PF (e.g., >96%), high power density and high peak efficiency (e.g., >95%). The second curve 708 represents the behavior of the power factor at high input AC voltage (e.g., 230 Vac_rms). The PF is a bit decreasing as the power goes lower at the high input AC voltage. However, below 75 W power, THD requirement not required in Class D requirement as illustrated by the shaded portion 710. At power >=75 W. the converter exits the PPT mode and still fulfils IEC Class D requirement.

[0106] FIG. 8 illustrates variation of measured total harmonic distortion values of a converter with an increase in harmonic number at high input AC voltage, in accordance with an embodiment of the present disclosure. FIG. 8 is described in conjunction with elements of FIGs. 1, 2, 3, 4, and 5. With reference to FIG. 8, there is shown a bar graphical representation 800 that illustrates the variation of measured total harmonic distortion values of the converter (i.e., the single stage resonant AC / DC converter) with an increase in harmonic number at high input AC voltage (e.g., 230 Vac_rms), with frequency of 50Hz and a power load of 150W.

[0107] The bar graphical representation 800 includes an X-axis 802 and a Y-axis 804. The X-axis 802 represents harmonic number and the Y-axis 804 represents total harmonic distortion (THD) values. Moreover, the bar graphical representation 800 represents the measured THD values for each harmonics up to 39thharmonics. This depicts that the converter (i.e., the single stage resonant AC / DC converter) achieves the required THD values that meets the Class-D requirement by a large margin at the high input AC voltage. The converter also achieves the required THD values at the low input AC voltage that meets the Class-D requirement by a larger margin than the high input AC voltage.

[0108] FIG. 9 is a circuit diagram of a charger, in accordance with another embodiment of the present disclosure. FIG. 9 is described in conjunction with elements of FIG. 1. With reference to FIG. 9, there is shown a circuit diagram of a charger 900. The charger 900 is represented by a dashed box, which is used for illustration purpose only and does not form a part of circuitry.

[0109] The charger 900 is similar to the charger 100 (of FIG. 1) except that a pair of diodes 902 (may also be represented as Di and D2) and another pair of diodes 904 (may also be represented as Doi and D02) are used in the charger 900. The pair of diodes 902 (i.e., Di and D2) replaces the low-frequency half-bridge switching device circuit 102 (i.e., Sa and Sb) and the other pair of diodes 904 (i.e., Doi and D02) replaces the output synchronous rectification switching device circuit 122 (i.e., SRi and SR2) of the charger 100.

[0110] The control technique that is the VFM control and the PPT control is also applicable to the charger 900 with a difference. The difference is the inductor current magnitude cannot go below zero due to the pair of diodes 902 (i.e., Di and D2) blocking the reverse power flow.

[0111] Similar to the charger 100, the charger 900 may be used as a smart phone or laptop charger and for general household electronic devices like smart TV, vacuum cleaners, and the like.

[0112] Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the present disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

CLAIMS1. A charger (100, 900) configured for wide input / output voltage regulation, the charger (100, 900) comprising a low-frequency half-bridge switching device circuit (102), a high- frequency half-bridge switching device circuit (104) and a controller (106) configured to: receive an output DC voltage reference; determine a DC-bus voltage reference; determine a switching frequency based on the DC-bus voltage reference; determine if the switching frequency is above a threshold frequency and if so, perform pulse power transfer, PPT, control, and if not perform variable frequency modulation, VFM, control; receive an output charging current; determine if the output charging current is under a current threshold, and if so, disable the low-frequency half-bridge switching device circuit (102).

2. The charger (100, 900) according to claim 1, wherein the controller (106) is further configured to, if the switching frequency is above the threshold frequency: determine a PPT mode duty cycle; determine if the PPT mode duty cycle is equal to 1, and if so, perform variable frequency modulation, VFM, control else, perform pulse power transfer, PPT, control.

3. The charger (100, 900) according to claim 1 or 2, wherein the controller (106) is further configured to set gates of the low-frequency half-bridge switching device circuit (102) to low if the output charging current is under the current threshold.

4. The charger (100, 900) according to claim 1, 2 or 3, wherein the controller (106) is further configured to set the high frequency duty cycle to a constant value.

5. The charger (100, 900) according to any preceding claim, wherein the controller (106) is further configured to set the switches of the low-frequency half-bridge switching device circuit (102) based on a grid frequency.

6. The charger (100, 900) according to claim 5, wherein the controller (106) is further configured to set the switches of the low-frequency half-bridge switching device circuit (102) to turn-off during the zero-crossing area and set to tum-on complementarily in each half-cycle of the grid frequency after the zero-crossing area.

7. The charger (100, 900) according to any preceding claim, wherein the controller (106) is further configured to, when performing the pulse power transfer, PPT, control, disable the VFM control loop and set the switching frequency to the highest allowable frequency.

8. The charger (100, 900) according to any preceding claim, wherein the controller (106) is further configured to adapt the switching frequency in steps as the output load and output voltage of the charger (100, 900) changes.

9. The charger (100, 900) according to claim 8, wherein the controller (106) is further configured to adapt a DC-bus voltage linearly based on the output power and voltage.

10. The charger (100, 900) according to any preceding claim, further comprising an AND gate (210) configured to combine a high frequency PWM signal and a pulse PWM signal to supply a combined PWM signal for the high frequency half-bridge switching device circuit (104) during the PPT mode.

11. The charger (100, 900) according to any preceding claim, further comprising a bridgeless rectifier stage (108) comprising a boost inductor (112), and a DC-bus capacitor (114) coupled with a switching resonant stage (110).

12. The charger (100, 900) according to claim 11, wherein the switching resonant stage (110) comprises a resonant inductor (116), a resonant capacitor (118) and a high frequency transformer (120) connected to an output synchronous rectification switching device circuit (122).

13. The charger (100, 900) according to any preceding claim, wherein the controller (106) further comprises a modulation controller (202) for an integrated power factor correction, PFC, +LLC stage and the output stage regulation uses variable frequency modulation controller (206) in normal operation and pulse power transfer controller (208) in PPT operation mode to simultaneously achieve wide AC input voltage and wide DC output voltage regulation, respectively.

14. The charger (100, 900) according to claim 13, wherein the modulation controller (202) comprises a PFC stage (204) with an outer loop for DC-bus voltage control, an inner current loop and zero-crossing compensation algorithm for generating the converter duty cycle.

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