Semiconductor arrangement comprising a semiconductor element, a substrate and at least one wiring element
Patent Information
- Application Number
- EP2023731137
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-07-29
- Filing Date
- 2023-05-31
- Publication Date
- 2025-03-05
AI Technical Summary
The reliability of semiconductor arrangements is compromised due to wiring elements detaching from load contacts during operation, leading to failures in semiconductor devices used in power converters.
A semiconductor arrangement with a substrate having electrically insulated line sections, where the semiconductor element is connected to a first line section and the contact surface is connected to the substrate via a wiring element with a first and second connection section, creating an asymmetrical current flow to counteract shear forces, enhancing the robustness of connections through 'overbonding'.
The solution significantly reduces the probability of wiring element detachment, thereby improving the reliability and extending the service life of semiconductor arrangements by providing a counterforce to shear forces acting on connections, especially under load conditions.
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Figure 1.1
Abstract
Description
[0001] Description
[0002] Semiconductor device with a semiconductor element, a substrate and at least one wiring element
[0003] The invention relates to a semiconductor device comprising a semiconductor element, a substrate and at least one wiring element.
[0004] Furthermore, the invention relates to a power converter with at least one such semiconductor arrangement.
[0005] Furthermore, the invention relates to a method for producing such a semiconductor arrangement, wherein the semiconductor element is connected, in particular materially, to the substrate, wherein in a further step the contact surface of the semiconductor element is connected to the substrate via the at least one wiring element.
[0006] Furthermore, the invention relates to a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate the behavior of such a semiconductor device.
[0007] Such a semiconductor module is generally used in a power converter. A power converter can be, for example, a rectifier, an inverter, a converter or a DC-DC converter. The semiconductor elements used in the semiconductor module include transistors, triacs, thyristors or diodes. Transistors are designed, for example, as insulated-gate bipolar transistors (IGBTs), field-effect transistors or bipolar transistors. The semiconductor elements of a semiconductor arrangement are usually contacted via wiring elements on a substrate. Such wiring elements can include, among other things, bond wires and / or bond strips. In particular, load contacts of a semiconductor element, including an emitter contact of an IGBT, are usually contacted with a plurality of wiring elements on the substrate.
[0008] The published patent application DE 11 2019 000 660 T5 describes a semiconductor device comprising: a substrate having a main surface; a plurality of conductor patterns provided on the main surface; a plurality of switching elements arranged on the plurality of conductor patterns to connect collector electrodes; and a single or a plurality of wiring elements directly connecting emitter electrodes of the switching elements arranged on different conductor patterns and connected in parallel between the plurality of switching elements.
[0009] During operation of the semiconductor elements, wiring elements can detach from the load contact, leading to failure of the semiconductor device. More robust wiring leads to improved reliability of the semiconductor device.
[0010] Against this background, the object of the present invention is to provide a semiconductor device which has improved reliability.
[0011] The object is achieved according to the invention by a semiconductor arrangement with a semiconductor element, a substrate and at least one wiring element, wherein the substrate has a substrate metallization with line sections arranged electrically insulated from one another, wherein the semiconductor element is connected, in particular materially, to a first line section of the substrate metallization, wherein the semiconductor element has a contact surface on a side facing away from the substrate, wherein the contact surface of the semiconductor element is connected to the substrate via at least one wiring element, wherein the at least one wiring element has a first connecting section which connects the contact surface to a second line section of the substrate metallization, and a second connecting section which connects the contact surface to a third line section of the substrate metallization,wherein the second and third conductive sections of the substrate metallization are configured such that the first connecting section and the second connecting section have an asymmetrical current flow during operation of the semiconductor device.,
[0012] Furthermore, the object is achieved according to the invention by a power converter with at least one such semiconductor arrangement.
[0013] Moreover, the object is achieved according to the invention by a method for producing such a semiconductor arrangement, wherein the semiconductor element is connected, in particular materially, to the substrate, wherein in a further step the contact surface of the semiconductor element is connected to the substrate via the at least one wiring element.
[0014] Furthermore, the object is achieved according to the invention by a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate a behavior, in particular thermal, mechanical and / or electrical, of such a semiconductor device.
[0015] The advantages and preferred embodiments listed below with regard to the semiconductor device can be transferred analogously to the power converter, the method and the computer program product.
[0016] The invention is based on the idea of improving the reliability of a semiconductor device by significantly reducing the probability of a failure during operation of the semiconductor device due to wiring elements being detached from a semiconductor element. Such a semiconductor device has a substrate with a substrate metallization. The substrate metallization is structured, i.e. it has line sections arranged so as to be electrically insulated from one another. The semiconductor element is connected, in particular in a material-to-material connection, to a first line section of the substrate metallization. The material-to-material connection is produced, for example, by soldering, sintering or adhesion. Furthermore, the semiconductor element has a contact surface on a side facing away from the substrate, which contact surface is connected to the substrate via at least one wiring element.For example, the semiconductor element is designed as an IGBT, which is soldered or sintered on the collector side onto the first line section of the substrate metallization, while on the emitter side it is connected to the substrate via the at least one wiring element. The at least one wiring element is designed, for example, as a bonding wire or bonding strip, it being possible to establish the connection between the substrate and the contact surface of the semiconductor element by means of ultrasonic bonding connections. The at least one wiring element comprises a first connecting section which connects the contact surface to a second line section of the substrate metallization. If current, in particular load current, flows through the at least one wiring element, a shearing force acts on connections, in particular ultrasonic bonding connections, between the contact surface of the semiconductor element and the wiring element.
[0017] In order to counteract such a shear force, the at least one wiring element comprises a second connecting section which connects the contact surface to a third conducting section of the substrate metallization, wherein the first conducting section, the second conducting section and the third conducting section are arranged on the substrate in an electrically insulated manner from one another. The second and the third conducting sections of the substrate metallization are configured such that the first connecting section and the second connecting section of the at least one wiring element have an asymmetrical current flow during operation of the semiconductor arrangement.This is the case, among other things, when the second or the third line section, apart from the connection to the at least one wiring element, is arranged in a floating manner, so that a current from the semiconductor arrangement flows at least predominantly, in particular substantially exclusively, via the first or second connecting section of the at least one wiring element. Due to the additional connection of the at least one wiring element via the second connecting section to the third line section, which is also called "overbonding", a counterforce counteracts the shear force, so that the connections of the at least one wiring element to the contact surface are more robust, in particular under load, which has a positive effect on the reliability of the semiconductor arrangement and extends its service life.
[0018] A computer program product which comprises instructions which, when the program is executed by a computer, cause the computer to simulate a behavior, in particular thermal, mechanical and / or electrical, of the described semiconductor arrangement can comprise a “digital twin” or be designed as such. Such a digital twin is described, for example, in the published patent application US 2017 / 0286572 A1. The disclosure content of US 2017 / 0286572 A1 is incorporated by reference into the present application. The “digital twin” is, for example, a digital representation of the components relevant for the operation of the semiconductor arrangement.
[0019] A further embodiment provides that the second and third line sections of the substrate metallization are arranged on opposite sides of the semiconductor element. Due to the opposite arrangement, the counterforce can counteract the shearing force in parallel, so that optimal robustness can be achieved. A further embodiment provides that a first current flowing through the first connecting section of the at least one wiring element, in particular load current, is a hundred times, in particular a thousand times, greater than a second current flowing through the second connecting section of the at least one wiring element. This is the case, among other things, when the third line section, apart from the connection to the at least one wiring element, is arranged in a floating manner, while the second line section is connected, for example, to an AC or DC connection.In this way, an optimal robustness of the connections of the at least one wiring element with the contact surface is achieved, in particular under load.
[0020] A further embodiment provides that the third line section connected to the second connecting section of the at least one wiring element is arranged in an open-circuit manner on the substrate. An open-circuit arrangement of the third line section means that, apart from the at least one wiring element, it is not electrically connected to any further component. In this way, optimal robustness of the connections of the at least one wiring element to the contact surface is achieved, particularly under load.
[0021] A further embodiment provides that the first connecting section and the second connecting section of the at least one wiring element are designed to be substantially axially symmetrical with respect to an axis of symmetry. A substantially axially symmetrical arrangement optimally balances any shear forces that occur by counteracting the shear forces.
[0022] A further embodiment provides that the at least one wiring element has a third connecting section which connects the third line section of the substrate metallization to a contact surface of a further semiconductor element. For example, the semiconductor element is designed as an IGBT, while the further semiconductor element is designed as a diode connected anti-parallel to the semiconductor element. Alternatively, the further semiconductor element can be designed, among other things, as a further IGBT connected in parallel to the semiconductor element designed as an IGBT. Such an arrangement achieves improved robustness of the connections of the at least one wiring element to the contact surfaces of the semiconductor elements, which has a positive effect on the reliability of the semiconductor arrangement and extends its service life.
[0023] A further embodiment provides that the semiconductor arrangement comprises a plurality of wiring elements for connecting the contact surface to the second and third line sections. Such a configuration is particularly advantageous for higher load currents. Furthermore, parasitic inductances are reduced by connecting wiring elements in parallel, which leads to lower switching losses.
[0024] A further embodiment provides that the semiconductor element is wider on a side facing the third line section than the third line section, wherein a main current path of the first line section is designed to run past the third line section on both sides. For example, a load current flows to the semiconductor element via the first line section. In this case, a main current path of the load current runs past the third line section on both sides. A narrower design of the third line section achieves improved current conduction, which leads, for example, to lower losses.
[0025] A further embodiment provides that the main current path of the first line section is configured to run essentially symmetrically past the third line section. Such a configuration of the arrangement achieves optimized current flow.
[0026] A further embodiment provides that more wiring elements are connected to the second line section than to the third line section. For example, at least one wiring element, in particular at least one outer wiring element, does not have a second connecting section for connection to the third line section, thereby enabling a narrower design of the third line section, which leads to improved current conduction.
[0027] A further embodiment provides that the third line section of the substrate metallization comprises at least two wiring islands arranged electrically insulated from one another, which are arranged open-circuit on the substrate, wherein at least one wiring element is connected to one of the wiring islands of the third line section via the respective second connecting section. Such a split arrangement enables improved current conduction, which leads, for example, to lower losses.
[0028] A further embodiment provides for two wiring islands to be arranged on the substrate in such a way that a main current path is formed between the wiring islands. For example, a load current flows between the wiring islands to the semiconductor element. Such direct current routing reduces losses.
[0029] A further embodiment provides that the semiconductor element is designed as a switchable semiconductor element, in particular as a transistor, and forms a half-bridge with at least one further switchable semiconductor element. For example, the semiconductor element is configured as a low-side switch of the half-bridge. In particular, the switchable semiconductor element and the further switchable semiconductor element are each designed as at least one IGBT. Due to the circuit topology of the half-bridge, it may happen, for example, that the wiring of the low-side switch has a lower reliability, which negatively influences the service life of the half-bridge. In this example, the reliability of the low-side switch is improved or adapted by overbonding the wiring elements via the second connection section to the third line section, such that a longer service life of the half-bridge is achieved.
[0030] In the following, the invention is described and explained in more detail with reference to the exemplary embodiments shown in the figures.
[0031] It shows :
[0032] FIG 1 is a schematic representation of a first embodiment of a semiconductor device in a plan view,
[0033] FIG 2 shows a schematic representation of the first embodiment of the semiconductor device in a cross-sectional view,
[0034] FIG 3 is a schematic representation of a second embodiment of a semiconductor device in a plan view,
[0035] FIG 4 is a schematic representation of a third embodiment of a semiconductor device in a plan view,
[0036] FIG 5 is a schematic representation of a fourth embodiment of a semiconductor device in a plan view, FIG 6 is a schematic representation of a fifth embodiment of a semiconductor device in a plan view,
[0037] FIG 7 is a schematic diagram of a power converter.
[0038] The exemplary embodiments explained below are preferred embodiments of the invention. In the exemplary embodiments, the described components of the embodiments each represent individual features of the invention that are to be considered independently of one another. These also further develop the invention independently of one another and are thus to be regarded as components of the invention, either individually or in a combination other than that shown. Furthermore, the described embodiments can also be supplemented by further features of the invention already described.
[0039] The same reference symbols have the same meaning in the different figures.
[0040] FIG 1 shows a schematic representation of a first embodiment of a semiconductor arrangement 2 in a plan view, which comprises a semiconductor element 4 that is contact-connected to a substrate 6. By way of example, the semiconductor element 4 is designed as an insulated-gate bipolar transistor (IGBT). Further examples of such semiconductor elements 4 are triacs, thyristors, diodes or other transistor types such as field-effect transistors or bipolar transistors. The IGBT comprises a control terminal, which is designed as a gate terminal G, and load terminals, which are designed as a collector terminal C and an emitter terminal E, the collector terminal C being connected in a materially bonded manner to the substrate 6 on a side of the semiconductor element 4 facing the substrate 6.
[0041] The emitter terminal E has a contact area 8, wherein the gate terminal G has a control contact area 10 which is arranged electrically insulated from the contact area 8 of the emitter terminal E. The contact area 8 and the control contact area 10 have at least one metallic layer which contains, for example, aluminum, copper and / or gold. The IGBT is connected, for example via a soldered or sintered connection, to a first line section 12 of a substrate metallization 14 of the substrate 6. Furthermore, the substrate 6 has a second line section 16 which is arranged electrically insulated from the first line section 12 and a third line section 18 which is formed like an island in the first line section 12 and is electrically insulated therefrom, wherein the second and third line sections 16, 18 of the substrate metallization 14 are arranged on opposite sides of the semiconductor element 4.In addition, the substrate 6 comprises a dielectric material layer 20 which contains, for example, a ceramic material, in particular aluminum nitride or aluminum oxide, and has a thickness of 25 pm to 400 pm, in particular 50 pm to 250 pm.
[0042] Furthermore, the semiconductor arrangement 2 has a plurality of wiring elements 22 for connecting the contact surface 8 of the emitter terminal E to the second and third line sections 16, 18. The wiring elements 22 are designed as essentially parallel bonding wires or bonding strips which contain, for example, aluminum, copper and / or gold. In addition, the wiring elements 22 each have a first connecting section 24 which connects the contact surface 8 of the emitter terminal E to the second line section 16 of the substrate metallization 14, and a second connecting section 26 which connects the contact surface 8 of the emitter terminal E to the third line section 18 of the substrate metallization 14. The third line section 18 connected to the second connecting section 26 of the respective wiring element 22 is arranged in an open-circuit manner on the substrate 6.The open-circuit arrangement has the consequence that, during operation of the semiconductor arrangement 2, a first current II, in particular a load current, flows from the emitter E via the first connecting sections 24 of the respective wiring elements 22, while a, in particular negligibly small, second current I2 flows via the second connecting sections 26. In particular, the first current II is a hundred times, in particular a thousand times, greater than the second current I2. Thus, the first connecting section 24 and the second connecting section 26 have an asymmetrical current flow during operation of the semiconductor arrangement 2.
[0043] FIG 2 shows a schematic representation of the first embodiment of the semiconductor arrangement 2 in a cross-sectional representation. The wiring elements 22 are designed as bonding wires and form a plurality of stitch contacts 32 on the contact surface 8 between the first connecting section 24 and the second connecting section 26, the connection being produced by means of ultrasonic bonding. The connection of the wiring elements 22 to the contact surface 8 of the semiconductor element 4 is produced by looping through the wiring elements 22, in particular by means of multi-stitch wedge-to-wedge wire bonding. The multiple bonding is also called "stitching". Such stitch contacts 32 are usually also referred to as "stitch bonds" and can, for example, be designed as "wedge bonds".The first connecting section 24 and the second connecting section 26 of the respective wiring elements 22 are designed to be substantially axially symmetrical with respect to an axis of symmetry 30.
[0044] If a first current II, in particular load current, flows via the wiring elements 22, a shearing force Fl acts on the connections 32, in particular ultrasonic bonded connections. As a result of the overbonding of the wiring elements 22 via the second connecting section 26 to the third line section 18, a counterforce F2 can counteract the shearing force Fl, so that the connections 32 are more robust, in particular under load. The result is that the overbonding results in a longer service life of the semiconductor arrangement 2.
[0045] FIG. 3 shows a schematic representation of a second embodiment of a semiconductor device 2 in a plan view, wherein a half-bridge is formed by the semiconductor element 4 embodied as an IGBT and a further semiconductor element 34, which is also embodied as an IGBT. The semiconductor elements 4, 34 each have an antiparallel-connected diode 36.
[0046] The semiconductor element 4 is configured as a low-side switch of the half-bridge. The first line section 12 of the substrate 6 is connected to an AG terminal AG via a shunt resistor 38, while the second line section 16 is connected to a negative DC terminal DCN of the half-bridge. The further semiconductor element 34 is connected, in particular in a materially bonded manner, to a fourth line section 40 of the substrate metallization 14, the fourth line section 40 being connected to a positive DC terminal DGB of the half-bridge. A load current path IL of the first line section 12 is formed running past the third line section 18 on both sides. Furthermore, the semiconductor arrangement 2 comprises a temperature sensor, which is designed, for example, as an NTC thermistor (Negative Temperature Coefficient Thermistor). The further embodiment of the semiconductor arrangement 2 in FIG 3 corresponds to that in FIG 1 or FIG 2.
[0047] FIG 4 shows a schematic representation of a third embodiment of a semiconductor arrangement 2 in a plan view. The third line section 18 of the substrate metallization 14 has two wiring islands 42, 44 which are arranged electrically insulated from one another and which are each arranged open-circuited on the substrate 6. The second connecting sections 26 of the wiring elements 22 are each connected to one of the wiring islands 42, 44 of the third line section 18. By way of example, three wiring elements 22 are connected to a first wiring island 42 and two wiring elements 22 are connected to a second wiring island 44. The exemplary rectangular wiring islands 42, 44 are arranged spaced apart on the substrate 6 in such a way that a main current path IH is formed between the semiconductor elements 4, 34. The further design of the semiconductor device 2 in FIG 4 corresponds to that in FIG 3 .
[0048] 5 shows a schematic representation of a fourth embodiment of a semiconductor arrangement 2 in a plan view, wherein only three of the total of five wiring elements 22, by way of example, for connecting the contact area 8 of the semiconductor element 4 to the substrate 6 are connected to the third line section 18 via a second connecting section 26. The semiconductor element 4 has a first width b1 on a side facing the third line section 18, while the third line section 18 has a second width b2 which is smaller than the first width b1. A main current path IH of the first line section 12 is essentially symmetrical and runs past the third line section 18 on both sides. The further embodiment of the semiconductor arrangement 2 in FIG 5 corresponds to that in FIG 3.
[0049] FIG 6 shows a schematic representation of a fifth embodiment of a semiconductor arrangement 2 in a plan view, wherein a further semiconductor element 34 is connected via the wiring elements 22, which are provided for connecting the contact area 8 of the semiconductor element 4, which is designed as an IGBT, for example, to the second and third line sections 16, 18. The wiring elements 22 have a third connecting section 46, which connects the third line section 18 of the substrate metallization 14 to the further semiconductor element 34. The further semiconductor element 34 is designed, for example, as a diode connected anti-parallel to the semiconductor element 4. Additionally or alternatively, the further semiconductor element 34 can comprise at least one further IGBT connected in parallel to the semiconductor element 4.The third line section 18 is designed to be open-circuited, i.e., the third line section 18 is not electrically connected to any other component besides the wiring elements 22. The further configuration of the semiconductor arrangement 2 in FIG. 6 corresponds to that in FIG. 1 or FIG. 2.
[0050] FIG 7 shows a schematic representation of a power converter 48, which comprises, for example, a semiconductor arrangement 2.
Claims
Patent claims 1. Semiconductor arrangement (2) with a semiconductor element (4), a substrate (6) and at least one wiring element (22), wherein the substrate (6) has a substrate metallization (14) with line sections (12, 16, 18) arranged electrically insulated from one another, wherein the semiconductor element (4) is connected, in particular materially, to a first line section (12) of the substrate metallization (14), wherein the semiconductor element (4) has a contact surface (8) on a side facing away from the substrate (6), wherein the contact surface (8) of the semiconductor element (4) is connected to the substrate (6) via at least one wiring element (22), wherein the at least one wiring element (22) has a first connecting section (24), which connects the contact surface (8) to a second line section (16) of the substrate metallization (14), and a second connecting section (26),which connects the contact surface (8) to a third line section (18) of the substrate metallization (14), wherein the second and the third line section (16, 18) of the substrate metallization (14) are configured such that the first connecting section (24) and the second connecting section (26) have an asymmetrical current flow during operation of the semiconductor device (2).
2. Semiconductor arrangement (2) according to claim 1, wherein the second and third line sections (16, 18) of the substrate metallization (14) are arranged on opposite sides of the semiconductor element (4).
3. Semiconductor arrangement (2) according to one of claims 1 or 2, wherein a first current (II), in particular load current, flowing through the first connecting section (24) of the at least one wiring element (22) is one hundred times, in particular one thousand times, greater than a second current (II) flowing through the second connecting section (26) of the at least one wiring element (22).
4. Semiconductor arrangement (2) according to one of the preceding claims, wherein the third line section (18) connected to the second connecting section (26) of the at least one wiring element (22) is arranged open-circuit on the substrate (6).
5. Semiconductor arrangement (2) according to one of the preceding claims, wherein the first connecting section (24) and the second connecting section (26) of the at least one wiring element (22) are designed to be substantially axially symmetrical with respect to an axis of symmetry (30).
6. Semiconductor arrangement (2) according to one of the preceding claims, wherein the at least one wiring element (22) has a third connecting section (46) which connects the third line section (18) of the substrate metallization (14) to a contact surface (8) of a further semiconductor element (34).
7. Semiconductor device (2) according to one of the preceding claims, wherein the semiconductor arrangement (2) comprises a plurality of wiring elements (22) for connecting the contact surface (8) to the second and the third line section (16, 18).
8. Semiconductor arrangement (2) according to claim 7, wherein the semiconductor element (4) is wider on a side facing the third line section (18) than the third line section (18), wherein a main current path (IH) of the first line section (12) is designed to run past the third line section (18) on both sides.
9. Semiconductor arrangement (2) according to claim 8, wherein the main current path (IH) of the first line section (12) is designed to run substantially symmetrically past the third line section (18).
10. Semiconductor arrangement (2) according to one of claims 7 to 9, wherein more wiring elements (22) are connected to the second line section (16) than to the third line section (18).
11. Semiconductor arrangement (2) according to claim 7, wherein the third line section (18) of the substrate metallization (14) comprises at least two wiring islands (42, 44) which are arranged electrically insulated from one another and are arranged open-circuit on the substrate (6), wherein in each case at least one wiring element (22) is connected to one of the wiring islands (42, 44) of the third line section (18) via the respective second connecting section (26).
12. Semiconductor device (2) according to claim 11, wherein two wiring islands (42, 44) are arranged on the substrate (6) in such a way that a main current path (IH) is formed running between the wiring islands (42, 44).
13. Semiconductor arrangement (2) according to one of the preceding claims, wherein the semiconductor element (4) is designed as a switchable semiconductor element, in particular as a transistor, and forms a half-bridge with at least one further switchable semiconductor element (34).
14. Power converter (48) with at least one semiconductor arrangement (2) according to one of the preceding claims.
15. A method for producing a semiconductor device (2) according to one of claims 1 to 13, wherein the semiconductor element (4) is connected, in particular materially, to the substrate (6), wherein in a further step the contact surface (8) of the semiconductor element (4) is connected to the substrate (6) via the at least one wiring element (22).
16. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate a behavior, in particular thermal, mechanical and / or electrical, of a semiconductor device (2) according to one of claims 1 to 13.