Voltage regulator

Abstract

The present description relates to a device (REG2) comprising a first MOS transistor (P1) connected between first and second nodes (102, 350), a selectively activatable current source (314) connected between the second node (350) and a third node (108), a circuit (302) controlling the first transistor (P1) to regulate a voltage from the second node to a first setpoint value (V1), a second MOS transistor (P2) connected between the first node (102) and a fourth node (104), and having its gate connected to that of the first transistor (P1), a third MOS transistor (N1) connected between the third and fourth nodes (108, 104), a switch (IT) connected between the second and fourth nodes (350, 104), and another circuit (310) controlling the third transistor (N1) to regulate a voltage (VDD) from the fourth node (104) to a second setpoint value (V2).

Description

technical field

[0001] This description applies generally to electronic circuits, for example, integrated circuits. More specifically, this description applies to circuits configured to receive a first supply voltage and to provide a second supply voltage from the first supply voltage; these circuits are commonly called, for example, voltage regulators. Previous technique

[0002] Many well-known electronic systems are powered by a first direct current (DC) voltage, for example, received at a power supply terminal of the system. To power all or part of their internal circuits with a second DC supply voltage of a lower value than the first, these systems include a voltage regulator configured to generate the second DC voltage from the first DC voltage.

[0003] During phases of use of these known systems, for example during development phases and / or during testing phases at the end of manufacturing, it may be desirable to know the current drawn by these systems from the voltage source providing the first voltage, so as, for example, to evaluate the consumption of the internal circuits of the system which are powered by the second voltage.

[0004] In other phases of use of these known systems, for example, during phases where the system is used by an end user and / or during phases where the system is deployed in its application environment, it may be desirable for the current drawn by these systems from the voltage source providing the first voltage to be constant, so as, for example, to mask the power consumption of the system's internal circuits powered by the second voltage. For example, this prevents attackers from accessing confidential information based on knowledge of the power consumption of the circuits powered by the second voltage. US patent 9,787,171B2 describes a power supply circuit according to the prior art. Summary of the invention

[0005] There is a need to overcome all or part of the drawbacks of known voltage regulators.

[0006] For example, there is a need to overcome some or all of the disadvantages of known voltage regulators configured to receive a first DC supply voltage and to provide a second DC supply voltage from the first DC supply voltage, the second voltage having a lower value than the first.

[0007] For example, there is a need for a voltage regulator that can operate alternately in a first mode where the current drawn from the voltage source supplying the first voltage varies with the current drawn by the powered circuits and in a second mode where the current drawn from this voltage source is constant.

[0008] For example, there is a need to overcome all or part of the drawbacks of known regulators that can operate alternately according to the first and second modes described above.

[0009] One embodiment overcomes all or part of the disadvantages of known voltage regulators.

[0010] One embodiment provides for a device comprising: a first MOS transistor connected between a first node configured to receive a first supply voltage, and a second node; a selectively switchable current source connected between the second node and a third node configured to receive a reference potential; a first circuit configured to control the first transistor so as to regulate a voltage from the second node to a first setpoint value determined at least in part by a first setpoint voltage; a second MOS transistor connected between the first node and a fourth node, and having its gate connected to the gate of the first transistor; a third MOS transistor connected between the fourth node and the third node; a switch connected between the second and fourth nodes;and a second circuit configured to control the third transistor so as to regulate a voltage from the fourth node to a second setpoint value determined at least in part by a second setpoint voltage.

[0011] According to one embodiment, the fourth node is configured to provide a second supply voltage having a value determined by the first setpoint value when the switch is conducting, and by the second setpoint value when the switch is blocked.

[0012] According to one embodiment, the first circuit comprises: a first resistive voltage divider bridge connected between the second and third nodes; and an error amplifier configured to receive the first setpoint voltage and a voltage from an intermediate node of the first bridge, and to provide to the gate of the first transistor a voltage determined by the difference between the two received voltages.

[0013] According to one embodiment, the second circuit comprises: a second resistive bridge connected between the fourth and third nodes; and an error amplifier configured to receive the second setpoint voltage and a voltage from an intermediate node of the second bridge, and to provide to the gate of the third transistor a voltage determined by the difference between the two received voltages.

[0014] According to one embodiment, a ratio of the dimension ratio of the first transistor to the dimension ratio of the second transistor is greater than 1, preferably greater than 100, for example on the order of 300.

[0015] According to one embodiment, the device further includes a control circuit configured to: deactivate the second circuit and the power source, and command the switch to the on state in a first operating mode; and activate the second circuit and the power source, and command the switch to the blocked state in a second operating mode.

[0016] According to one embodiment, the first and second circuits are configured so that the first setpoint value in the first steady-state mode is equal to the second setpoint value in the second steady-state mode.

[0017] According to one embodiment, the control circuit is further configured, during a transition from the first operating mode to the second operating mode, to successively: control the second circuit so that the second setpoint value is higher than the first setpoint value; activate the current source; control the switching of the switch to the open state to switch from the first operating mode to the second operating mode; and control the second circuit so that the second setpoint value is equal to the first setpoint value.

[0018] According to one embodiment: The first and second transistors have the same type of channel; and the third transistor has a channel of the opposite type to that of the first and second transistors.

[0019] According to one embodiment, the first and second supply voltages are positive with respect to the reference potential, and the first transistor is a P-channel transistor.

[0020] According to one embodiment, the current source includes a resistive element in series with a switch between the second and third nodes.

[0021] Another embodiment provides for an integrated circuit chip comprising: a device as described above; a pad configured to receive the first supply voltage, the first supply voltage corresponding to a supply voltage of the chip; and an integrated circuit connected to the fourth node, the integrated circuit being configured to be powered by the voltage available on the fourth node of said device. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1represents, schematically and in block form, an example of an integrated circuit chip including a voltage regulator; the figure 2 represents an example of a voltage regulator; and the figure 3 represents an example of a voltage regulator implementation method. Description of the implementation methods

[0023] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, the various known electronic circuits that can be used in conjunction with a voltage regulator providing them with a supply voltage have not been detailed, as the voltage regulator embodiments described later are compatible with these known circuits.

[0025] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0026] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0027] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0028] There figure 1 represents, schematically and in block form, an example of an integrated circuit chip 1 including a voltage regulator REG. The circuit of the figure 1 is not included in the subject matter of the attached claims.

[0029] Chip 1 includes input / output pads, each configured to receive a signal from outside chip 1 and / or to provide a signal to the outside of chip 1. figure 1 A pin 100 is configured to receive a DC supply voltage VCC. The VCC voltage is supplied to pin 100 by a voltage source external to chip 1, and is not shown in figure 1 .

[0030] Chip 1 includes at least one integrated circuit IC configured to be powered by a DC supply voltage VDD, the value of the voltage VDD being lower than that of the voltage VCC.

[0031] For this purpose, chip 1 includes the voltage regulator REG. The REG is configured to receive the VCC voltage and to output the VDD voltage from the VCC voltage. The REG therefore comprises a node 102, corresponding to an input of the REG circuit, configured to receive the VCC voltage, and a node 104, corresponding to an output of the REG circuit, configured to output the VDD voltage. For example, input 102 of the REG circuit is connected to pin 100 of chip 1. Similarly, output 104 of the REG circuit is connected to an input 106 of the IC circuit, with input 106 configured to receive the VDD supply voltage from the IC circuit.

[0032] As an example, chip 1 also includes a pin 107 configured to receive a reference potential GND, for example ground.

[0033] The VCC and VDD voltages are, for example, referenced to the GND potential. For example, the REG circuit includes a node 108, corresponding to an input of the REG circuit, configured to receive the GND potential, with node 108 being, for example, connected to pin 107. For example, the IC circuit includes a node 110, corresponding to an input of the IC circuit, configured to receive the GND potential, with node 110 being, for example, connected to pin 107.

[0034] In this example, the VCC and VDD voltages are positive.

[0035] As previously stated, it is desirable that, in a first operating mode (REG), the current drawn by the REG circuit at pin 100 to supply the voltage VDD varies with the current draw of the IC, that is, with the current drawn at output 104 of the REG circuit by the IC powered by the voltage VDD. It is also desirable that, in a second operating mode of the REG circuit, the current drawn by the REG circuit at pin 100 to supply the voltage VDD be constant and therefore independent of the current draw of the IC powered by the voltage VDD. In other words, it is desirable that the REG circuit can operate in the first mode during initial phases of operation and in the second mode during subsequent phases of operation. Put yet another way, it is desirable that the REG circuit can operate alternately in the first and second operating modes.

[0036] In the example of the figure 1 , only the two input / output pins 100 and 107 are represented although, in practice, chip 1 may include many other input / output pins.

[0037] Furthermore, in the example of the figure 1 , only one IC circuit is powered by the VDD voltage although, in other unillustrated examples, several integrated circuits of chip 1 are powered by the same VDD voltage, these circuits then all being coupled, e.g. connected, to node 104 of the REG circuit.

[0038] There figure 2 represents an example of a REG1 voltage regulator that can be used as a REG regulator in chip 1.

[0039] Thus, the REG1 circuit includes node 102 configured to receive the VCC voltage, node 104 configured to provide the VDD voltage, and node 108 configured to receive the GND reference potential. For example, nodes 102, 104, and 108 correspond respectively to an input, an output, and an input of the REG1 circuit.

[0040] The REG1 circuit also includes a first voltage regulator 200, for example, called a serial regulator. When activated, for example by a control circuit not shown but part of the REG1 circuit, regulator 200 is configured to provide the VDD voltage from the VCC voltage. Thus, regulator 200 is connected to nodes 102 and 108 to receive the VCC voltage, and to node 104 to provide the VDD voltage.

[0041] The regulator 200 includes, more specifically, a MOS transistor P1 and a control circuit 202 configured to control transistor P1. Transistor P1 is connected between nodes 102 and 104. For example, transistor P1 has its source connected to node 102 and its drain connected to node 104. In this example, where the voltages VCC and VDD are positive, transistor P1 is a P-channel transistor, or, in other words, transistor P1 is a PMOS transistor.

[0042] The transistor P1 control circuit 202 is configured, when the regulator 200 is active, to control transistor P1, that is to say to provide a control voltage on the gate of transistor P1, so that the voltage VDD is at a value equal to a setpoint value.

[0043] The setpoint value of the voltage VDD, for the regulator 200, is at least partly determined by a setpoint voltage V1. The voltage V1 is a DC voltage.

[0044] In this example, circuit 202 includes a resistive bridge 204 connected between nodes 104 and 108. The resistive bridge 204 is configured to provide a feedback voltage V1fb whose value is determined by the value of the voltage VDD. In the example of the figure 2 The resistive bridge 204 comprises two resistive elements R1 and R2 in series between nodes 104 and 108. Element R1 is connected to node 104, and the voltage V1fb is available at the node where element R1 connects to element R2. In other, unshown examples, the bridge 204 may comprise more than two resistive elements. When circuit 202 includes a resistive voltage divider bridge 204, as in figure 2, the resistance value of the resistive elements of bridge 204 and the intermediate node of bridge 204, that is to say the connection node between two resistive elements of bridge 204, where the voltage V1fb is taken determines, with the voltage V1, the setpoint value of the voltage VDD for the regulator 200.

[0045] In another example not shown, the voltage VDD can be used directly as the voltage V1fb and the circuit 202 is then without bridge 204. In this case, the setpoint value of the voltage VDD for the regulator 200 is determined solely by the voltage V1.

[0046] Furthermore, still using the example of the figure 2The circuit 202 includes an error amplifier 206 configured to provide a voltage Vg1 whose value is determined by the difference between the voltages V1 and V1fb, or, more generally, to provide a voltage Vg1 whose value is determined by the difference between the voltage VDD and its setpoint value. The voltage Vg1 is then the control voltage applied by the circuit 202 to the gate of transistor P1. For example, the circuit 206 is implemented by an operational amplifier having an inverting input (-) receiving the voltage V1, a non-inverting input (+) receiving the voltage V1fb, and an output providing the voltage Vg1.

[0047] When the regulator 200 is inactive, i.e. commanded to be inactive or disabled, the circuit 202 is configured so that the transistor P1 is blocked.

[0048] The REG1 circuit also includes a second voltage regulator 208, for example, called a shunt regulator. Regulator 208 is configured, when activated, for example by the control circuit not shown, to provide the VDD voltage from the VCC voltage. Thus, regulator 208 is connected to nodes 102 and 108 to receive the VCC voltage, and to node 104 to provide the VDD voltage.

[0049] The regulator 208 includes more particularly a MOS transistor N1, a control circuit 210 configured to control the transistor N1, and a circuit 212 for supplying a constant current to node 104 from the voltage VCC.

[0050] Circuit 212 includes a transistor P2 connected between nodes 102 and 104. For example, transistor P2 has its source connected to node 102 and its drain connected to node 104. In this example where the voltages VCC and VDD are positive, transistor P2 is a P-channel transistor, or, in other words, transistor P2 is a PMOS transistor.

[0051] Circuit 212 is configured, when regulator 208 is active—for example, when activated by the control circuit not shown—to bias the gate of transistor P2 so that the current I1 in transistor P2, which corresponds to the current drawn from node 102, is constant. For example, circuit 212 is configured so that the current I1 is equal to K times a reference current Iref, with K a positive factor. Thus, in figure 2Transistor P2 corresponds to the second transistor in a current mirror. P2 provides the output current of the mirror, and the other transistor, P3, receives the reference current (Iref) supplied by a current source (214) in circuit 212. The factor K is then defined as the ratio between the size ratio of transistor P2 and the size ratio of transistor P3. Transistors P2 and P3 naturally have channels of the same type, namely P-type channels in this example.

[0052] More specifically, in circuit 212 of the figure 2The transistor P3 has its source connected to node 102, its gate connected to the gate of transistor P2, and its drain connected to its gate and to one terminal of the current source 214, the other terminal of the current source 214 being connected to node 108. In other words, transistors P2 and P3 are mounted in current mirror, transistor P3 is connected in series with the current source 214 between nodes 102 and 108 and transistor P3 has its gate and its drain connected.

[0053] Transistor N1 is connected between nodes 104 and 108. For example, transistor N1 has its source connected to node 108 and its drain connected to node 104. Transistor N1 has a channel of the opposite type to that of transistor P2's channel. Thus, in this example where VCC and VDD are positive, transistor N1 is an N-channel transistor, or, in other words, an NMOS transistor.

[0054] The control circuit 210 of transistor N1 is configured, when the regulator 208 is active, to control transistor N1, that is to say to provide a control voltage on the gate of transistor N1, so that the voltage VDD is at a value equal to a setpoint value.

[0055] The setpoint value of the voltage VDD, for the regulator 208, is at least partly determined by a setpoint voltage V2. The voltage V2 is a DC voltage.

[0056] In this example, circuit 210 includes a resistive bridge 216 connected between nodes 104 and 108. The resistive bridge 216 is configured to provide a feedback voltage V2fb whose value is determined by the value of the voltage VDD. In the example of the figure 2The resistive bridge 216 comprises two resistive elements R3 and R4 in series between nodes 104 and 108. Element R3 is connected to node 104, and the voltage V2fb is available at the node where element R3 connects to element R4. In other, unshown examples, the bridge 216 may comprise more than two resistive elements. When circuit 210 includes a resistive voltage divider bridge 216, as in figure 2 , the resistance value of the resistive elements of bridge 216 and the intermediate node of bridge 216, that is to say the connection node between two resistive elements of bridge 216, where the voltage V2fb is taken determines, with the voltage V2, the setpoint value of the voltage VDD for the regulator 208.

[0057] In another example not shown, the voltage VDD can be used directly as the voltage V2fb and the circuit 210 is then without bridge 216. In this case, the setpoint value of the voltage VDD for the regulator 208 is determined solely by the voltage V2.

[0058] Furthermore, still using the example of the figure 2The circuit 210 includes an error amplifier 218 configured to provide a voltage Vg2 whose value is determined by the difference between the voltages V2 and V2fb, or, more generally, to provide a voltage Vg2 whose value is determined by the difference between the voltage VDD and its setpoint value. The voltage Vg2 is then the control voltage applied by the circuit 210 to the gate of transistor N1. For example, the circuit 218 is implemented by an operational amplifier having an inverting input (-) receiving the voltage V2, a non-inverting input (+) receiving the voltage V2fb, and an output providing the voltage Vg2.

[0059] When the regulator 208 is inactive, that is, controlled so as to be inactive or disabled, the circuit 212 is configured so that transistor N1 is blocked, and, in addition, the current source 214 is disabled, or, put another way, turned off.

[0060] The control circuit not shown for controllers 200 and 208, which is part of controller REG1, is configured to: activate regulator 200 and deactivate regulator 208 when the REG1 circuit is in a first operating mode where the current drawn from node 102 varies with the variations in the consumption of a load connected to node 104; and activate regulator 208 and deactivate regulator 200 when the REG1 circuit is in a second operating mode where the current drawn from node 102 must be constant regardless of the variations in the consumption of a load connected to node 104.

[0061] The REG1 circuit therefore makes it possible to supply the voltage VDD from the voltage VCC, so that the current drawn on node 102 varies with the consumption of the loads supplied by the voltage VDD in a first mode of operation, and that the current drawn on node 102 is constant and independent of the consumption of the loads supplied by the voltage VDD in a second mode of operation.

[0062] However, to achieve this, the regulator includes two relatively large and bulky transistors, P1 and P2, compared to transistor P3. Indeed, these transistors P1 and P2 must allow the maximum current that the voltage source VCC can deliver to node 102, and therefore to node 104, to pass through their terminals. For example, for a given application, this maximum current may have a value of approximately 20 mA.

[0063] It would therefore be desirable to have a REG1 voltage regulator that allows the same operation as the REG2 regulator but with a reduced size.

[0064] There figure 3 represents an example of an embodiment of such a voltage regulator REG2.

[0065] The REG2 regulator includes elements in common with the REG1 regulator of the figure 2 Thus, unless otherwise indicated, for the same element belonging to both REG1 and REG2 regulators, everything stated for that element when it belongs to REG1 also applies to that element when it belongs to REG2. Furthermore, only the differences between REG1 and REG2 regulators are highlighted here.

[0066] The RGE2 regulator therefore includes nodes 102, 108, and 104.

[0067] The REG2 regulator includes a series voltage regulator 300 identical to the regulator 200 described previously. Thus, the regulator 300 includes the MOS transistor P1 and a control circuit 302 for transistor P1. Circuit 302 is, for example, identical to circuit 202 described previously. For example, circuit 302 includes the resistive voltage divider 204 and circuit 206.

[0068] However, while in regulator 200 transistor P1 is connected between nodes 102 and 104, in this embodiment, transistor P1 of regulator 300 is connected between node 102 and a node 350.

[0069] In addition, when circuit 302 includes bridge 204, the latter is connected between nodes 350 and 108 rather than between nodes 104 and 108 as is the case in circuit REG1.

[0070] The REG2 regulator further includes a 308 derivative voltage regulator similar to the 208 regulator in that it includes: transistor P2, connected between nodes 102 and 104; transistor N1, connected between nodes 104 and 108; a control circuit 310 for transistor N1, for example identical to control circuit 210, supplying voltage Vg2 to the gate of transistor N1; and a current source 314.

[0071] However, the 308 regulator differs from the 208 regulator in that: the current source 314 is connected between nodes 350 and 108; the regulator 308 is devoid of transistor P3; and the current source 314 is configured, when activated, for example by a CTRL control circuit which is part of the REG2 circuit and is configured to control regulators 300 and 308, to provide a current Iref'.

[0072] Indeed, it is proposed here, when the regulator 308 is active, to use the current source and reuse the regulator 300 to bias the gate of transistor P2, so that the constant current I1 flows between the terminals of transistor P2.

[0073] To achieve this, the REG2 controller also includes an IT switch that connects node 350 to node 104. In other words, the IT switch has one conduction terminal connected to node 350 and another conduction terminal connected to node 104. The IT switch is controlled, for example, by the CTRL circuit. For instance, the IT switch is in the conducting state when controller 308 is inactive, and in the blocking state when controller 308 is active.

[0074] Furthermore, the current source 314 is selectively activated. In other words, the current source is alternately controlled to a state where it delivers the current Iref', in which case the current source 314 is said to be on or activated, and to a state where it does not deliver the current Iref', in which case the current source 314 is said to be deactivated or off. As an example, the current source 314 is controlled by the CTRL circuit. For instance, the current source 314 is activated when the regulator 308 is active, and deactivated when the regulator 308 is deactivated.

[0075] In the REG2 regulator, when regulator 300 is active, regulator 308 is inactive; that is, circuit 310 is deactivated, thus switching transistor N1 to the off state, and, furthermore, current source 314 is switched off. In this first operating mode, where regulator 300 is active and regulator 308 is inactive, switch IT is switched on.

[0076] As an example, in this first mode of operation, to limit current leakage in bridge 216, it is provided that the resistive element R4 of bridge 216 has a controllable resistance value, and element R4 is then controlled to have its maximum resistance value, preferably so that element R4 is equivalent to an open circuit.

[0077] As an alternative, when regulator 308 is inactive, a switch can be provided that is open when regulator 308 is inactive and closed when regulator 308 is active. This switch can be placed between node 104 and transistor N1. However, when regulator 308 is active, this can lead to significant voltage drops across the switch, which is undesirable. This switch can also be placed in series with bridge 216 between nodes 104 and 108. However, this too can lead to significant voltage drops across the switch, which is undesirable.

[0078] Furthermore, in the REG2 regulator, when regulator 308 is active, regulator 300 is inactive. In this second operating mode, where regulator 308 is active, the current source 314 is activated, and the IT switch is open. However, unlike the REG1 circuit where circuit 202 opens transistor P1 when regulator 200 is inactive, in the REG2 circuit, control circuit 302 continues to operate and control transistor P1 so that the voltage at node 350 is regulated to the setpoint of regulator 300.

[0079] In the first mode of operation, transistors P1 and P2 are connected in parallel between nodes 102 and 104, 350. The two transistors P1 and P2 therefore deliver a current together to node 104 and circuit 302 controls transistor P1, and therefore transistor P2, so that the voltage VDD is regulated to the setpoint value of regulator 300, the latter being at least partly determined by the value of voltage V1.

[0080] In the second operating mode, when the setpoint value of the voltage VDD for the regulator 308 is equal to the setpoint value of the voltage VDD for the regulator 300, which is the case in steady state, for example by assuming that the voltages V1 and V2 are equal, and that the ratio R1 / R2 is equal to the ratio R3 / R4, then the voltage on node 350 is regulated to the same value as the voltage VDD on node 104. Since transistors P1 and P2 have the same gate voltage Vg1 and the same source voltage VCC, transistor P2 delivers the current I1 at a value determined by the current flowing through transistor P1 and by the ratio between the dimension ratio of transistor P2 to the dimension ratio of transistor P1.Now, the current in transistor P1 when regulator 300 is inactive, that is to say, when it does not directly regulate the voltage VDD on node 104, the current in transistor P1 is equal to the current Iref' if the current in bridge 204 is neglected, or to the sum of the current Iref' and the current in bridge 204 if the current in bridge 204 is not neglected, this current then being approximately equal to VDD / (R1+R2) in the example of the . figure 3 Thus, the current I1 in transistor P2 is indeed equal to K times the current in transistor P1, with K determined by the ratio of dimensions between transistors P1 and P2.

[0081] For example, the ratio between the size ratio of transistor P1 to the size ratio of transistor P2 is positive and for example greater than 100, preferably greater than or equal to 300, for example equal to about 300. In this way, the current I1 in transistor P2 when regulator 308 is active is greater than the current in transistor P1, for example greater than 100 times the current in transistor P1, preferably greater than or equal to 300 times the current in transistor P1, for example equal to about 300 times the current in transistor P1.

[0082] Thus, in the REG2 circuit, transistor P2 has similar, or even identical, dimensions to transistor P2 for the same current values ​​I1, and transistor P1 is therefore smaller than transistor P1 in the REG1 circuit, and smaller than transistor P2 in the REG2 circuit. The REG2 circuit therefore contains one less large transistor than the REG1 circuit, and is thus more compact.

[0083] According to one embodiment, since in the second operating mode the voltage at node 350 is equal to the regulated voltage VDD at node 104, the current source 314 can be implemented using a resistor R, the current Iref' then being equal to VDD / R. For example, this resistor is in series with a switch that is either on or off when the source 314 is on or off. Alternatively, the resistor R is a controllable resistor and is set to its maximum value, preferably corresponding to an open circuit, when the source 314 is off.

[0084] According to one embodiment, to avoid cross conduction between the two regulators 300 and 308 during a transition from the first operating mode to the second operating mode, the following process is implemented, for example by the CTRL circuit.

[0085] At an initial stage, regulator 300 is active and regulator 308 is inactive. Switch IT is therefore closed, current source 314 is inactive or off, and circuit 310 controls transistor N1 in the closed state.

[0086] In a subsequent step, the VDD voltage setpoint for regulator 310 is modified so that, when regulator 308 is switched to the active state, it will attempt to regulate the voltage at node 104 to a higher value than the value to which regulator 300 regulates the VDD voltage at node 104. In other words, the VDD voltage setpoint for regulator 308 is set to a higher value than the VDD voltage setpoint for regulator 300. As a result, transistor N1 is then controlled to the open state by circuit 310.

[0087] As an example, the setpoint value for the voltage VDD for the regulator 308 is changed by correspondingly changing the value of the voltage V2.

[0088] As an alternative example, in an embodiment where the two bridges 204 and 216 are identical and where the voltage V1fb is taken from an intermediate node of bridge 204 corresponding to the intermediate node of bridge 216 from which the voltage V2fb is taken, in order to avoid generating two different setpoint voltages V1 and V2, the setpoint value of the voltage VDD for the regulator 308 is modified by changing the resistance value of one of the resistive elements of bridge 216. For example, when the voltages V1 and V2 are equal and elements R1 and R3 have the same resistance value, if elements R2 and R4 have the same resistance value, the setpoint values ​​of the voltage VDD are the same for both regulators 300 and 308, and, if the resistive element R4 has a lower resistance value than that of the resistive element R2, then the setpoint value of the voltage VDD for the regulator 308 will be higher than that for the 300 regulator.

[0089] In a subsequent step, the current source 314 is switched to the active state and begins to deliver the current Iref'.

[0090] In a subsequent step, regulator 308 is switched to the active state. Since its VDD voltage setpoint is higher than that of regulator 300, as previously mentioned, transistor N1 remains controlled in the off state.

[0091] The regulator 300 is then switched to the off state by opening the IT switch. As a result, the VDD voltage at node 104 increases until it reaches the VDD voltage setpoint for the regulator 308.

[0092] Before or when the VDD voltage reaches this setpoint, the VDD voltage setpoint for the 308 regulator is again changed to be equal to the VDD voltage setpoint for the 300 regulator.

[0093] It should be noted that the implementation method for the transition process from the first operating mode to the second operating mode described for the REG2 circuit can be adapted and implemented in the REG1 circuit example described in relation to the figure 2 , for example in the following way.

[0094] At an initial stage, regulator 200 is active and regulator 208 is inactive.

[0095] In a subsequent step, the VDD voltage setpoint for regulator 208 is set to a higher value than the VDD voltage setpoint for regulator 200.

[0096] In a subsequent step, regulator 208 is switched to the active state. Because the setpoint value of the voltage VDD for regulator 208 is higher than the setpoint value of the voltage VDD for regulator 200, transistor N1 is held open by circuit 210.

[0097] In a subsequent step, regulator 200 is switched to the inactive state. As a result, the VDD voltage at node 104 increases until it reaches the setpoint value of the VDD voltage for regulator 208.

[0098] Before or when the VDD voltage reaches this setpoint, the VDD voltage setpoint for the regulator 208 is again changed to be equal to the VDD voltage setpoint for the regulator 200.

[0099] Various embodiments and variations have been described. Those skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, although examples have been described in which the VCC and VDD voltages are positive and transistors P1 and P2 are P-channel while transistor N1 is N-channel, in other, unillustrated examples, the VDD and VCC voltages are negative, with VDD being lower in absolute value than VCC. In this case, transistors P1 and P2 are N-channel and transistor N1 is P-channel. Those skilled in the art will be able to adapt the implementation of circuits 302 and 310, if necessary, for example, by reversing the input voltages to the inverting and non-inverting inputs of circuits 206 and 218.

[0100] Furthermore, although not detailed, in one embodiment the REG2 regulator is implemented in chip 1, instead of the REG regulator.

[0101] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

1. Device (REG2) comprising: a first MOS transistor (P1) connected between a first node (102) configured to receive a first power supply voltage (VCC), and a second node (350); a selectively activable current source (314) connected between the second node (350) and a third node (108) configured to receive a reference potential (GND); a first circuit (302) configured to control the first transistor (P1) so as to regulate a voltage of the second node to a first set point value at least partly determined by a first set point voltage (V1); a second MOS transistor (P2) connected between the first node (102) and a fourth node (104), and having its gate connected to the gate of the first transistor (P1); a third MOS transistor (N1) connected between the fourth node (104) and the third node (108); a switch (IT) connected between the second and fourth nodes (350, 104); and a second circuit (310) configured to control the third transistor (N1) so as to regulate a voltage (VDD) of the fourth node (104) to a second set point value at least partly determined by a second set point voltage (V2).

2. Device according to claim 1, wherein the fourth node (350) is configured to deliver a second power supply voltage (VDD) having a value determined by the first set point value when the switch (IT) is on, and by the second set point value when the switch is off.

3. Device according to claim 1 or 2, wherein the first circuit (302) comprises: a first resistive voltage dividing bridge (204) connected between the second and third nodes (350, 108); and an error amplifier (206) configured to receive the first set point voltage (V1) and a voltage (V1fb) of an intermediate node of the first bridge (204), and to supply the gate of the first transistor (P1) with a voltage (Vg1) determined by the difference between the two received voltages (V1, V1fb).

4. Device according to any of claims 1 to 3, wherein the second circuit (310) comprises: a second resistive bridge (216) connected between the fourth and third nodes (104, 108); and an error amplifier (218) configured to receive the second set point voltage (V2) and a voltage (V2fb) of an intermediate node of the second bridge (216), and to supply the gate of the third transistor (N1) with a voltage (Vg2) determined by the difference between the two received voltages (V2, V2fb).

5. Device according to any of claims 1 to 4, wherein a ratio of an aspect ratio of the first transistor (P1) to an aspect ratio of the second transistor (P2) is greater than 1, preferably greater than 100, for example in the order of 300.

6. Device according to any of claims 1 to 5, wherein the device further comprises a control circuit (CTRL) configured to: deactivate the second circuit (310) and the current source (314), and control the switch (IT) to the on state in a first operating mode; and activate the second circuit (310) and the current source (314), and control the switch (IT) to the off state in a second operating mode.

7. Device according to claim 6, wherein the first and second circuits (302, 310) are configured so that the first set point value in the first mode in steady state is equal to the second set point value in the second mode in steady state.

8. Device according to claim 6 or 7, wherein the control circuit (CTRL) is further configured, during a transition from the first operating mode to the second operating mode, to successively: - control the second circuit (310) so that the second set point value is higher than the first set point value; - activate the current source (314); - control the switching of the switch to the off state to switch from the first operating mode to the second operating mode; and - control the second circuit (310) so that the second set point value is equal to the first set point value.

9. Device according to any of claims 1 to 8, wherein: - the first and second transistors (P1, P2) have a channel of the same type; and - the third transistor (N1) has a channel of the type opposite to that of the channel of the first and second transistors.

10. Device according to claim 9, wherein the first and second power supply voltages (VCC, VDD) are positive with respect to the reference potential (GND), and the first transistor (P1) has a P channel.

11. Device according to any of claims 1 to 10, wherein the current source (314) comprises a resistive element in series with a switch between the second and third nodes (350, 108).

12. Integrated circuit chip (1) comprising: a device (REG2) according to any of claims 1 to 11; a pad (100) configured to receive the first power supply voltage (VCC), the first power supply voltage corresponding to a power supply voltage of the chip (1); and an integrated circuit (IC) connected to fourth node (104), the integrated circuit (IC) being configured to be powered with the voltage (VDD) available on the fourth node of said device (REG2).

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