Multibeam antenna and method for producing a multibeam antenna

Abstract

The invention relates to a multibeam antenna (1) having: a substrate (S); and a metasurface on the substrate (S), said metasurface being designed as a matrix comprising rows (6) and columns (4, 5) of unit cells of a first (2) and second (3) type, wherein the multibeam antenna (1) is designed to emit signals with a set phase in multiple directions simultaneously on the basis of a periodic arrangement of the unit cells of the first (2) and second (3) type on the substrate (S).

Description

[0001] Description

[0002] Multibeam antenna and method for manufacturing the same

[0003] A multi-beam antenna

[0004] TECHNICAL FIELD

[0005] The invention relates to a multi-beam antenna having the features of the preamble of claim 1 and a method for producing such an antenna.

[0006] The following background is intended only to provide information necessary to understand the context of the inventive ideas and concepts disclosed herein. Therefore, this background section may contain patentable subject matter and should not, per se, be considered prior art.

[0007] BACKGROUND

[0008] Demand for mobile broadband is growing rapidly; technological applications such as the Internet of Things (IoT) and machine-to-machine (M2M) communications are also experiencing continuous development. This market demand has led to an increase in the number of base stations, antennas, and antenna masts, which incur high CAPEX and OPEX. Multibeam antennas play an important role in solving these problems, as they can fulfill the function of multiple antennas in a single device.

[0009] Typically, mobile operators use three sectors within a 360° coverage area. Therefore, many antenna towers are currently overcrowded with 4G and SG antennas. Finding more space on antenna towers for emerging 5G and 6G technologies and reducing the number of base station locations in cities is a future challenge. Furthermore, creating multiple narrow beams will improve spectral efficiency and increase the capacity of wireless network systems by enabling the reuse of frequency resources within a given area without degrading signal quality due to self-interference.

[0010] Signal quality (SNR) in tall buildings is typically poor because the top floors receive multiple signals from different base stations simultaneously, which interfere with each other. This degrades data rates and voice quality. Mobile operators are typically forced to deploy multiple antennas with different tilts / angles to optimize coverage in terms of elevation and azimuth.

[0011] Mobile phones operate using various technologies, such as 3G, 4G, 5G, Wi-Fi, and GPS. They are already congested and are becoming increasingly smart and compact, requiring more compact antennas. The new 5G standard uses millimeter-wave bands to provide broadband services. However, path loss is very high in these bands. Therefore, highly directional and tightly steerable beams are required to compensate for the path loss. Conventional phased array antennas are difficult to install in mobile phones due to their limited size. In addition, phased array antennas integrate a phase shifter and digital beamforming to enable multi-beam steering, requiring more power and size.

[0012] An efficient multi-beam structure is also required in microwave imaging applications, such as security screening and medical diagnostics. Conventional state-of-the-art systems utilize either mechanical raster scanning or phased array antenna systems. Mechanical raster scanning is slow and cumbersome because it scans point-by-point, whereas phased array antenna systems require complete phase control for each antenna. According to the Nyquist limit, scanning the human body at millimeter scales requires thousands of antenna elements, each requiring separate RF circuitry (e.g., phase shifters, power amplifiers). This results in a complex, costly, and energy-consuming architecture for beam sweeping. Phased array antenna systems also require a large number of input ports with dedicated feed networks.Common types of feed networks include Butler Matrix, Luneburg, and Rotman lens. However, they can only achieve predefined beam angles and are complex and bulky. Most phased array antenna systems also have RF gain control components (either attenuators or variable-gain amplifiers) at each antenna element. These components are used to correct amplitude errors associated with other circuit elements and are typically also used to control the RF amplitude of the RF signal at each antenna element, and thus the sidelobe levels.

[0013] Furthermore, MIMO phased array antenna systems require power-hungry digital-to-analog converters (DACs, ADCs) and beam processing. Phased array antennas therefore have a complex hardware architecture and consume a lot of power.

[0014] Metasurface antennas are also being researched for use in beam steering, beam shaping, and multi-beam generation. Metasurfaces are planar 2D structures consisting of an array of metamaterial elements. These metamaterial elements are called unit cells or metaatoms. Metamaterials are artificial, subwavelength structures that enable electromagnetic properties not found in natural materials. Metasurfaces are fabricated by printing very small metal patches (subwavelength) onto a grounded dielectric plate to control the wavefronts emitted by the antenna, preferably without phase shifters and complex structures like conventional array antennas.

[0015] Conventional metasurface structures have a small number of simultaneous beams, limited bandwidth, a large or multi-layered structure, low efficiency, an unstable beam pattern over the frequency sweep, and uneven gain for the radiated beams.

[0016] In summary, conventional phased array antennas have limited suitability for meeting the requirements of future communication systems, which require a large number of antenna elements to achieve high directivity and multiple beams. This is because conventional phased array antennas have a complex hardware architecture and high power consumption, as each antenna element in the phased array antenna system requires a phase-shift circuit and a power amplifier to compensate for insertion loss.

[0017] The invention is based on the object of solving at least some of the above-mentioned disadvantages in the prior art and, in particular, of reducing manufacturing, implementation and / or usage costs.

[0018] SUMMARY

[0019] This summary is intended to introduce a selection of features and concepts of the invention that are explained further in the description. This summary is not intended to identify important or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0020] According to the invention, the above-mentioned object is achieved by the features of the independent claims.

[0021] Specifically, the problem is solved by a multi-beam antenna. The multi-beam antenna has a substrate. The multi-beam antenna further has a metasurface on the substrate. The metasurface is designed as a matrix with rows and columns of unit cells. The unit cells are of a first type and a second type. The two different types are different from each other. The two types differ in the structure of the metallization. The multi-beam antenna is designed to radiate phase-adjusted signals in multiple directions simultaneously, based on a periodic arrangement of the unit cells of the first and second type on the substrate.

[0022] The invention has the advantage that manufacturing, implementation and / or usage costs can be reduced due to the simplified structure.

[0023] A unit cell can, for example, be understood as a cell with a fixed dimension, in particular as a metallized elementary area of ​​the metasurface. The unit cells can therefore be described by their two-dimensional mapping. The unit cells of the first type can have the same size as the unit cells of the second type and differ only in the metallization. For example, each unit cell has a substantially rectangular or substantially square shape. In general, the unit cells can have the same dimensions, preferably the same height, width and / or length. The dimensions can be significantly smaller than an operating wavelength, e.g., smaller than 0.25 times (or 0.2 times, or 0.15 times, or 0.1 times) the operating wavelength.The operating wavelength can correspond to a wavelength for which the multi-beam antenna is designed / impedance-matched, i.e. in particular a center frequency or a carrier frequency.

[0024] The periodic arrangement of the unit cells of the first and second kind can be understood as an arrangement pattern of the unit cells of the first and second kind repeating itself relative to each other, for example more than once, twice, three times, four times or five times.

[0025] Advantageous embodiments of the invention are specified in the subclaims.

[0026] A portion, preferably a majority, of unit cells belonging to the same row may have an electrically conductive connection to one another within an overall metasurface area. Another remaining or remaining portion thereof may, for example, have no electrically conductive connection to one another within the overall metasurface area.

[0027] All unit cells belonging to the same row can have an electrically conductive connection to each other within an entire area of ​​the metasurface.

[0028] For example, all unit cells belonging to different rows have no electrically conductive connection to each other within the entire area of ​​the metasurface.

[0029] This allows a beam that is narrower in elevation and adjustable in azimuth to be achieved.

[0030] With respect to a region of the multi-beam antenna consisting exclusively of the matrix, each unit cell, in particular regardless of its type, can be electrically connected to a respective row of the matrix. For example, a junction of all adjacent unit cells in a respective row of the matrix can be, for example, exclusively metallic.

[0031] With respect to the region of the multi-beam antenna consisting exclusively of the matrix, each unit cell, especially of the same type, in a respective column of the matrix may not be electrically conductively connected. For example, a junction of all adjacent unit cells in a respective column of the matrix may be, for example, exclusively free of metal.

[0032] The phase-adjusted signals can be in-phase signals. This allows an explicit beam pattern to be defined without phase shift. In this case, the multi-beam antenna can explicitly operate without active elements. The phase-adjusted signals can also be signals that are uniformly phase-shifted from row to row of the matrix. The term "uniform" can mean that a uniform phase angle can be specified from row to row of the matrix.

[0033] This allows the application range of the multi-beam antenna to be significantly expanded.

[0034] The multi-beam antenna can be flat. In particular, the multi-beam antenna can consist only of the substrate and one or more types of metal. For example, the multi-beam antenna can be a sandwich consisting of a substrate between two metallization surfaces. The top side of the substrate is metallized in a structured manner, and the bottom side of the substrate is metallized in a flat manner. Other active and passive elements can be omitted or even absent from the multi-beam antenna.

[0035] The metasurface or the unit cells can consist of a, preferably continuous, single metal layer and can be printed onto the, preferably single-layer, substrate.

[0036] This allows for easy production of the multi-beam antenna.

[0037] The multi-beam antenna may have a single, e.g., full-area metal surface on the opposite side of the metasurface on the substrate. The metal surface may form a ground (GND).

[0038] This allows for the creation of a sandwich structure consisting essentially of two basic elements (substrate and metal). Thus, only the substrate itself is located between the two metal surfaces on the top and bottom of the substrate.

[0039] The unit cells of the first type can be arranged in columns and / or rows, alternating with the unit cells of the second type. Each row or column can have the same periodic arrangement pattern as every other row or column of the matrix. Adjacent unit cells can be of different types in the row direction of the matrix. Adjacent unit cells can be of the same type in the column direction of the matrix.

[0040] The unit cells of the first type may have a smaller impedance than the unit cells of the second type, for example, less than 0.8 times (or 0.75 times or 0.5 times) the impedance of the unit cells of the second type. For example, a metal area of ​​the unit cells of the first type may be larger than a metal area of ​​the unit cells of the second type, for example, more than 1.25 times (or 1.5 times) the metal area of ​​the unit cells of the second type. For example, the metasurface of the multi-beam antenna may be structured exclusively from two types of unit cells.

[0041] A metallization pattern of the unit cells can be different along each column of the matrix. A metallization pattern of the unit cells can be different along each row of the matrix. This metallization pattern can be constant in the row direction of the matrix and change periodically in the column direction.

[0042] One of the columns at the edge of the matrix (outermost column) can have respective feed points corresponding to the row. The number of feed points can correspond to the number of feed points located at one outer edge of the matrix, e.g., the number of rows. The feed points can be configured to feed the phase-adjusted signals, preferably into the rows / in sequence / row by row.

[0043] The multi-beam antenna may have a single feed port. The feed port may be configured to feed a signal on which the phased signals are based. The feed port may also be configured to feed the phased signal. The multi-beam antenna may have a splitter. The splitter may be configured to split the signal into the phased signals and forward them to the respective feed points. The splitter may also be configured to forward the phased signal to the respective feed points. This provides the unit cells with a simple and cost-effective signal feed.

[0044] The feed port can be electrically connected to the feed points via transmission lines. The divider device can consist of N1 signal dividers, e.g., Wilkinson dividers. N can denote the number of feed points and / or the number of rows in the matrix. To form the in-phase signals, the divider device can contain no active elements and electrically connect the feed port to all feed points, e.g., impedance-matched. However, to form the uniformly phase-shifted signals, the divider device can also have N phase shifters in order to uniformly shift the phase of the signal fed into the feed port from row to row of the matrix. The phase shifters can each be arranged downstream directly before the respective feed points. Thus, the phase shifters can each be connected after the signal dividers arranged directly before the feed points (last downstream).The phase shifters can be implemented by switches with PIN diodes.

[0045] In particular, at least some or all of the connecting lines, e.g., the transmission lines, may be printed lines in the form of striplines on the substrate, for example, the connecting lines of the multi-beam antenna located on the substrate. The striplines may be microstrip lines, symmetric striplines, shielded striplines, coplanar lines, and / or dual-strip lines.

[0046] Some or all elements of the multi-beam antenna can be printed on one and the same substrate.

[0047] A flat and passive device can therefore be provided with which a plurality of beams can be generated. Furthermore, simple circuits can be integrated to enable multi-beam control. Space and energy can therefore be saved. The above-mentioned object is also achieved by a method for producing a multi-beam antenna, for example as described above. The method comprises providing a substrate. The method further comprises providing a metasurface by forming a matrix with rows and columns of unit cells of a first and second type on the substrate. The method further comprises periodically arranging the unit cells of the first and second type on the substrate to enable the multi-beam antenna to radiate phased signals in multiple directions simultaneously.

[0048] Manufacturing, implementation and / or deployment costs can generally be reduced.

[0049] The above-mentioned object is also achieved by a computer program. The computer program comprises instructions that, when executed by a computer, cause the computer to perform the method described above or at least one of the steps thereof. The computer program can, for example, be a module for starting / operating a computer device as described herein.

[0050] The above-mentioned task is also achieved by a data storage medium. The computer program can be stored on a machine-, processor-, or computer-readable storage medium, such as a permanent or rewritable storage medium. This also includes the possibility of making the computer program available for download on a server or a cloud server, e.g., via a data network such as the Internet or a communications connection such as a wireless connection.

[0051] In other words, the invention relates to a multibeam metasurface antenna based on a single substrate layer and a single feed port. Thus, the multibeam metasurface antenna can generate up to eleven simultaneous beams with only one feed port. The overall structure of the multibeam metasurface antenna can be passive and, for example, contain no phase shifters. The multibeam metasurface antenna can consist of a flat, single-layer substrate. The substrate can be easily implemented using standard printed circuit board technology.

[0052] For some frequencies in the millimeter wave range (from 20 GHz to 40 GHz), various antennas have been created that can radiate from two to eleven simultaneous beams depending on the setting of the parameters (metallization, basic shape, unit cell size, unit cell metallization per type, substrate thickness, substrate type, etc.).

[0053] All beams can have approximately the same high gain. Furthermore, other practical beam shapes can be achieved by designing the metasurface geometry. For example, narrow pencil beams, fan beams, simultaneous end- and backfire beams, and narrow hemispherical beams can be created that can cover 180° with a constant gain in azimuth. Any number of simultaneous beams (more than 25 beams) can also be achieved by using more than one injection port.

[0054] The concept can be explicitly extended to the 2.6 GHz and 6 GHz bands. At least two simultaneous beams can be achieved in each band.

[0055] This multi-beam metasurface antenna can be combined with various base stations and portable transmitting and receiving devices, such as mobile phones or radar devices. The multi-beam metasurface antenna can thus be used in applications such as 4G, 5G, and 6G communication systems, radar, automotive, energy harvesting, reconfigurable smart surfaces, and imaging, including security screening systems and medical diagnostics.

[0056] The time to market for a product using such a multi-beam metasurface antenna is expected to be short, as it can achieve a lower C-SWaP (cost, size, weight and power consumption) than current commercial antennas.

[0057] In other words, the invention describes a flat structure based on passive elements that can generate multiple beams simultaneously without the use of complex RF circuits such as phase shifters, power amplifiers, and / or beamformers as in phased array antenna systems. The flat structure is based on the metasurface principle, in which the unit cells are designed and optimized to influence the dispersion properties of surface waves. The surface impedance of these unit cells is periodically modulated, resulting in the conversion of surface waves into leaky waves and, depending on the desired radiation pattern, into free-space waves.

[0058] In this application, the radiation pattern of this multi-beam antenna can be customized to create multiple narrow beams, each of which can cover a specific floor of a building. Furthermore, each beam can provide 180° coverage in the azimuth plane, allowing the same floors of many buildings to be covered simultaneously with good gain. This allows the mobile operator to offer more data capacity and reduce many resources such as space and power. Furthermore, the radiation pattern can be customized to user needs, allowing it to be used in a variety of scenarios, such as hotspots, indoors, and rural areas.

[0059] Another application for the multi-beam metasurface antenna could be energy harvesting. For example, when portable devices are idle, they can receive multiple RF signals from the environment via the simple passive multi-beam metasurface antenna while maintaining high gain. This technique allows more energy to be harvested than with conventional antennas.

[0060] The overall structure can thus be cost-effective, simple, thin, planar, and passive. The multi-beam antenna can be easily customized depending on requirements regarding the number of simultaneous beams and the possible beam patterns.

[0061] The simultaneously generated beams of the multi-beam antenna can have uniformly high gain and low sidelobe values. Furthermore, the radiation pattern can be stable over a wide frequency range, which is desirable in mobile network systems.

[0062] Because the structure is planar, dynamic multi-beam formation is possible by integrating active elements such as diodes, transistors, varactors, and switches into the unit cells. The multi-beam antenna can be provided monolithically or hybridly on the substrate, which forms the core layer of the printed circuit board (PCB). The optional elements used for the multi-beam antenna can be surface-mounted devices (SMDs). SMD components are soldered directly onto the circuit board using solderable pads (flat assembly). The associated technology is surface-mounting technology (SMT).Alternatively or in addition to the SMD components that do not have wire connections, the elements optionally used for the multi-beam antenna can be leaded components that are mounted using through-hole technology (THT).

[0063] The core layer of the circuit board can be made of electrically insulating material. Conductive connections or tracks (for example, on the multi-beam antenna 1 itself) can be adhered to one side of the electrically insulating material. The other side of the electrically insulating material can be a continuously conductive surface, which can form the ground (GND) of the circuit board. Fiber-reinforced plastic or laminated paper can be provided as the insulating material. The tracks / metallizations can be etched from a layer of metal, such as copper, for example, with a thickness in the range of 20 to 35 μm. The designed multi-beam antenna can be compatible with current phased array antenna systems such as Massive MIMO, i.e., each array of unit cells (which can also be considered an array element) can be fed separately to achieve beam steering and generate desired beam patterns.This can reduce the complexity and power consumption of conventional beamforming circuits, as each array of unit cells can generate many beams simultaneously.

[0064] Although some of the aspects described above are described with reference to the multi-beam antenna, these aspects may also apply to the method. Likewise, the aspects described above with reference to the method may apply correspondingly to the multi-beam antenna.

[0065] All technical and scientific terms used herein have the meaning commonly understood by those skilled in the art in the technical field of antenna technology; they are to be interpreted based on the definitions found in the dictionary or the technical jargon of that technical field. If technical terms are used incorrectly and thus do not express the technical idea of ​​the present invention, they shall be replaced by technical terms that provide a correct understanding to those skilled in the art.

[0066] The terms "first" and "second" are intended to distinguish components from one another. For example, a first component can be referred to as the second component, and a second component as the first component.

[0067] If it is stated here that a component is "connected" to another component, this may mean, for the purposes of this disclosure, that these components may also be directly connected to each other. The term "directly" indicates that there is no further component in between.

[0068] The process steps described herein should not be interpreted as requiring them to be performed in a particular order, unless expressly or implicitly stated otherwise, for example, if these process steps cannot be interchanged for technical reasons. The process steps may also be performed directly one after the other (without any further intervening steps) and / or continuously.

[0069] BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Further objects, features, advantages, and possible applications will become apparent from the following description of non-limiting embodiments with reference to the accompanying drawings. The same or similar elements in the drawings are always provided with the same or similar reference numerals. Detailed explanations of well-known functions and structures are omitted where they would detract from the scope of the invention.

[0071] The drawings show in:

[0072] FIG. 1 shows a principle of the multi-beam antenna described herein;

[0073] FIG. 2 is a plan view of a multi-beam antenna according to a first

[0074] embodiment;

[0075] FIG. 3 is a plan view of a multi-beam antenna according to a second

[0076] embodiment;

[0077] FIG. 4 is a schematic representation of the method for manufacturing the multi-beam antenna; and

[0078] FIG. 5 is a view of a computer used in the manufacture of the multi-beam antenna.

[0079] DETAILED DESCRIPTION The multi-beam antenna and the method of manufacturing the same will now be described with reference to the embodiments. While not intended to be limiting, specific details are explained to provide a deeper understanding of the invention.

[0080] Fig. 1 to 3 schematically show respective multi-beam antennas 1, in which Fig. 1 is intended to illustrate the essential basic principle of the multi-beam antenna 1 and the multi-beam antenna 1 from Fig. 2 and 3 is intended to represent an example of an implementation.

[0081] Thus, the multi-beam antenna 1 essentially has two different components: the substrate S and a metallization 8 on the top and bottom of the substrate S. The metallization on the bottom of the substrate S (the invisible plane in Figs. 1 to 3) can be fully metallized to form a ground for the multi-beam antenna 1. The metallization 8 on the top of the substrate S can be formed in the form of a matrix in which at least two different types 2, 3 of unit cells are formed. The different types 2, 3 of unit cells are arranged alternately or with a different period shape along each row. Each row forms a continuous electrically conductive surface. Each row is essentially a copy of every other row.The rows can be insulated from one another, at least with respect to a region formed by the matrix, since an electrical connection can be formed outside the matrix region by the divider device mentioned herein. The periodic arrangement of the columns 4, 5 is shown schematically. In Figs. 2 and 3, the various columns 4, 5 are each divided by a dash 7 in the column direction in order to better distinguish the unit cells 2, 3. Furthermore, Figs. 2 and 3 show a row insulation 12 in the row direction, which is present between respective rows 6 in order to insulate them from one another in the matrix region.

[0082] The feed is effected via transmission lines 9, which can be impedance-matched. The smallest line spacing 10 between transmission lines 9 directly coupled to adjacent feed points 11 can be greater than the smallest respective spacing of the transmission lines 9 in an area directly in front of the corresponding feed point 11, in which the transmission line 9 runs adjacent to and parallel to an edge of the corresponding unit cell 2.

[0083] The examples of metallizations 8 on the top side of the substrate S in Fig. 2 and 3 can be summarized at least in the basic principle from Fig. 1.

[0084] The metallization 8 in Fig. 2 shows two different types 2, 3 of unit cells, with the first type 2 of unit cell having a larger metal surface than the second type 3 of unit cell. This can be seen, for example, in the web of the first type 2 unit cell compared to the web of the second type 3 unit cell. As a result, the impedance of the second type 3 unit cell is more than twice (or three times) as high as the impedance of the first type 2 unit cell. The metallization of both types 2, 3 can be described by an H-shape, with the two parallel regions being connected by means of a different web depending on the type. The web of the second type 3 is at least twice (or three times or four times) as small as the web of the first type 2. The correspondingly parallel regions of the H-shaped unit cells of the first type 2 and second type 3 touch each other.

[0085] The metallization 8 in Fig. 3 is similar to the metallization 8 in Fig. 2 in that corresponding webs (although not H-shaped) between corresponding unit cells of the first 2 and second 3 types have different sizes. In the case of Fig. 3, the opposite is true of Fig. 2, because in Fig. 3, the first 2 type of unit cells have a higher impedance than the second 3 type of unit cells. However, the connection at the respective dashes 7 in Fig. 3 behaves exactly like the connection at the respective dashes 7 in Fig. 2. Here, the transition between each unit cell in a row 6 of the matrix is ​​metallic. In other words, there are no joints at the transition, or the transition is smooth or not visible.

[0086] For the task in Fig. 1 to 3 it can be summarized that the width of the metallization 8 of the corresponding unit cells 2, 3 in

[0087] The direction of wave propagation can be preset to achieve a desired radiation pattern. For this purpose, the various unit cells 2 or 3 can have ridges of different widths (extending in the direction of wave propagation or the row direction of the matrix), or the width of the ridges can be preset / specified. The number of ridges within a unit cell can be at least one. As can be seen in Fig. 3, the number of ridges can also be two or more. The impedance of the unit cell(s) - measured in the row direction - can be decisive for the type and appearance of the ridges. In this way, unit cells of the first 2 and second 3 types can be selected which have a corresponding impedance pattern to one another in order to achieve a desired radiation characteristic.

[0088] Fig. 4 shows a schematic representation of the method S0 for manufacturing the multi-beam antenna 1. The method S1 comprises providing S1 the substrate S. The method S0 comprises providing S2 the metasurface by forming the matrix with the rows 6 and the columns 4, 5 from the unit cells of the first type 2 and the second type 3 on the substrate S. The method S0 further comprises periodically arranging S3 the unit cells of the first type 2 and the second type 3 on the substrate S to enable the multi-beam antenna 1 to radiate the phased signals in the multiple directions simultaneously.

[0089] The method steps illustrated as blocks of the block diagram in Fig. 4 may, for example, be substantially embodied in a machine-, processor-, or computer-readable medium and thus executed by a computer 13 or processor 14, as described below with reference to Fig. 5. Examples may further be or refer to a computer program including program code for executing at least some of the method steps of Fig. 4 when the computer program is executed on the computer 13 or processor 14. An example may also include non-volatile memory or persistent storage 16, as also described below with reference to Fig. 5, which is machine-, processor-, or computer-readable and encodes machine-executable, processor-executable, or computer-executable programs with instructions that cause some or all of the method steps to be executed. Fig.Figure 5 schematically shows a block diagram illustrating a computer 13. The computer 13 may, for example, describe at least part of a computing device used to manufacture the multi-beam antenna 1.

[0090] The computer 13 implements one or more steps of the method SO for manufacturing the multi-beam antenna, as shown in Fig. 4. In particular, the computer 13 provides functionality, such as computer software, that runs on the computer 13 and performs one or more steps of the method SO. In particular, the computer 13 can execute instructions associated with the DATA required to manufacture the multi-beam antenna 1, which are contained in the computer program described herein, and cause the computer 13 to perform the one or more steps of the method SO. The data required to manufacture the multi-beam antenna 1 (hereinafter referred to as manufacturing data) can include setting parameters such as metallization, basic shape, unit cell size, unit cell metallization per type, substrate thickness, substrate type, etc.

[0091] It is contemplated herein that computer 13 may take any suitable physical form. By way of example, computer 13 may be embodied at least in part as an embedded computer, system-on-chip (SOC), single-board computer (SBC), server, and / or user equipment (UE). Computer 13 may be unified or distributed; span one or more locations; span one or more machines or data centers; or be located in a cloud, which may include cloud components in a network. Computer 13 may perform one or more steps of method SO without substantial spatial or temporal limitation. By way of example, computer 13 may perform one or more steps of method SO in real time, in parallel, or in batch mode. Computer 13 may perform step(s) of method SO at different times or at different locations.

[0092] The computer 13 has at least one or more of the following components: a processor 14, a volatile memory 15, a persistent memory 16 with a controller 17 and a non-volatile memory (NVM) device 18, a bus 19, an arbiter 20, a power connector 21, a main power supply 22, an auxiliary power supply 23, and an input / output (I / O) interface 24. The components of the computer 13 can be implemented at least partially in hardware and / or software. The interconnection of the components of the computer 13 is structured as shown in Fig. 3 merely for the sake of simplicity. In particular, the interconnection and connection can differ in implementation due to signal processing and signaling. Fig. 5 shows, by way of example, that the main power supply 22 is an external device. This component can, of course, also be part of the computer 13 itself.

[0093] The processor 14 has means for executing instructions associated with the manufacturing data, e.g., of the computer program described herein. For example, the processor 14 may load the instructions associated with the manufacturing data contained in the computer program described herein, e.g., from the volatile memory 15 and / or the persistent memory 16, and then execute the instructions, which in turn causes the processor 14 to perform the one or more steps of the method 50, as illustrated, e.g., in Fig. 4. The processor 14 may have an internal register / cache for the manufacturing data, for the instructions associated with the manufacturing data, and / or for associated addresses. The processor 14 may have an FPLA, an FPGA, a microcontroller, a CPU, a GPU, an ASIC, and / or a DSP for accessing the internal register / cache.As an example, to execute instructions associated with the manufacturing data, processor 14 may retrieve them from processor 14's internal register / cache, volatile memory 15, or persistent storage 16; decrypt and execute them; and then write a result to processor 14's internal register / cache, volatile memory 15, or persistent storage 16.

[0094] As an example, processor 14 may include an instruction cache, a data cache, and / or a translation buffer (TLB). The instructions related to the manufacturing data in the instruction cache may be copies of instructions in volatile memory 15 and / or persistent storage 16, and the instruction cache may accelerate the retrieval of these instructions related to the manufacturing data by processor 14. The manufacturing data in the data cache may be copies of data for the instructions currently executing on processor 14 and related to the manufacturing data in volatile memory 15 and / or persistent storage 16.The results of previous instructions executing on processor 14 and associated with the manufacturing data may be provided for access by subsequent instructions executing on processor 14 and associated with the manufacturing data, or for writing to volatile memory 15 and / or persistent storage 16. The data cache may accelerate the read or write operations of processor 14. The addresses in the TLB associated with the manufacturing data may be address references to addresses in volatile memory 15 and / or persistent storage 16 to accelerate virtual address translation for processor 14.

[0095] The volatile memory 15 may be a dynamic RAM (DRAM) or a static RAM (SRAM). The volatile memory 15 may, in particular, be embodied as the data storage medium described herein, on which the computer program described herein may be at least temporarily stored. Furthermore, the volatile memory 15 may be a single-channel or multi-channel RAM. The volatile memory 15 may include a main memory for storing instructions related to the manufacturing data for the processor 14, which then executes these instructions; or include the manufacturing data for the processor 14, which the processor 14 uses to operate on them. For example, the computer 13 may load these instructions into the volatile memory 15 from the persistent memory 16 or another source (such as another computer, the network, or the cloud).Processor 14 may then load these instructions from volatile memory 15 into processor 14's internal register / cache. To execute these instructions, processor 14 may retrieve and decrypt these instructions from the corresponding internal register / cache. During or after executing these instructions, processor 14 may write a result (which may be intermediate or final results) to the internal register / cache. Processor 14 may then write the result to volatile memory 15. For example, processor 14 executes only instructions related to manufacturing data in processor 14's internal register / cache or volatile memory 15 (as opposed to persistent memory 16), and operates only on the manufacturing data in processor 14's internal register / cache or volatile memory 15 (as opposed to persistent memory 16).A memory management unit (MMU - not shown) may be located between the processor 14 and the volatile memory 15 and may support access to the volatile memory 15 requested by the processor 14 and associated with the manufacturing data.

[0096] The volatile memory 15 can be a memory shared by the processor 14 and the I / O interface 24. The I / O interface 24 accesses the shared volatile memory 15 via the processor 14. For example, the I / O interface 24 can not contain any built-in memory. In this case, the I / O interface 24 can share the volatile memory 15 connected to the processor 14. The processor 14 can have a memory access path that enables access to the shared volatile memory 15 associated with the manufacturing data. The I / O interface 24 accesses the shared volatile memory 15 via the memory access path of the processor 14. The I / O interface 24 is enabled access to the shared volatile memory 15 associated with the manufacturing data while the memory access path is active and the processor 14 is inactive.In this case, the memory access path is active without intervention by the processor 14. The memory access path is disabled while the processor 14 and the I / O interface 24 are inactive. The memory access path is enabled without intervention by the processor 14 as soon as a request to couple the memory access path to the processor 14 is received while the memory access path is disabled and the I / O interface 24 is active.

[0097] The persistent memory 16 has a mass storage device, e.g., a non-volatile memory (NVM) 18 for the manufacturing data or the instructions associated with the manufacturing data. The persistent memory 16 can, in particular, be embodied as the data storage device described herein, on which the computer program described herein can be stored. As an example, the persistent memory 16 can be a solid-state memory (SSD), a flash memory, a non-volatile memory card, a Secure Digital Memory Card (SD), an Embedded Multi Media Card (eMMC), and / or a Universal Serial Bus (USB). The persistent memory 16 can store the manufacturing data in an erasable or non-erasable manner. The persistent memory 16 can be located in the computer 13, i.e., internally, or externally thereto.The persistent memory 16 may include the controller 17, which supports communication for passing the manufacturing data between the processor 14 and the persistent memory 16, in particular the NVM 18 of the persistent memory 16.

[0098] For example, the NVM 18 can be an NVM package consisting of a buffer chip and NVM chips. The NVM chips each have a status output pin. The controller 17 controls the NVM chips and has a first pin. The buffer chip is connected between the controller 17 and the NVM chips. The buffer chip has a second pin that outputs an external status signal to the first pin of the controller 17, and a third pin that receives internal status signals indicating the respective states of the NVM chips from the status output pins. Furthermore, the buffer chip outputs the external status signal with a fixed period based on the internal status signals. The fixed period can be a duty cycle. The internal status signals indicate either a first or second state. The duty cycle of the external status signal is determined depending on an identifier (ID - e.g.The controller 17 determines the state of the NVM chip(s) that outputs the internal state signal indicating the first state among the NVM chips (initialized at startup of the computer 13). The controller 17 receives the external state signal from the buffer chip. Based on the external state signal, the controller 17 delivers a status read command to the NVM chips and a write / read command to at least one of the NVM chips through the buffer chip based on the specified period or duty cycle included in the external state signal. The controller 17 writes / reads the manufacturing data to / from the NVM chips that receive the write / read command via the buffer chip. A manufacturing data reordering method may be employed in the persistent memory 16. Here, a batch of manufacturing data is reordered using one of the NVMs 18 at one level of the NVM hierarchy.Reordering involves streaming one portion of the manufacturing data stack and retrieving another portion of the manufacturing data stack in parallel with streaming one portion of the manufacturing data stack. The reordered stack (combined from one portion and the other portion) is then stored in another NVM of the NVM 18 at a different level of the NVM hierarchy.

[0099] The processor 14 can be connected to the persistent memory 16 directly or indirectly, e.g., via an internal host controller (not shown). The connection can be implemented via a clock bus, command bus, and data bus. This is shown only schematically using bus 19 in Fig. 5. In the case of a separate host controller, this is electrically connected to the processor 14 and to the persistent memory 16. The host controller is preferably part of the processor 14. The persistent memory 16 receives commands related to the manufacturing data and the manufacturing data in conjunction with a clock signal provided by the processor 14 or the host controller on the clock bus. The clock signal clocks the reception of the commands related to the manufacturing data and the manufacturing data. The processor 14 or the host controller sends a command related to the manufacturing data to the persistent memory 16 via the command bus.Furthermore, the processor 14 or the host controller sends the manufacturing data according to the command via the data bus to the persistent memory 16 or receives the manufacturing data from the persistent memory 16 via the data bus. Furthermore, the processor 14 or the host controller sends another command related to the manufacturing data via the command bus to the persistent memory 16, during or before the transmission of the manufacturing data. One command is a command accompanied by the manufacturing data and the other command is a command not accompanied by the manufacturing data. The processor 14 or the host controller sends the other command when the persistent memory 16 is in an active state. The active state of the persistent memory 16 is indicated by the data bus. In the active state, the manufacturing data can be read from the NVM 18 of the persistent memory 16 into a data buffer (e.g.,as part of the buffer chips (not shown) of the permanent memory 16 in order to be able to retrieve the manufacturing data more quickly with another command.

[0100] In one example, the NVM 18 may have a clock pin through which the clock signal is received from the controller 17 of the persistent memory 16. The clock signal may be a write enable signal and / or a read enable signal. The NVM 18 may further have first and second I / O pins. The manufacturing data is received from the controller 17 of the persistent memory 16 in synchronization with the clock signal via the first I / O pin. The NVM 18 may further have a command / address buffer (e.g., as part of the buffer chip), a memory cell array (e.g., as part of the NVM chips - not shown), and control logic (not shown). The command / address buffer operates at a first operating speed and, in synchronization with the clock signal, buffers the command and corresponding address received via the second I / O pin and associated with the manufacturing data. The NVM 18 may further have an I / O buffer (e.g.,as part of the buffer chip) that operates at the first operating speed and buffers the manufacturing data as read data from the memory cell array or writes the manufacturing data as write data to the memory cell array. The first and second I / O pins can coincide. In this case, the clock signal can be formed by a first and second clock signal, in which the first clock signal only switches during a period in which the command and the address (both related to the manufacturing data) are received from the controller 17, and the second clock signal only switches during a period in which the manufacturing data is received from the controller 17. The first operating speed corresponds to a data input speed or data output speed between the NVM 18 and the controller 17 of the persistent memory 16.The control logic controls an operation with respect to the memory cell array based on the buffered command and the buffered address (both related to the manufacturing data). The control logic operates at a second operating speed that is lower than the first operating speed. The second operating speed corresponds to an internal operating speed of the NVM 18. The bus 19 may be understood herein as a subsystem of the computer 13 that transfers the manufacturing data and / or electrical power between the components of the computer 13. The (one) bus 19 may interconnect the components of the computer 13 via the same set of lines. The bus 19 may be configured for dedicated communication of the manufacturing data between two or more of the components of the computer 13.Bus 19 can have a ring topology, star topology, (partially) meshed topology, bus topology, tree topology, and / or line topology. Bus 19 can have one or more of the following bus types: Accelerated Graphics Port (AGP), HyperTransport (HT), Industry Standard Architecture (ISA), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Serial Advanced Technology Attachment (SATA), and / or INFINIBAND.

[0101] Bus 19 can be a system bus through which processor 14 is connected to the other components of computer 13. In this case, bus 19 can be synchronous—the transfer of production data occurs bidirectionally with a clock edge of bus 19's clocking—and / or asynchronous—no clocking, but a handshake occurs to transfer the production data. In such a semi-synchronous system bus, bus 19 is clocked, but control lines enable wait cycles to allow even slow components, such as persistent memory 16, to be used via bus 19.

[0102] Arbiter 20 can be provided for at least partial control over bus 19. Arbiter 20 can be considered a coprocessor subordinate to processor 14. Arbiter 20 regulates access to bus 19 related to the manufacturing data based on a two-way handshake or three-way handshake. For this purpose, three signals are used: Bus Request (BREQ) for forwarding the manufacturing data, Bus Grant (BGRT) for confirming and approving the forwarding, and Bus Grant Acknowledge (BGA) for optional forwarding feedback. Arbiter 20 simultaneously receives multiple BREQs from different components of computer 13 via bus 19. Arbiter 20 sorts the BREQs by priority and forwards them sequentially—in a pipeline—to processor 14. Once the processor 14 has received the BREQ, the processor 14 sends the BGRT to the arbiter 20 or directly to the component of the computer 13 that sends the BREQ.A lower-ranking BREQ of the BREQs in the pipeline—e.g., from another component of computer 13—is forwarded to processor 14 in response to a BGRT sent by processor 14 relating to the BREQ with priority in the pipeline and related to at least a portion of the manufacturing data. The BGRT related to the lower-ranking BREQ is sent from processor 14 to arbiter 20 after at least a portion of the manufacturing data has been processed. Arbiter 20 may, for example, in turn, in response to the BGRT related to the lower-ranking BREQ, send a BREQ further downstream in the pipeline—e.g., relating to another portion of the manufacturing data—to processor 14. Likewise, in response to each BGRT from processor 14, arbiter 20 may send a respective BGA related to it to processor 14. With the procedure described here, a BGA can be omitted entirely.This saves overhead in the communication between the components of computer 13. That is, instead of a three-way handshake, a two-way handshake is provided.

[0103] Bus 19 may also include a data bus, address bus, and control bus. Production data is transferred bidirectionally between the components of computer 13 via the data bus. The address bus is operated solely by processor 14 and unidirectionally transfers memory addresses associated with the production data. The control bus is controlled solely by arbiter 20, e.g., in the sense of a watchdog, and transfers control of it to the processor in the pipelined manner described above to control the transfer of production data.

[0104] The power connector 21 can be arranged at a dedicated connection point on a housing of the computer 13. The power connector 21 can represent a central power supply point for the components of the computer 13 and connects the computer 13 or its components to the main power supply 22. In the case of an integrated main power supply 22, the power connector 21 can be an integrated part of the computer 13 or the main power supply 22.

[0105] The main power supply 22 supplies at least one or more of the components of the computer 13 with electrical power, e.g., via the bus 19. In particular, the main power supply 22 charges the auxiliary power supply 23 with electrical power, e.g., from outside the computer 13, e.g., in the case that the main power supply 22 is connected to a power source outside the computer 13. Here, the main power supply 22 may represent a preferred component used to power the components of the computer 13 and may, for example, comprise an accumulator or a battery. The main power supply 22 may comprise further components such as voltage regulators, DC voltage stabilizers, series regulators, buck converters, and / or boost converters to meet the respective requirements of the components of the computer 13.Here, the main power supply 22 can have either a dedicated fixed power connection to the power source, such as a power grid, or a detachable power supply connection for charging the accumulator or battery of the main power supply 22. For this purpose, the main power supply 22 can have an inverter to provide a predetermined DC power supply from an external AC power source as the power source, wherein the DC power supply is then supplied to the components of the computer 13 via the aforementioned voltage regulators.

[0106] The auxiliary power supply 23 is connected to the volatile memory 15 and / or the permanent memory 16 via the bus 19. The auxiliary power supply 23 is charged by the electrical power of the main power supply 22. The auxiliary power supply 23 can be arranged inside or outside the computer 13, or inside or outside the volatile memory 15 and / or the permanent memory 16. For example, the auxiliary power supply 23 can be housed on a motherboard of the computer 13 to supply the volatile memory 15 and / or the permanent memory 16 with auxiliary power. The auxiliary power supply 23 can, in particular, be embodied in the form of a supercapacitor, an accumulator, and / or a battery. The power capacity (energy capacity) of the main power supply 22 can be many times greater, for example, at least 10 times or 50 times greater, than the power capacity (energy capacity) of the auxiliary power supply 23.

[0107] The processor 14 monitors changes in the electrical power supplied by the main power supply 22. In the event of a sudden power failure, e.g., if the power source external to the computer 13 is disconnected from the main power supply 22 or the main power supply 22 degrades or fails for another reason, and the processor 14 determines that the electrical power supplied by the main power supply 22 to one or more of the components of the computer 13 has fallen below a threshold, e.g., 0.8 or 0.75 of an operating power of the main power supply 22, the processor 14 causes the auxiliary power supply 23 to assume a remaining supply power for a shutdown of the computer 13. The shutdown includes supplying at least the processor 14, the volatile memory 15, and / or the persistent memory 16 with electrical power for the duration of the shutdown.During the shutdown process, the manufacturing data currently located in the volatile memory 15 and / or the manufacturing data currently being processed in the processor 14, for example, in the register / cache of the processor 14, are transferred from the volatile memory 15 and / or the processor 14 to a meta-area of ​​the persistent memory 16. For this purpose, the meta-area of ​​the persistent memory 16 can be reserved specifically for the shutdown process.

[0108] During a boot process of the computer 13, during which the main power supply 22 again provides operating power, the processor 14 loads the manufacturing data from the meta-area of ​​the persistent memory 16 to enable faster data processing. The meta-area of ​​the persistent memory can be released after the boot process or successively during the boot process.

[0109] The I / O interface 24 can enable user interaction with the computer 13. In particular, the manufacturing data or the corresponding parameters can be entered via this interface. The I / O interface 24 can have a device and / or software driver that enables the processor 14 to control the I / O interface 24 to retrieve the setting parameters or manufacturing data and provide them to the components of the computer 13.

[0110] In summary, the invention will simplify the installation of mobile networks. It will help make cities more environmentally friendly by reducing power consumption and reducing or eliminating visual pollution from large antenna masts. Many mobile phone manufacturers could leverage this technology to reduce size, cost, and power consumption. Furthermore, the invention could be used in many other applications such as radar systems, imaging, automotive, vehicle sensors, and energy harvesting.

[0111] At this point, it should be noted that all parts described above, viewed individually and in any combination, particularly the details shown in the drawings, are claimed as essential to the invention. Modifications to these are familiar to those skilled in the art.

[0112] LIST OF REFERENCE SYMBOLS

[0113] 1 multi-beam antenna

[0114] 2 Unit cell of the first kind

[0115] 3 Unit cell of the second kind

[0116] 4 Column of the first kind

[0117] 5 Column of the second type

[0118] 6 rows of the same type

[0119] 7 dash

[0120] 8 Metallization

[0121] 9 Transmission line

[0122] 10 cable spacing

[0123] 11 Feed-in point

[0124] 12 Series insulation 13 Computer

[0125] 14 processor

[0126] 15 Volatile memory

[0127] 16 Permanent memory 17 Controller

[0128] 18 NVM

[0129] 19 buses

[0130] 20 arbiters

[0131] 21 Power connection 22 Main power supply

[0132] 23 Auxiliary power supply

[0133] 24 I / O interface

[0134] S substrate

Claims

Claims Multi-beam antenna (1), comprising: a substrate (S); a metasurface on the substrate (S) which is designed as a matrix with rows (6) and columns (4, 5) of unit cells of a first (2) and second (3) type, characterized in that the multi-beam antenna (1) is designed to radiate phase-adjusted signals in several directions simultaneously, based on a periodic arrangement of the unit cells of the first (2) and second (3) type on the substrate (S).Multi-beam antenna (1) according to claim 1 or 2, characterized in that a part, preferably a majority, of unit cells (2, 3) belonging to the same row (6) have an electrically conductive connection to one another within an overall area of ​​the metasurface and another remaining part thereof has no electrically conductive connection to one another within the overall area of ​​the metasurface, or all unit cells (2, 3) belonging to the same row (6) have an electrically conductive connection to one another within an overall area of ​​the metasurface; and all unit cells (2, 3) belonging to different rows (6) have no electrically conductive connection to one another within the overall area of ​​the metasurface. Multi-beam antenna (1) according to one of the preceding claims, characterized in that the multi-beam antenna (1) is flat, and the metasurface or the unit cells (2, 3) consist of a metal layer and are printed on the substrate (S). Multi-beam antenna (1) according to one of the preceding claims, characterized in that the multi-beam antenna (1) has a metal surface on the opposite side of the metasurface on the substrate, and the metal surface forms a mass. Multi-beam antenna (1) according to one of the preceding claims, characterized in that the unit cells of the first (2) type are arranged in columns (4, 5) and / or in rows (6) alternating with the unit cells of the second (3) type; and / or adjacent unit cells in the row direction (6) of the matrix are of different types, and adjacent unit cells in the column direction (4, 5) of the matrix are of the same type.

6. Multi-beam antenna (1) according to one of the preceding claims, characterized in that one (4) of the columns (4, 5) at the edge of the matrix has respective feed points (11) corresponding to the row (6), which are designed to feed the phase-adjusted signals; and / or the multi-beam antenna (1) has: a single feed port which is designed to: feed in a signal on which the phase-adjusted signals are based, or to feed in the phase-adjusted signal; and a splitter device which is designed to: split the signal into the phase-adjusted signals and forward them to the respective feed points (11), or forward the phase-adjusted signal to the respective feed points (11).

7. Multi-beam antenna (1) according to one of the preceding claims, characterized in that some or all elements of the multi-beam antenna (1) are printed on one and the same substrate (S).

8. Method (SO) for producing a multi-beam antenna (1) according to one of the preceding claims, the method (SO) comprising: Providing (Sl) a substrate (S); Providing (S2) a metasurface by forming a matrix with rows (6) and columns (4, 5) of unit cells of a first (2) and second (3) type on the substrate (S); characterized by Periodically arranging (S3) the unit cells of the first (2) and second (3) types on the substrate (S) to enable the multi-beam antenna (1) to radiate phased signals in multiple directions simultaneously.

9. A computer program, characterized in that the computer program comprises instructions which, when the computer program is executed by a computer (13), cause the computer (13) to carry out the method according to claim 8 or at least one of the steps thereof.

10. Data carrier, characterized in that the computer program according to claim 9 is stored on the data carrier.

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