Method for detecting parallel circuits in power supply devices

Abstract

The invention relates to a method for detecting parallel circuits of output channels in power supply devices, in which a neural network implemented in a first digital computer of a monitoring device is provided for detecting the parallel circuits, wherein various operating states are triggered in a power supply device to determine training data (UCℎ1[0] UCℎ2[1] UCℎ1[2] UCℎ2[3]... UCℎ1[j −3] UCℎ2[j − 2]UCℎ1[j −1] UCℎ2[j]) for the neural network, and the associated voltage curves and / or current curves are measured at the output channels, wherein the training data is transmitted to another digital computer by means of which the neural network is trained, and wherein the trained ready-to-use neural network is implemented in the first digital computer of the monitoring device and used to detect parallel circuits.

Description

[0001]202216491 1 Description / Description Title of the invention / Title of the invention Method for detecting parallel connections in power supply devices. The invention relates to a method for detecting parallel connections, in particular in power supply devices. The advantages of electronic fuses in the field of industrial DC power supplies compared to conventional fuses or electromagnetic releases are leading to these fuses being increasingly used. As the performance of these DC power supplies increases, so do the demands placed on the fuses. A particular challenge is the parallel operation of power supply channels, as is common to increase output power. Various operating situations such as channel start-up, overcurrent limitation, shutdown, setpoint specification, etc. must be adapted to parallel operation.By automatically detecting a parallel connection of channels, the monitoring device can recognize this at an early stage and adjust accordingly. EP2812969 B1 describes the operation of power supplies with outputs that can be connected in parallel. Various methods are proposed for determining whether two or more output channels have been connected in parallel. A first method comprises a contacting clamp that, by means of a built-in switch or other electronic contact, signals the parallel connection to the monitoring device and simultaneously establishes the power contact. 202216491 2 Furthermore, a method is described in which a test sequence is carried out during device startup. By briefly switching on an output channel and simultaneously measuring the output voltage on the activated channel and its neighboring channels, it can be determined whether a parallel connection exists by comparing the measured data.If the output voltage increases simultaneously on the activated and an inactive channel, a parallel connection is detected. During operation, a parallel connection can be detected by the current regulation of the power supply. If, for example, two output channels share a load current, this can be determined metrologically in two different ways. By reducing the setpoint on one of the two channels, the current regulator is activated when the setpoint is undershot below the currently flowing load current. This reduces the current through this channel into the load. Either the adjacent channel takes over the current flow, whereby the parallel connection can be detected by summing the currents, or the reduction causes the output voltage on both channels to drop, whereby the parallel connection is in turn detected via the output voltage monitoring. The main disadvantage of the solution described is its complex implementation.The invention is based on the object of specifying a method with which the detection of parallel circuits is improved.According to the invention, this is achieved with a method for detecting parallel connections of output channels in power supply devices, in which a neural network implemented in a first digital computer of a monitoring device is provided for detecting the parallel connections, in which various operating states are triggered in a power supply device to determine training data for the neural network, and the associated voltage curves at the output channels are measured, the training data are transmitted to another digital computer by means of which the neural network is trained, and the trained, ready-to-use neural network is implemented in the first digital computer of the monitoring device and used to detect parallel connections. Advantageous embodiments arise from the subclaims.In classic programming paradigms, the rules of an information technology problem are defined in advance and then implemented in the source code using decision trees, e.g., if{}-else{} statements. The challenge here lies in capturing as many possible states as possible into a uniform set of rules. This set of rules is accordingly rigid and difficult to adapt to changing circumstances that were not considered in advance. Artificial neural networks (ANNs) offer a different, problem-solving-oriented approach. The information technology problem is abstracted (modeling), and through a learning process, the rule finding is left to the model itself.During this learning process, the model is provided with previously measured data sets as input parameters and the corresponding categories as output parameters. Statistical optimization methods are used to attempt to map the input data to these output data. With reference to the problem of parallel connection, series of tests are carried out before the 202216491 4 learning process, in which different load conditions with and without parallel connection are taken into account. This measured data serves as the basis for the input data of the model, with the categorization "parallel" or "single" as the output parameter. After completing the learning process, including subsequent validation and testing of the neural network, a trained model is obtained as the result. This trained model is transferred to the monitoring device, such as a microcontroller, where it is used as part of what is known as "inference".The invention is explained in more detail with reference to figures. They show, by way of example: Fig. 1a, 1b first training data sets Fig. 2a, 2b second training data sets Fig. 3 the topology of a neural network Fig. 4 a sequence of the method according to the invention for detecting parallel connections Fig. 5 sequence of the method according to the invention integrated into the device start-up Fig. 6 sequence of the method according to the invention using the current curve In the method according to the invention, in a first step, training data is first collected for the learning process of the neural network. For this purpose, various operating states are triggered by means of the monitoring device of the power supply, typically a microcontroller, i.e. test series with various load conditions with and without parallel connection are carried out and the output voltage curves U. outCh1 , U outCh2or, if necessary, the current waveforms on the channels are measured. 202216491 5 The term power supply includes power supplies and / or electronic fuses and / or a combination of the two. The measured values ​​are digitized using an analog-to-digital converter (Scan ADC) and written to a buffer memory. The scan duration can be matched to the test sequence by the memory size of the buffer, e.g. n = 200 samples, and the conversion time of the analog-to-digital converter. Preferably, the output data of the analog-to-digital converter is written directly to the memory via so-called direct memory access, without placing a load on the computing core of the monitoring device or the microcontroller. In the exemplary embodiment, the test data is measured by the monitoring device.However, under certain circumstances, it may be expedient to have this measurement of the test data and the formation of the input tensor for the neural network carried out by separate hardware. An example load pattern, as shown in Fig. 1a for independent channels and in Fig. 1b for parallel-connected output channels, comprises a test pulse on a first channel of the power supply in the period t1 to t2. This should be limited in time so that the downstream load does not start up accidentally. Typical values ​​for this are a few 100 µs. Since it can be assumed that not only linear loads will be connected to the power supply, but also those that subsequently exhibit a compensating process, the measurement process continues beyond the pulse duration up to time t3 so that decay processes can be at least partially recorded.202216491 6 The sampled measurement data of the output channels in question, for example n samples, are then stored alternately for both channels in the microcontroller's memory (with increasing memory address) 〈 ^^ ^^ℎ1[0] ^^ ^^ℎ2[0] ^^ ^^ℎ1[1] ^^ ^^ℎ2[1] … ^^ ^^ℎ1[ ^^ − 1] ^^ ^^ℎ2[ ^^ − 1] ^^ ^^ℎ1[ ^^] ^^ ^^ℎ2[ ^^]〉 This arrangement depends on the configuration of the microcontroller and the measurement channels. The index n indicates the discrete sampling points of the analog-to-digital converter. The number of sampling points and the number of channels to be acquired determine the size of the required memory and also the order of the data in the memory.With j as the index of the memory address, the measured values ​​are mapped to the memory as follows: 〈 ^^ ^^ℎ1^0^ ^^ ^^ℎ2^1^ ^^ ^^ℎ1^2^ ^^ ^^ℎ2^3^ … ^^ ^^ℎ1^ ^^ െ3^ ^^ ^^ℎ2^ ^^ െ 2^ ^^ ^^ℎ1^ ^^ െ1^ ^^ ^^ℎ2^ ^^^〉 It would also be conceivable to sample the output voltages with several analog-to-digital converters and store the data in different memory areas. The correct, consistent arrangement and sequence of the data both during training and operation is essential for the successful use, i.e. the inference, of the neural network. Deviations must therefore be corrected in a timely manner. Once the prerequisites have been met, the test sequence can be run several times. First, data sets are collected in which the channels were operated both in parallel and individually. The signal curve of the output voltages thus yields different data sets for individual channels (Fig. 1.a, Fig. 2a) and for parallel connections (Fig.1b, Fig. 2b. 202216491 7 In order to train the neural network for different load situations from the outset, it is advisable to carry out the repetitions with changing loads. Purely resistive loads have a voltage curve approximately as shown in Fig. 1a, 1b. For loads with a capacitive component, the output voltage increases with a delay and is smoothed and possibly delayed, as shown in Fig. 2a, 2b. Furthermore, it is also advisable to vary the input voltage of the electronic fuse in order to cover the entire operating voltage range. For optimal training results, the variation of the aforementioned parameters is preferably random. The training of the neural network and the preprocessing of the data are preferably not carried out in the first digital computer of the monitoring device, but by means of another independent digital computer, for example a commercially available personal computer.The test data measured by the monitoring device is therefore transferred to this personal computer and subjected to preprocessing. This test data is first categorized, in this example by "parallel" and "single." It is also advisable to standardize the raw data to the value 1024 (2nd order). 10 ) and floating-point processing. The normalized raw data is then written into a tensor—a matrix—and forms the so-called input tensor. For example, if n samples are recorded for each run of the test sequence and the run is repeated k times (k records), the result is a matrix of the form [k,i]. 202216491 8 Since two channels are sampled at discrete times n, the buffer must have dimension j, where ^^=2 ^^ Since it is known at the time of data acquisition whether the output channels were connected in parallel, the individual rows of the matrix can be assigned categories such as "Parallel" or "Single". These categories must be mapped numerically. This process is referred to as "hot encoding". The numerical representation is part of the problem abstraction and is necessary for the rule-finding algorithm. Hot encoding is a simple numerical assignment. This allows the input tensor consisting of the test data and the assignment of the state "Parallel" or "Single" to be passed to the neural network for training. The input tensor has a dimension [k,j] and the row-by-row assignment of the state results in a matrix of the form [k, 2]. This matrix is ​​referred to as the output tensor.Neural networks are usually based on the interconnection of many McCulloch-Pitts neurons or slight modifications thereof. In principle, other artificial neurons can also be used, e.g., the high-order neuron. The topology of a network (the assignment of connections to nodes) must be appropriate to the task. As shown in Fig. 3, the present embodiment uses a so-called multi-layer 202216491 9 feedforward network, which, in addition to input and output layers (Input Layer E1, E2…) and output layers A1, A2, also includes hidden layers (Hidden Layers B1, C1…) whose outputs are not visible outside the network. In feedforward networks, a layer is always only connected to the next higher layer. Hidden layers improve the abstraction of the network. The number of neurons in the input layer E1, E2… corresponds to the number of samples of the analog-to-digital converter.The number of neurons in the output layers A1, A2 corresponds to the number of possible outcomes, i.e. "parallel" or "single" or the statement parallel connection yes / no. After the construction of a network follows the training phase, in which the network "learns", mainly by modifying the weights of the neurons. The training of the neural network is computer-aided using conventional programs. Specialized software programs such as TensorflowLite, Keras, Lasagne, Caffe, ONNX, Matlab, etc. are suitable for this. Each software delivers a file containing the functioning neural network as the result of the training process. As can be seen from Fig. 3, the individual neurons are separated between the layers by weights ε. B1C1 In this process, a path through the network is sought and described by a so-called activation function, which is, for example, as follows: ( ^^1 ^^ ^^1 ^^1 + ^^3 ^^ ^^3 ^^1 )+ ^^1 ^^ ^^1 ^^1 + ^^1 ^^ ^^1 ^^1During training, this path is traversed with initialization values ​​for the weighting. By multiplying out and adding, a numerical value for the first output node A1 is obtained along the path. This process is called forward propagation. Since the "true" value for the first output node A1 is known during the training process, the deviation between the calculated result and the actual value is determined. The deviation, or error, provides information about how the weighting factors must be reweighted. The path is calculated backwards from the first output node A1. This process is called back propagation. This process is repeated until the errors are as small as possible for all cases of the input tensors. Since this optimization process could theoretically run endlessly, it is useful to specify during training how many runs, called epochs, should take place.By observing the error rate from epoch to epoch, one can determine whether a model has been sufficiently trained. For training, the available data is preferably divided into training, validation, and test data. For example, 60% of the data is used for pure training and 20% is used to validate the model so that anomalies in the data can be identified. This is intended to prevent, for example, statistical deviations in the data from being overestimated. Finally, 20% of the data is used to test the network. This provides a known dataset that the model never saw during training and can be used to check whether the neural network also produces plausible results with new datasets.The now available file with the functional neural network is then converted into a format suitable for the power supply monitoring device - a microcontroller. This is generally done by translating it into a HEX file, which can then be integrated into the microcontroller's source code, such as any programming library (model.h and model.c) with corresponding parameters and handlers. The sequence of the inventive method for detecting parallel connections during device startup in the monitoring device is shown in Fig. 4. First, the hardware is initialized (Hardware_Init()). This involves setting the clock frequency, for example, and configuring the microcontroller's peripherals. Subsequently, in step ADC_Conf(), the analog-to-digital converter is prepared for sampling the output voltages. The length of the buffer, iethe number of memory locations j is specified, or the sampling time ts is determined. The configuration must be adjusted so that enough samples are collected during the test sequence for operational use. The number of samples n, or the buffer length j, must be the same as for the training data. Furthermore, the analog-to-digital converter is set so that the data sampling runs parallel to the main control process. This is made possible by direct memory access. After configuration, the analog-to-digital converter is triggered (Start_ADC()). The sampling process of the analog-to-digital converter begins and runs parallel to the test sequence. The test sequence can optionally start with a slight time delay in order to take hardware-related conditions into account (Delay(…)). The channel is then switched on (Ch1_ON()) and after a switch-on time ton of typically a few 100 μs (Delay(ton)), channel 1 is switched off again (Ch1_OFF()).During the entire test sequence, both output channels are monitored via the sampling process of the analog-to-digital converter. After triggering the analog-to-digital converter using Start_ADC(), the first value of the output voltage of channel 1 is determined (Scan_UCh1()) and written to the first memory location of the buffer (Val_UCh1 → Buf[ j ]), after which the memory location is incremented (j++). Then, the first 202216491 12 value of the output voltage of channel 2 is determined (Scan_UCh2()) and written to the second memory location of the buffer (Val_UCh2 → Buf[ j ]). The memory address is then incremented again (j++). This process is repeated until the buffer is completely full, with the sampling process taking place at the previously set sampling times ts (Delay(ts)). As soon as the buffer is full, the data is post-processed.If the order of the output voltage values ​​of channel 1 and channel 2 does not match the order in the training data, or if samples are being sampled on two different analog-to-digital converter peripherals, the data must be sorted (Sort_Buf()). This is followed by the same normalization as for the training data (Norm_Buf()). Since the values ​​from the analog-to-digital converter are available as 10-bit integer values, normalization by 1024 is advisable. With 12-bit resolution, the normalization factor would be 4096. After sorting and normalization, the input tensor is available, so that the inference can be performed. The result is the output tensor with the prediction of whether or not the channels are connected in parallel. Based on this information, the monitoring device can configure the channels (Channel_Conf()). This allows the parameters for parallel operation to be adjusted for the further course of the program.These include, in particular, the current distribution of the channels, adaptation of the tripping characteristic, limitation times, and startup behavior. The integration of the method for detecting parallel connections of output channels into the startup of a power supply device is explained using Fig. 5. No separate test sequences are required, and a parallel connection is detected during the startup of channel 1. Channel 1 is switched on and a maximum duty cycle tmax is specified. At the same time, all necessary steps are started in order to be able to perform an inference for parallel connection detection, which may detect a parallel connection of another channel. This means that the initial state of the channel configuration can change during the startup of channel 1. This results in the following scenarios: a) There is no parallel connection, and channel 1 starts up within the maximum startup time tmax.Channel 1 remains switched on and no further steps are necessary. A separate termination criterion is required for this, which can be achieved when the output voltage Uout reaches the value, taking into account a specifiable difference, of the input voltage Uin. Furthermore, a sufficient criterion can also be achieved by observing the output current. b) There is no parallel connection; channel 1 does not start up within tmax and is switched off again and remains in this state. c) Channels 1 and 2 are connected in parallel and this is detected within the maximum start-up time tmax. Channel 2 is switched on and start-up occurs with two parallel channels. d) Channels 1 and 2 are connected in parallel, but this is only detected after tmax has elapsed (or there is not enough time left for channel 1 because it is already too hot for parallel start-up).Both channels are switched off and after a cooling time tcool, channels 1 and 2 start up in parallel. The power supply device then starts up as follows, depending on the current scenario: After channel 1 is switched on, the termination condition is checked: whether the output voltage Uoff has (almost) reached the value of the input voltage Uein (scenario a). The duty cycle is then monitored to prevent the transistor of channel 1 from overheating, and a check is made to see whether a parallel connection of another channel has been detected. These checks are repeated until either the maximum duty cycle is reached (scenario b) and / or a parallel connection has been detected. As described previously, the neural network requires a certain number of samples to be able to detect a parallel connection.Since channel 1 is already starting up, the output voltage at channel 2 will also change in a parallel connection, similar to the test pulse implementation, and can therefore be detected. If the parallel connection is achieved before the maximum duty cycle is reached (scenario c), channel 2 is switched on and both channels start up in parallel. If the parallel connection is only detected after the maximum duty cycle tmax has elapsed, or if there is not enough time left for channel 1 to start up in parallel (scenario d), channel 1 is switched off and after a cooling time tcool has elapsed, the channels start up in parallel. The exemplary embodiments describe the use of the neural network for only two output channels. However, the invention can be applied without restrictions to applications with almost any number of channels.Furthermore, it is possible to record not just one measured value for the channels, but any number of measured values, and then write these to the input tensor. Furthermore, it is also conceivable to execute multiple inferences simultaneously, so that multiple combinations are evaluated simultaneously. A serial sequence of inferences is also conceivable, in order to either use the same neural network for the detection of adjacent channels (1||22||3 3||4), thus saving memory space in the target hardware, or to use multiple different inferences to detect further combinations. Finally, neural networks can also be trained to detect multiple states. By expanding the output tensor, all combinations of the output channels can be mapped (1||2||32||4 1||3||4, etc.). The method according to the invention can also be used during ongoing operation of a power supply device.In addition, the output current waveforms can also be used as data for the neural network instead of the voltage waveforms. If the current setpoint is briefly changed on a channel, either the output voltage and / or the output current serves as a detection signal for a parallel connection. Fig. 6 shows the operation as a sequence within a program flow in the source code of the µC. This can be a continuous part of the main program or a cyclically called auxiliary program. The process is started by triggering the analog-to-digital converter, with the scanning process of the analog-to-digital converter being carried out in parallel with the test sequence. By changing the setpoint Set_IsollCh1() below the current value of the load current, the current in the channel is regulated back. The voltage at the output is then either reduced or the current is taken over by a channel connected in parallel.A neural network can now be trained in such a way that it can detect changes both by the voltage change at the output, provided this occurs on both channels, and by the current change in the channels. After a certain test duration (Delay(ton)) of a few 100 µs to a few ms (or possibly longer, provided stable operation is not endangered), the setpoint of channel 1 is adjusted again, thus restoring normal operation. At the same time, the output voltage and / or the output current of both channels are monitored via the analog-to-digital converter. After the analog-to-digital converter is triggered, the first measured value of channel 1 is again acquired (Scan_Val_Ch1()) and written to a buffer (Val_Ch1 → Buf[ j ]). After the memory location (j++) is incremented, the measured value on channel 2 is acquired (Scan_Val_Ch2()) and written to the buffer (Val_Ch2 → Buf[ j ]).After the buffer's memory address (j++) has been incremented again, the entire process is repeated with the sample rate 202216491 16 ts (Delay(ts)) until the buffer is full. The measured values ​​are then sorted (Sort_Buf()) and standardized (Norm_Buf()) if necessary, after which the inference (Inference()) is performed. If a parallel connection of the channels is detected, they are configured accordingly and the associated parameters are adjusted (Channel_Conf()). When parallel connection detection is integrated into the processing of the monitoring device's main program, the presence of a parallel connection is not tested using a test sequence, but rather during program runtime, using the measured values ​​already determined. In the main loop of the monitoring device's program, the measured values ​​of the output variables are determined in order to react in the event of a fault such as the occurrence of overcurrents or a short circuit, etc.to be able to react accordingly. The measured values ​​are not discarded after each run, but written to the buffer. Once enough values ​​have been collected to form an input tensor for the neural network, an inference is performed, and if a parallel connection is detected, the channels are configured and parameterized accordingly. It should be noted that for this implementation, the entire process consisting of steps 1…5 must be run through with the necessary adjustments. It is also conceivable to detect the parallel connection of several devices, i.e. a group of electronic fuses. If the supplying power supply(s) vary their output voltage, this happens to the same extent at the inputs of electronic fuses connected in parallel. The input voltage of the electronic fuse is monitored anyway.With appropriately equipped device families, information can be exchanged via a communication bus. One of the devices could be defined as the master in the network, on which the inference is performed.

Claims

202216491 17 Patent claims / Patent claims 1. Method for detecting parallel connections of output channels in power supply devices, characterized in that a neural network implemented in a first digital computer of a monitoring device is provided for detecting the parallel connections, that various operating states are triggered in a power supply device to determine training data for the neural network and the associated voltage curves (U outCh1 , U outCh2) and / or current curves at the output channels are measured, that the training data ( ^^ ^^ℎ1[0] ^^ ^^ℎ2[1] ^^ ^^ℎ1[2] ^^ ^^ℎ2[3] … ^^ ^^ℎ1[ ^^ −3] ^^ ^^ℎ2[ ^^ − 2] ^^ ^^ℎ1[ ^^ −1] ^^ ^^ℎ2[ ^^]) are transmitted to a further digital computer by means of which the training of the neural network takes place and that the trained, ready-to-use neural network is implemented in the first digital computer of the monitoring device and is used to detect parallel connections.

2. Method according to claim 1, characterized in that the power supply device comprises an analog-digital converter which is connected on the input side to output channels of the power supply device and on the output side to the monitoring device. 3.Method according to claim 2, characterized in that, in order to determine training data for the neural network in a power supply device, different operating states with different load conditions are triggered with and without parallel connection, that the output voltages at the channels (U. outCh1 , U outCh2 ) are measured, digitized by means of an analog-digital converter and stored in a memory of the digital computer of the monitoring device as training data ( ^^ ^^ℎ1[0] ^^ ^^ℎ2[1] ^^ ^^ℎ1[2] ^^ ^^ℎ2[3] … ^^ ^^ℎ1[ ^^ −3] ^^ ^^ℎ2[ ^^ − 2] ^^ ^^ℎ1[ ^^ −1] ^^ ^^ℎ2[ ^^]). 202216491 18 4. The method according to claim 3, characterized in that the transfer of the digitized data from the analog-to-digital converter to a memory of the digital computer of the monitoring device takes place by means of direct memory access.

5. The method according to one of claims 1 to 4, characterized in that a multi-layer feedforward network is used as the neural network, which, in addition to an input and an output layer, also includes hidden layers.

6. The method according to one of claims 1 to 5, characterized in that the available training data is divided into core training, validation, and test data, that approximately 60% of the training data is used for the actual training, that 20% of the training data is used to validate the model, and a further 20% is used to test the network. 7.Method according to one of claims 1 to 5, characterized in that the determination of training data for the neural network is carried out by further hardware which is independent of the monitoring device.

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