Structure comprising a high thermal conductivity boron arsenide layer, and method of manufacture

Abstract

Structure (Struct) for microelectronic applications, extending along an extension plane, comprising a crystal layer (BAslay) of boron arsenide BAs having two dimensions each of at least 2 cm in, respectively, two directions normal to each other and within the extension plane.

Description

STRUCTURE COMPRISING A LAYER OF BORON ARSENIDE WITH HIGH THERMAL CONDUCTIVITY AND METHOD OF MANUFACTURING SAME TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates to a semiconductor crystal of high thermal conductivity which can be formed into a substrate for applications in the semiconductor industry, in particular in the thermal management of semiconductor devices formed on such a substrate. TECHNOLOGICAL BACKGROUND

[0002] Heat dissipation is a critical issue in the electronics and semiconductor industry. The high power and high component density of integrated circuits increase the temperature of the electronic devices they contain, leading to overheating and failure. To improve the reliability of these devices, it is necessary to quickly distribute and dissipate the heat generated in integrated circuits, an aspect of electronic devices known as thermal management.

[0003] Materials with high thermal conductivity are proposed to dissipate the heat produced by integrated circuits. In particular, aluminum nitride (AlN) and silicon carbide (SiC) can be mentioned, with respective thermal conductivities of approximately 285 W / mK and 300 W / mK, which are insufficient for satisfactory thermal management. Diamond has a high thermal conductivity of approximately 2000 W / mK but suffers from its high cost and its difficulty of implementation in integrated devices.

[0004] In this context, the thermal characteristics of boron arsenide (BAs) appeared attractive, with in particular a thermal conductivity theoretically evaluated at around 1400 W / mK and experimentally measured at around 1200 W / mK, therefore much higher than the materials conventionally used in the field, such as copper which has a thermal conductivity of around 400 W / mK.

[0005] However, boron arsenide is notoriously difficult to synthesize, and can only achieve its maximum thermal conductivity in a perfect crystalline form, free of defects and impurities that scatter phonons in the material, drastically reducing its thermal conductivity to just a few hundred watts per meter per kelvin. On this topic, see Fei Tian and Zhifeng Ren, “High Thermal Conductivity in Boron Arsenide: From Prediction to Reality,” in Angew. Chem. 2019, 131, 2-10.

[0006] US 2021 / 0035885 A1 describes an integrated circuit arranged in or on a BAs substrate and a method for crystal growth of a BAs single crystal. The BAs growth method uses a chemical vapor transport technique in the presence of a boron phosphide BP single crystal used as a crystal seed, at temperatures of about 1000°C for reaction periods in a sealed quartz tube extending over 5 weeks, repeated periods until high-quality BAs crystals with thermal conductivities of up to 1300 W / mK at room temperature are obtained.

[0007] Document US 2021 / 0269318 A1 describes a similar process, with a first chemical vapor transport reaction in a quartz tube using single crystals of BAs of micrometric sizes as crystal seeds, at temperatures of approximately 800°C for 2 weeks, followed by a second reaction similar to the first using the better quality crystals obtained following the first reaction as crystal seeds, to obtain millimetric sized BAs crystals.

[0008] We find that there is a strong need to provide boron arsenide in high quality crystalline form, preferably in single crystal form, suitable for use in the development of electronic circuits, and in particular for the thermal management of these circuits. More specifically, it is particularly desirable to provide boron arsenide in the form of a substrate or a layer suitable for transfer onto a substrate capable of accommodating a plurality of electronic circuits, such as a 6”, 8”, or 12” silicon wafer.

[0009] A first object of the invention is to provide a structure for microelectronic applications consisting at least in part of a crystalline layer of boron arsenide of chemical formula BAs, of zinc-blende structure. A second object is to provide a manufacturing method making it possible to obtain such a structure, capable of accommodating a plurality of electronic circuits or already equipped with such circuits.

[0010] With a view to achieving this aim, a first aspect of the invention is a structure for microelectronic applications, extending along an extension plane (xy), comprising a crystalline layer of boron arsenide BAs having two dimensions each of at least 2 cm along, respectively, two directions normal to each other and included in the extension plane.

[0011] An advantage of the structure according to the invention derives from the fact that it has a very high thermal conductivity while having a geometry suitable for being placed in intimate contact with a plurality of electronic circuits in a collective manufacturing process compatible with conventional manufacturing techniques in the microelectronics industry. Thus, this structure is able to efficiently evacuate the heat produced by electronic circuits integrated on this structure or the heat produced by electronic circuits with which this structure is placed in intimate contact, and therefore to improve the reliability of these electronic circuits.

[0012] According to additional non-limiting characteristics of the first aspect of the invention, considered individually or in any technically feasible combination:

[0013] - the crystalline layer of boron arsenide BAs can be monocrystalline;

[0014] - the structure may further comprise a layer of polytype 3C silicon carbide in direct contact with the layer of boron arsenide BAs;

[0015] - one of the crystalline boron arsenide BAs layer and the polytype 3C silicon carbide layer may comprise an implantation layer comprising hydrogen and / or helium;

[0016] - the structure may comprise a temporary support attached to the crystalline layer of boron arsenide BAs;

[0017] - the temporary support may be an adhesive thermal tape; and

[0018] - the structure may comprise a layer of stress material between the temporary support and the crystalline layer of boron arsenide BAs;

[0019] The invention extends to an electronic device integrating the structure. According to additional non-limiting characteristics of the electronic device according to the invention, considered individually or according to any technically feasible combination:

[0020] - the electronic device may comprise a semiconductor substrate integrating at least one electronic circuit juxtaposed with the crystalline layer of boron arsenide BAs;

[0021] - the crystalline layer of boron arsenide BAs can be assembled to the semiconductor substrate by direct bonding;

[0022] - the electronic device may comprise a transistor configured to comprise a channel forming in the crystalline layer of boron arsenide BAs.

[0023] A second aspect of the invention relates to the manufacture of a structure comprising a crystalline layer of boron arsenide of chemical formula BAs, so as to practically and economically produce layers of boron arsenide BAs of dimensions compatible with the industrial needs of the semiconductor industry.

[0024] To achieve this aim, a first aspect of the invention is a method of manufacturing a structure for microelectronic applications, comprising the steps of providing a 3C polytype silicon carbide layer having a flat surface and growing a crystalline layer of boron arsenide BAs on the silicon carbide layer, the layer (3C-SiC lay) of silicon carbide and the crystalline layer of boron arsenide BAs having two dimensions each of at least 2 cm along, respectively, two directions normal to each other and included in an extension plane parallel to the flat surface of the silicon carbide layer

[0025] The method according to the invention is advantageous in that it makes it possible to obtain large-sized layers of boron arsenide BAs, of the order of a centimeter or tens of centimeters, using techniques well mastered in the semiconductor industry. This method makes it possible to envisage standardized and mass-produced structures comprising layers of boron arsenide BAs capable of being integrated into an electronic circuit manufacturing process. The dimensions of the layers obtained make it possible to envisage the collective manufacturing of a plurality of semiconductor circuits on the same layer of boron arsenide BAs obtained according to the method of the invention.

[0026] According to additional non-limiting characteristics of the second aspect of the invention, considered individually or in any technically feasible combination:

[0027] - the method may further comprise forming a detachment layer and detaching, at the detachment layer, at least a portion of the crystalline layer of boron arsenide BAs from at least a portion of the layer of silicon carbide;

[0028] - the formation of the detachment layer may comprise a step of introducing a light species into the silicon carbide layer so as to define a weakening plane there before the step of growing the crystalline layer of boron arsenide BAs, then a heat treatment of fracturing the silicon carbide layer into two parts at the weakening plane;

[0029] - the step of growing the crystalline layer of boron arsenide BAs on the silicon carbide layer can be carried out at a temperature below 850°C;

[0030] - the crystalline layer of boron arsenide BAs can be grown to a thickness between 100 µm and 2000 µm;

[0031] - the formation of the detachment layer may comprise a step of introducing a light species into the crystalline layer of boron arsenide BAs so as to define a weakening plane there, then a heat treatment of fracture of the layer of boron arsenide BAs into two parts at the level of this weakening plane;

[0032] - the crystalline layer of boron arsenide BAs can be grown to a thickness between 0.5 µm and 5 µm;

[0033] - the formation of the detachment layer may comprise a step of covering the silicon carbide substrate with a layer (vdW lay ) of van der Waals material before the step of growing the crystalline layer of boron arsenide BAs;

[0034] - the layer of van der Waals material may comprise a layer of graphene; and

[0035] - the method may further comprise a step of detaching the boron arsenide BAs layer from the silicon carbide layer by traction applied to an intermediate support attached to the boron arsenide BAs layer.

[0036] The invention extends to a method of manufacturing a microelectronic circuit, comprising the method of manufacturing a structure described above, and further comprising the steps of assembling the crystalline layer of boron arsenide BAs to a semiconductor substrate on which a plurality of electronic circuits are integrated and a step of separating the electronic circuits from each other after the assembly step. BRIEF DESCRIPTION OF THE FIGURES

[0037] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0038] Larepresents a first structure comprising a crystalline layer of boron arsenide according to the invention and its manufacturing method;

[0039] Larepresents a second structure comprising a crystalline layer of boron arsenide according to the invention and its manufacturing method;

[0040] Larepresents a third structure comprising a crystalline layer of boron arsenide according to the invention and its manufacturing method;

[0041] Larepresents a fourth structure comprising a crystalline layer of boron arsenide according to the invention and its manufacturing method;

[0042] It represents a particular implementation of the structure of the;

[0043] Larepresents a fifth structure comprising a crystalline layer of boron arsenide according to the invention and its manufacturing method; and

[0044] It represents a first particular implementation of the structures of figures 1 to 6;

[0045] La represents a second particular implementation of the structures of figures 1 to 6; and

[0046] Illustrates the geometry of the boron arsenide crystalline layers in Figures 1-6. DETAILED DESCRIPTION OF THE INVENTION

[0047] As seen in the section on the technological background of the invention, a difficulty in growing crystals, and therefore crystalline layers, of boron arsenide BAs is that there is no substrate available that can serve as a seed for the crystalline growth of this material in the form of thin layers or wafers that can be used as such for the integration of electronic circuits. Indeed, until now, seeds of micrometric sizes are usually used, leading to the slow growth of crystals of uncontrolled geometries.

[0048] However, the applicant realized that a known but little-used material in the semiconductor industry has crystal parameters compatible with those of boron arsenide and can therefore serve as a basis for its crystal growth: this is the 3C polytype of silicon carbide, also called β-SiC or 3C-SiC, of ​​sphalerite type. It will be noted in particular that the lattice parameter of 3C-SiC is 4.3596 Å, sufficiently close to the lattice parameter of 4.777 Å of BAs to serve as a seed for crystal growth.

[0049] This material can, for example, be manufactured by growth on a monocrystalline silicon Si substrate with a (001) crystal orientation, typically in the form of generally circular wafers, in dimensions compatible with conventional processes in the semiconductor industry, for example 6 inches, 8 inches, 12 inches, or even 300 mm. Indeed, thanks to the good compatibility of 3C-SiC with Si, in particular with regard to their thermal expansion coefficients, respectively 3.8 10 -6 K -1 and 2.6 10 -6 K -1, it is easy to increase the substrate sizes of 3C-SiC / Si composite structures. As well known in the semiconductor industry, wafers can be made of disc-shaped insulating or semiconductor substrates, with two substantially parallel and flat opposite surfaces, as well as a notch or flat on the periphery, serving as a reference for the crystalline orientation of the substrate if necessary.

[0050] First embodiment

[0051] A first embodiment of the invention is illustrated by the.

[0052] In (A), it represents an intermediate structure Struct inter obtained by a process comprising the steps detailed below.

[0053] On a Sprt support, for example a monocrystalline silicon substrate of orientation (001), a 3C-SiC layer is grown using conventional heteroepitaxy methods. layof 3C-SiC up to a thickness between 0.3 and 5 µm, preferably between 0.5 and 1.5 µm for example by CVD or MOCVD, respectively Chemical Vapor Deposition and Metalorganic Chemical Vapor Deposition in English terminology.

[0054] On the 3C-SiC layer lay , we grow a BAs layer lay crystalline boron arsenide of chemical formula BAs by an atmospheric pressure MOCVD method using boron precursor gases such as diborane B2H6 or triethylboron B(C 2H5)3évaporé dans l’hydrogèneet d’arsine (AsH3)ou TertiaryButylArsine (TBAs) ou TrimethylArsenic (TMAs), de l’hydrogène étant utilisé comme gaz porteur à pression réduite et à une température de croissance comprise entre 450°C et 800°C, de préférence entre 500°C et 750°C.

[0055] Alternatively to the MOCVD or MBE method, it is possible to grow the BAs layer lay crystalline BAs on the 3C-SiC layer layby a CVT (Chemical Vapor Transport) method similar to that described by Tian and mentioned in the "Technological Background" section, an important difference being that the 3C-SiC layer is used as a seed. For this purpose, arsenic and boron in elemental form or boron arsenide BAs can be used as sources of arsenic and boron, possibly in combination, and, as a carrier agent, iodine I2, capable of reversibly forming boron triiodide BI3 with boron in elemental form B as with boron arsenide BAs, and similarly capable of forming arsenic triiodide AsI3. In addition to iodine I2, ammonium iodide NH4I and tellurium tetraiodide TeI4 can be used as carrier agents.Placing the 3C-SiC layer, the source and the carrier agent in a closed reactor with a temperature gradient leads to the growth of BAs in crystalline form on the 3C-SiC layer placed on the cold side of the reactor, and thus to a layer of BAs in crystalline form. Temperature ranges such as 613°C-850°C or 613°C-900°C, or 727°C-850°C or 727°C-900°C can be considered.

[0056] According to either the MOCVD method or the CVT method, a crystalline layer, preferably monocrystalline, of BAs of 300 to 1000 µm thickness, preferably 500 to 800 µm thickness, is grown. Such a thickness makes it possible to obtain a layer of BAs that will be self-supporting: it will not require the use of a temporary support for its manipulation.

[0057] An advantage of this method over prior art methods is the use of a 3C-SiC layer epitaxially grown on a silicon substrate as a seed, which makes it possible to obtain crystalline and preferably monocrystalline BAs layers of relatively large areas, for example by using a silicon wafer of 6 inches, 8 inches, 12 inches, or 150 mm, 200 mm or 300 mm in diameter respectively, as the surface for forming the 3C-SiC layer. It is thus possible to obtain crystalline layers of boron arsenide having a dimension of at least 2 cm in a given direction, and more, depending on the size of the substrate used, for example 4 inches, 6 inches, 8 inches, 12 inches, 100 mm, 150 mm, 200 mm or even 300 mm respectively if wafers of these diameters are used, the shape of the 3C-SiC layer not being limited to the circular shape typical of a semiconductor substrate wafer.The crystalline boron arsenide layers according to the invention may still have a flat surface having an area greater than 1 cm. 2 , preferably greater than 10 cm 2 , preferably still greater than 100 cm 2 The crystalline layers of boron arsenide according to the invention may also have a flat surface in which a circle with a diameter greater than 2 cm, preferably greater than 5 cm, preferably greater than 10 cm is inscribed.

[0058] At this stage it is desirable to be able to detach the BAs layer lay Sprt support, for example by implementing the Smart Cut process TM . To this end, prior to the growth of the BAs layer lay , we were able to prepare the 3C-SiCl layer ayby introducing one or more light species such as hydrogen or helium. This introduction may correspond to a hydrogen implantation, that is, an ion bombardment of hydrogen through a flat face of the 3C-SiCl layer ay . This face can optionally be provided with a protective layer formed before the ion bombardment, which can possibly be removed after it. In a manner known per se, and as illustrated in (A), the hydrogen ions H + implanted form an Imp implantation layer within the 3C-SiCl layer ay and aim to form a Frgl weakening plan SiC defined by this implantation layer and dividing the 3C-SiCl layer ay in two parts, one on the support side, the other on the BAsl layer side aywhich will be separated from the support at this weakening plane at a later stage. The implantation layer Imp is considered as a detachment layer of the BAsl layer ay with respect to its Sprt support and part of the 3C-SiCl layer ay .

[0059] The nature, the dose of the implanted species and the implantation energy are chosen according to the thickness of the layer that we wish to transfer. In the case of the 3C-SiCl layer ay , we can choose to implant a dose of hydrogen between 10 16 and 5.10 17at / cm² with an energy between 30 and 300 keV to define a weakening plane at a depth of the order of 200 to 2000 nm. When such a process is implemented, including the formation of a weakening plane, it is preferable to keep the growth temperature of the BAs layer below 850°C, for example between 613°C and 850°C or between 727°C and 850°C, so as to limit the risks of uncontrolled cleavage of the 3C-SiCl layer ay .

[0060] Illustrates in (B) a Struct structure comprising a BAs layer lay crystalline boron arsenide obtained following detachment from the Sprt support, and appearing in the form of a platelet.

[0061] The detachment step of the Sprt support is carried out by fracture at the level of the weakening plane Frgl SiC , which can be caused by application to the intermediate structure Struct interof a heat treatment in a temperature range between 850°C and 920°C, preferably between 900°C and 920°C, to allow the detachment of the BAs layer lay while avoiding a phase change from the BAs layer to a B layer 12 As6. Furthermore, it is preferable to carry out this heat treatment in an atmosphere with an arsenic overpressure (AsH3 , TBAs, TMAs) to avoid desorption of arsenic. As a replacement or in addition to heat treatment, this step may include the application of a blade or jet of gaseous or liquid fluid, or any other mechanical force at the embrittlement plane Frgl SiC .

[0062] As an alternative to implementing the Smart Cut process TMdetailed above, the step of detaching a part of the donor substrate can be replaced by a step of mechano-chemical thinning of the Sprt support and, possibly, of all or part of the 3C-SiC layer lay .

[0063] Whether the removal of part of the thickness of the donor substrate is achieved by thinning or by fracture, any type of finishing treatment can be applied to the Struct structure thus formed to conform the BAs layer. lay to specifications of thickness, thickness uniformity, roughness, crystal quality or any other type of specifications.

[0064] In this example where the Smart Cut process TM is used by fracturing the 3C-SiC layer, the Struct structure is made of the BAs layer laycrystalline boron arsenide and part of the 3C-SiC layer used for its growth as a crystal seed. It is of course possible to completely eliminate the 3C-SiC layer, for example by mechanical-chemical thinning, in which case the Struct structure consists only of the BAs layer lay crystalline boron arsenide.

[0065] The example taken for this embodiment consists of a layer of BAs with a thickness of between 200 and 1000 µm. Alternatively, this thickness could be between 0.5 and 2000 µm. A thick layer is self-supporting, a thin layer may have a certain flexibility during its handling, depending on its lateral dimensions, and may therefore need to be directly assembled to a definitive support or else to be assembled to a flexible or rigid auxiliary support temporarily, to facilitate its handling. Such a case will be addressed in the following embodiments, in particular the second and the fourth, which can be combined with this first embodiment.

[0066] The BAs layer laycrystalline boron arsenide layer finally obtained reproduces the shape and dimensions of the 3C-SiC layer which served as a seed for its growth, and which itself reproduces, where appropriate, the shape and dimensions of the silicon substrate which served as the basis for its formation. It is practical and appropriate to use a silicon wafer of substantially circular shape widely available from semiconductor material suppliers; but any type of support capable of growing the 3C-SiC layer is adequate, whether it is a portion of a silicon substrate or any other material of arbitrary shape, preferably extending in a plane so as to grow a BAs layer having a planar geometric configuration suitable for use in the semiconductor industry.For example, the layer obtained according to the invention can be characterized as forming a wafer, that is to say as an element having two dimensions in two directions normal to each other located in the same extension plane which are each at least ten times, preferably at least one hundred times, more preferably at least 1000 times and even more preferably at least 10000 times greater than a thickness of this element, thickness considered as a dimension of this element in a direction perpendicular to said plane or to said two directions normal to each other. This perpendicular direction is also perpendicular to a flat surface of the 3C-SiC layer and to a flat surface of its substrate, the silicon wafer in the present example. In addition, these two dimensions are each preferably greater than 2 cm, more preferably greater than 5 cm, even more preferably greater than 10 cm.

[0067] Illustrates this geometry, with a BAs layer lay crystalline boron arsenide obtained by any of the above embodiments, extending in an xy plane perpendicular to a z direction, the xy plane being defined by the x and y directions, the x, y and z directions forming a right-angled direct trihedron. In (a), illustrates the BAs layer lay view along the z direction, the xy plane being in the plane of the figure; in (b), illustrates a sectional view along the xz plane of the BAs layer lay passing through the axis AA' defined in (a).

[0068] Second embodiment

[0069] Illustrates a second embodiment of the invention, close to the first embodiment so that the description below will focus on the differences from the first embodiment, and reference may be made to the description of the first embodiment for the common elements.

[0070] In this mode, the BAs layer is thinner than in the first mode, with a thickness between 0.5 and 5 µm, preferably 1 to 2 µm. Furthermore, as shown in (A) of the, the fracture plane for separation of the BAs layer lay Sprt support is not defined in the 3C-SiC layer lay but in the BAs layer lay itself, it is then designated as Frgl BAs on the, so that the fracture, caused as explained in the first embodiment, occurs within the BAs layer lay and only a part BAs splt.lay of this layer will finally be preserved, as illustrated in (B) of the. The implantation layer Imp of the first embodiment is this time formed in the BAs layer lay , this time as a detachment layer of only one part (the BAs part splt.lay defined below) of the BAsl layer ay vis-à-vis the BAs layer lay of the support.

[0071] In this embodiment, the BAs layer layis assembled on the rear face of a semiconductor substrate Sub on a front face of which a plurality of electronic circuits Crct is integrated, before the step of detaching the support Sprt, which makes it possible to avoid the difficulties linked to the handling of a layer of this thickness, generally flexible and fragile. These circuits are intended to be separated from each other during a step called "dicing" consisting of separating from each other different electronic circuits formed on a common support. When mentioning the integration of an electronic circuit on one face of a semiconductor substrate, this can mean that the electronic circuit comprises a transistor whose channel is formed in the volume of the semiconductor substrate, which can consist of a wafer of semiconductor material or a layer of semiconductor material supported by a support, as in the case of an SOI type structure.

[0072] Preferably, before the assembly step, the semiconductor substrate Sub on which the circuits are integrated is thinned by its rear face, for example to less than 300 µm, preferably 200 µm, so as to promote heat dissipation. The semiconductor substrate may be made of any semiconductor material usually used in the semiconductor industry, such as a silicon wafer, possibly with a (100) crystal orientation. In the case where the circuits are manufactured on a SOI (Silicon on Insulator) type substrate comprising a semiconductor layer supported by a base substrate via an electrically insulating layer, it is also possible to chemically eliminate the entire base substrate and selectively stop the chemical attack on the electrically insulating layer.

[0073] We can proceed to the assembly of the BAs layer layto the substrate Sub of the electronic circuits Crct by means of an adhesive substance which is a good heat conductor, comprising for example silver. Preferably, an assembly can be carried out by means of direct bonding by placing in intimate contact at an interface between one face of the BAs layer and the rear face of the semiconducting substrate Sub. First, the free face of the BAs layer lay and the rear face of the substrate Sub can be prepared so as to allow direct bonding by intimate contact, by molecular adhesion for example. It is thus possible to form a dielectric layer such as silicon dioxide (not shown here) on one or other of the faces to be contacted of the circuit Crct and the layer BAs lay , or both, to facilitate assembly.

[0074] As is well known, during a molecular adhesion process, the surfaces to be adhered to each other (one and / or the other possibly being covered with a dielectric layer), perfectly clean, flat and smooth, are brought into intimate contact to promote the development of molecular bonds, for example van der Waals or covalent bonds. The assembly of the two bodies is then obtained without the use of an adhesive. The assembly process may include the application of a low-temperature heat treatment (for example between 50°C and 300°C, typically 100°C) to strengthen the bonding energy. Following the adhesion and the fracture step at the embrittlement plane, a BAs part splt.lay of the BAs layer lay remains attached to the Crct circuit, as illustrated in (B) of the.

[0075] An advantage of using direct adhesion is that it avoids the formation of an adhesive layer between the Crct circuit and the BAs layer. splt.lay , less good conductor than the latter. If this solution is not practicable, for technical or economic reasons, an adhesive layer can of course be implemented even if it is not the most optimal technical solution from the point of view of thermal exchanges.

[0076] In this embodiment, alternatively to assembling the BAs layer on an electronic circuit, it is possible to assemble the BAs layer to a rigid support such as a wafer of semiconductor material or to a flexible support such as an adhesive thermal tape, as will be seen in the case of the fourth embodiment illustrated by the. It is also possible to assemble the BAs layer to the front face of the semiconductor substrate rather than on its back face.

[0077] The example taken for this embodiment consists of a layer of BAs with a thickness of between 0.5 and 5 µm. Alternatively, this thickness could be between 0.5 and 2 µm.

[0078] Third embodiment

[0079] Illustrates a third embodiment of forming a Struct structure in the form of a BAs wafer. Unlike the first and second embodiments, this third embodiment is based on 2DLT technology, or 2D material-based Layer Transfer in English terminology. This is a technology developed to produce elements such as monocrystalline layers, thin films or even more complex structures, in a form detached from the substrate on which they were formed. To this end, a material called a 2D van der Waals material (2D because essentially two-dimensional) is interposed between the element in question and its substrate, allowing for subsequent detachment. In this case, the van der Waals material is used to separate a BAs layer from a substrate on which it was grown.For elements in common between the embodiments, reference may be made to the explanations given for the first embodiment. In particular, the growth methods described in the first embodiment are applicable and reference may be made to this first embodiment for these aspects of the present embodiment.

[0080] As illustrated in (A) of the, a layer of so-called van der Waals material is formed on a 3C-SiC layer layof 3C-SiC carried by a Sprt support. A van der Waals material is defined as a material consisting of atoms strongly bonded to each other by covalent or ionic bonds only in the plane of formation of the material, without strong bonds perpendicular to this plane. From a practical point of view, one or more layers of graphene or 2D material, preferably a monolayer, can thus be used to remove a structure formed on top of the graphene layer from the support located below it, as detailed for example by Celesta Chang et al. in “Remote Epitaxy”, Nature Methods, June 2022, or in the document WO 2017 / 044577 A1.

[0081] The intermediate structure Struct inter illustrated in (A) of the is formed to comprise, in this order, a Sprt support, such as monocrystalline silicon, a 3C-SiC layer lay of 3C-SiC, a vdW layer layvan der Waals material such as a graphene layer, a BAs layer lay of BaS, and temporary Temp support Sprt such as adhesive thermal tape. Optionally, a layer of Stres lay of material involving high mechanical stress such as nickel or copper facilitating subsequent detachment at the level of the vdW layer lay can be interposed between the layer of BAs and the temporary support, as illustrated by the. We consider here a layer of BAs sufficiently thick to be self-supporting, of thickness similar to that of the layer of the first embodiment.

[0082] The graphene layer can be obtained for example by a wet transfer method of a layer obtained by CVD on a catalytic metal substrate or by graphitic transformation of the SiC layer by sublimation of silicon. It is noted that the crystal pattern of the 3C-SiC layer is capable of guiding the crystal growth of the BAs layer through the graphene layer when it is sufficiently thin, preferably 1 to less than 10, preferably 1 to 3 graphene sheets.

[0083] Illustrates in (B) the result of the simple traction of the temporary support: the BAs layer lay was detached from the support at the vdW layer lay then the temporary support was detached by applying heat if it is an adhesive thermal tape, and the Stres layer lay has been chemically removed in a conventional manner. The self-supporting layer BAs laythen forms the Struct structure by itself. It is possible to leave the Stres layer lay on the BAs layer lay , depending on the applications targeted by the practitioner. We consider the vdW layer lay as a detachment layer of the BAsl layer ay of its Sprt support and the 3C-SiC layer lay of 3C-SiC.

[0084] Fourth embodiment

[0085] Illustrates a fourth embodiment of the invention, close to the third embodiment so that the description below will focus on the differences from the third embodiment, and reference may be made to the description of the third embodiment for the common elements.

[0086] Unlike the third mode, only a reduced thickness of BAs, between 0.5 and 5 µm, preferably 1 to 2 µm, is grown on the graphene layer, so that the BAs layer layis not self-supporting, or is too fragile to be easily handled alone, without auxiliary support.

[0087] In this situation, after detachment of the BAs layer lay at the vdW layer level lay , we do not proceed to detach the temporary Temp support Sprt and the elimination of the Stres layer lay , but we keep the BAs layer lay attached to the temporary Temp support Sprt until its final implementation. In this embodiment, the BAs layer lay of BAs is supported by the temporary Temp support Sprt .

[0088] Fifth embodiment

[0089] Illustrates an implementation of the BAs layer lay assembled to a temporary support as illustrated in (B) of the. This embodiment can be described as a combination of the second embodiment for the aspects related to the assembly of the BAs layer layto electronic circuits C rct with the fourth embodiment for the aspects relating to obtaining a layer of BAs attached to a temporary support and the third embodiment for the aspect relating to the removal of the temporary support and the Stres layer lay .

[0090] In other words, one or the other of the assembly techniques mentioned in the second embodiment can be applied to assemble the BAs layer lay of the fourth embodiment to one or more electronic circuits Crct integrated into a semiconductor substrate Sub, contacting the Bas layer lay being done while this layer is manipulated via its temporary support Temp Sprt as illustrated in (A) of the, this support and the Stres layer laybeing removed after assembly to the electronic circuit, so as to obtain the device Dev illustrated in (B) of the. Unlike the configuration illustrated in (B) of the, the BAs layer lay is assembled on the front face of the semiconductor substrate Sub, that is to say on the face on which the electronic circuits Crct are integrated. As for the second embodiment, after assembly, a step of separating the electronic circuits from each other can be carried out during an operation known in the microelectronics industry as "dicing" in English terminology.

[0091] Sixth embodiment

[0092] Illustrates a sixth embodiment of the invention, close to the third and fourth embodiments illustrated by Figures 3 and 4, but with the particularity that instead of comprising only a single layer of BAs, the intermediate structure comprises a stack of layers of BAs, each separated from the others by a layer of van der Waals material such as graphene. Reference may be made to these embodiments for the common elements.

[0093] Illustrates in (A) an intermediate structure Struct inter with n BA layers lay-x of BAs and n vdW layers lay-x of van der Waals material, x taking an integer value from 1 to n increasing with the distance from the support Sprt, the BAs layer lay-n , the furthest from the Sprt support, being formed on a vdW layer lay-n of van der Waals material and provided with a Stres layer lay-n of stressful material on which a temporary support is attached TempSprt .

[0094] As in the third embodiment, the BAs layer can be separated lay-n of the intermediate structure. Subsequently, the layer of van der Waals material vdWlay-n is removed, then the BAs layer is deposited on lay-(n-1) then exposed a new layer of stress material and a new temporary support is attached to it. The process is then repeated until the n layers of BAs have been removed from the intermediate structure and form as many BA structures in the form of platelets. This process is advantageous in that it allows greater productivity during the manufacture of BA platelets.

[0095] As illustrated in (B) of the, the BA layers can be separated from their respective temporary supports and cleaned of their stressful material layers. This option is suitable when the BA layers lay-xare thick enough to be self-supporting. Alternatively, when the layers are too thin to be easily handled, they can be kept attached to their temporary support, as in the case illustrated in (B) of the.

[0096] Seventh embodiment

[0097] An application of the BA layers described in the preceding claims is in the heat dissipation of integrated electronic circuits. Conventionally, an integrated electronic circuit is equipped with a heat sink or heat sink, possibly provided with heat dissipation fins, in order to limit the heating of this electronic circuit during its operation by dissipating the heat that it produces.

[0098] In the context of the present invention, a BAs layer can be interposed between the electronic circuit and the heat sink. layof BAs obtained according to any of the embodiments described above, as illustrated by the. The advantage is to allow the evacuation of heat as close as possible to the circuit and to limit the appearance of hot spots, heat islands located on the surface of the circuit. The high thermal conductivity of the BAs layer and its proximity to the circuit considerably improve the efficiency of heat evacuation from an electronic circuit compared to known solutions.

[0099] The BAs layer laycan be located on the back face or the front face of an integrated circuit Chip and be fixed there by direct bonding (without adding a layer of intermediate adhesive material) or by means of an adhesive, preferably a good heat conductor. Direct bonding is preferable in order to ensure intimate contact between the BAs and the electronic circuit and to promote heat exchange between the circuit and the BAs layer. An adhesive, even a relatively good heat conductor, will represent a thermal barrier taken in comparison with the crystalline layer of BAs according to the invention, a better heat conductor.

[0100] Eighth embodiment

[0101] The application examples given so far consist of taking advantage of the high thermal conductivity of crystalline BAs to assist in the removal of heat produced by an integrated circuit onto another semiconductor substrate such as silicon.

[0102] The present embodiment consists in taking advantage of the semiconductor characteristics of BAs, which is a III-V type semiconductor, by integrating therein a device Dev comprising an electronic circuit comprising at least one transistor configured so as to comprise a channel forming in a layer of BAs formed according to any of the methods described above, as illustrated by thewith a transistor Tr integrated on a BAs layer lay of BAs according to any of the preceding embodiments.

[0103] The transistor Tr comprises a source S, a drain D and a gate G which can be formed from metals, two doping Dop zones surrounding the gate, formed superficially in the volume of the BAs layer lay and in electrical contact respectively with the source and drain, and a channel forming zone Ch located between the two doping zones, superficially in the volume of the BAs layer lay, a Diel layer of dielectric insulating the gate from this channel forming area.

[0104] This provides optimal heat dissipation at any hot spots in the circuit, increasing its reliability and limiting the need for elements specifically dedicated to heat dissipation, simplifying the design and manufacturing of such circuits compared to those based on other semiconductors.

[0105] The figures in this document are not necessarily to scale. Some features and components may be shown exaggerated in relation to other components or in a somewhat schematic form, and some details of conventional items may not be shown in the interest of clarity and conciseness.

[0106] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Structure for microelectronic applications, extending along an extension plane (xy), comprising a layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs having two dimensions each of at least 2 cm according to, respectively, two directions (x, y) normal to each other and included in the extension plane (xy). Structure according to claim 1, wherein the layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs is monocrystalline. Structure according to claim 1 or 2, further comprising a (3C-SiC) layer lay , 3C-SiC splt.lay ) of 3C polytype silicon carbide in direct contact with the layer (BAs lay , Down splt.lay ) of boron arsenide BAs. Structure according to claim 3, wherein one of the layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs and the layer (3C-SiC lay , 3C-SiC splt.lay) of polytype 3C silicon carbide comprises an implantation layer (Imp) comprising hydrogen and / or helium. Structure according to any one of claims 1 to 3, comprising a temporary support (Temp Sprt ) attached to the layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs. Structure according to claim 5, the temporary support (Temp Sprt ) being an adhesive thermal tape. Structure according to claim 5 or 6, comprising a layer (Stres lay ) of stressful material between the support (Temp sprt ) temporary and the layer (BAs lay ) crystalline boron arsenide BAs. Electronic device (Dev) integrating the structure according to any one of claims 1 to 3. Electronic device (Dev) according to claim 8, comprising a semiconductor substrate (Sub) integrating at least one electronic circuit (Crct) juxtaposed with the layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs. Electronic device according to claim 9, wherein the layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs is assembled to the semiconductor substrate (Sub) by direct bonding. Electronic device (Dev) according to claim 8, comprising a transistor (Tr) configured to comprise a channel forming in the layer (BAs lay , Down splt.lay ) crystalline boron arsenide BAs. Method of manufacturing a structure for microelectronic applications, comprising the steps of:- providing a layer (3C-SiC lay ) of polytype 3C silicon carbide having a flat surface; and- growing a crystalline layer of boron arsenide BAs (BAslay ) on the layer (3C-SiC lay ) of silicon carbide, the layer (3C-SiC lay ) of silicon carbide and the crystalline layer of boron arsenide BAs (BAs lay ) having two dimensions each of at least 2 cm along, respectively, two directions normal to each other and included in an extension plane parallel to the flat surface of the silicon carbide layer. The method of claim 12, further comprising forming a release layer (Imp, vdW lay ) and the detachment, at the level of the detachment layer, of at least one part (BAs lay , Down splt.lay ) of the crystalline layer of boron arsenide BAs (BAs lay ) with respect to at least part of the layer (3C-SiC lay ) of silicon carbide. Manufacturing method according to claim 13, wherein the formation of the detachment layer (Imp) comprises a step of introducing a light species into the silicon carbide layer so as to define a plane (Frgl SiC ) of embrittlement before the growth step of the boron arsenide crystalline layer, then a heat treatment of fracture of the silicon carbide layer into two parts at the embrittlement plane. The manufacturing method of claim 14, wherein the step of growing the crystalline layer of boron arsenide BAs (BAs lay ) on the layer (3C-SiC lay ) of silicon carbide is implemented at a temperature below 850°C. Manufacturing method according to claim 14 or 15, in which the crystalline layer of boron arsenide BAs is grown to a thickness of between 100 µm and 2000 µm. Manufacturing method according to claim 13, wherein the formation of the detachment layer (Imp) comprises a step of introducing a light species into the crystalline layer of boron arsenide BAs so as to define a plane (Frgl BAs ) of embrittlement, then a heat treatment of fracture of the layer of boron arsenide into two parts at the level of this embrittlement plane. Manufacturing method according to claim 17, wherein the crystalline layer of boron arsenide BAs is grown to a thickness of between 0.5 µm and 5 µm. The manufacturing method of claim 13, wherein forming the release layer comprises a step of coating the silicon carbide substrate with a (vdW lay ) of van der Waals material before the step of growing the crystalline layer of boron arsenide BAs. The method of claim 19 wherein the layer of van der Waals material comprises a layer of graphene. The method of claim 19 or 20, further comprising a step of detaching the boron arsenide BAs layer (BAs lay ) of the layer (3C-SiC lay ) of silicon carbide by traction applied to an intermediate support (Temp Sprt ) attached to the boron arsenide layer. A method of manufacturing a microelectronic circuit, comprising the method of manufacturing a structure for microelectronic applications according to claim 12, and further comprising the steps of:- assembling the crystalline layer of boron arsenide BAs to a semiconductor substrate (Sub) on which a plurality of electronic circuits (Crct) are integrated; and- a step of separating the electronic circuits from each other after the assembly step.

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