Radio frequency switch and reconfigurable surface

Abstract

The invention relates to a radio frequency switch (100) for a reconfigurable surface (200). The radio frequency switch (100) comprises a first memory latch (110) configured to receive a data bit, and output the data bit to a gate (136) of a FET (130) which comprises a drain (132) configured to be connected to a first connection point (212) of an antenna unit cell (210) of the reconfigurable surface (200), and a source (134) configured to be connected to a second connection point (214) of the antenna unit cell (210). Thus, the FET (130) is configured to be in a closed state when the data bit has a first value and in an open state when the data bit has a second value different to the first value thereby acting as a switch. Furthermore, embodiments of the invention also relate to a reconfigurable surface comprising such a radio frequency switch.

Description

[0001] RADIO FREQUENCY SWITCH AND RECONFIGURABLE SURFACE

[0002] TECHNICAL FIELD

[0003] Embodiments of invention relate to a radio frequency switch for a reconfigurable surface. Furthermore, embodiments of the invention also relate to a reconfigurable surface comprising such a radio frequency switch.

[0004] BACKGROUND

[0005] In order to meet the demand for higher data rates in communication systems operators will have to expand mobile data networks into the mm-Wave bands, which offer higher bandwidths compared to the saturated lower frequency bands. In order to overcome the limitations of shadowing typically associated with these higher frequencies operators will have three main options to increase coverage: densification of the macro grid; deployment of mmWave ultra dense networks; and the use of passive or active repeater technology.

[0006] A reconfigurable intelligent surface (RIS) is a passive repeater technology which is a unification of a wave reflector panel and beamforming array. It shapes the electromagnetic (EM) wave reflection to open paths from a base station (BS) to user equipments (UE) which otherwise would be in shadowed positions. Adding RIS devices to the communication network is an attractive path to increase coverage with a low power consumption. RIS is a green technology, and it allows operators to stay on site with existing BS installations.

[0007] SUMMARY

[0008] An objective of embodiments of the invention is to provide a solution which mitigates or solves the drawbacks and problems of conventional solutions.

[0009] Another objective of embodiments of the invention is to provide a RF switch solution consuming less power compared to conventional solutions.

[0010] The above and further objectives are solved by the subject matter of the independent claims. Further embodiments of the invention can be found in the dependent claims.

[0011] According to a first aspect of the invention, the above mentioned and other objectives are achieved with a radio frequency switch for a reconfigurable surface, the radio frequency switch comprising: a first memory latch comprising: a clock input configured to receive a clock signal, a data input configured to receive a data bit, and a data output configured to output the data bit; and a first field effect transistor, FET, comprising: a drain configured to be connected to a first connection point of an antenna unit cell of the reconfigurable surface, a source configured to be connected to a second connection point of the antenna unit cell, and a gate connected to the data output of the first memory latch, wherein the first FET is configured to be in a closed state when the data bit has a first value and in an open state when the data bit has a second value different to the first value thereby acting as a switch.

[0012] An advantage of the radio frequency switch according to the first aspect is that the steadystate power consumption of a RF switch based on FET is lower compared to diode-based RF switches thus e.g., being suitable for reconfigurable surface applications having strict power requirements. Further advantages that come with the addition of a memory latch are simplified control of reconfigurable surfaces with fewer output drive circuits for the control arrangement, and a reduced routing complexity for reconfigurable surface printed circuit board (PCB).

[0013] In an implementation form of a radio frequency switch according to the first aspect, the first memory latch and the first FET are arranged on a common single chip.

[0014] An advantage with this implementation form is that the integration of FET(s) and memory latch(es) on to the same chip allows for a cost-efficient high-volume manufacturing of the chip devices. Further, such common chip has a built-in resistance to temperature variations through the logic-level threshold design. Also, when the memory latch is localized together with the FET switch at the antenna unit cell row / column addressing is possible thereby providing simplified control circuits and a less complex PCB. Further, the co-localization of FET and memory latch on the same chip enables the smallest possible component size for the wanted functionality. It is of importance for the antenna performance, such as to minimize reflection loss and to maximize bandwidth, that any component assembled into the antenna unit cell is physically small compared to the antenna element dimensions. Thus, an advantage of the integrated RF switch is to make the reconfigurable surface perform better than if the functions were split on to several separate chips.

[0015] In an implementation form of a radio frequency switch according to the first aspect, the first FET is a N-channel FET.

[0016] An advantage with this implementation form is that the electron mobility of N-channel FETs is higher than for P-channel FETs. A switch can thus be made with lower on-state resistance for RF signals when using the N-channel FET. This will lead to lower reflection loss for the reconfigurable surface.

[0017] In an implementation form of a radio frequency switch according to the first aspect, the source of the first FET is connected to a common reference ground via a first resistance.

[0018] An advantage with this implementation form is that is that the control of the FET from the logic output of the memory latch becomes reliable as the resistor establishes a close to zero potential for the source terminal of the first FET. Due to the high gate input resistance, the value of the resistor can be made high as to become practically invisible for the RF circuit to be switched.

[0019] In an implementation form of a radio frequency switch according to the first aspect, the clock input of the first memory latch is configured to be connected to a column line of the reconfigurable surface, and the data input of the first memory latch is configured to be connected to a row line of the reconfigurable surface, or vice versa.

[0020] An advantage with this implementation form is that the row / column addressing of the RF switch is enabled. A particular switch on the array can be attributed to a pair of coordinates corresponding to a row and a column number. This greatly reduces the number of electrical control line outputs that the control arrangement of the reconfigurable surface needs. The clock input of the memory latch is used to transfer a data bit presented on the row line into the memory latch. While no other columns on the array receive the clock signal, the RF switches on this row in the other columns do not respond to the presented data bit.

[0021] In an implementation form of a radio frequency switch according to the first aspect, the radio frequency switch further comprises: a second memory latch comprising: a clock input configured to receive a common control signal for the antenna unit cells of the reconfigurable surface, a data input connected to the data output of the first memory latch, and a data output connected to the gate of the first FET, wherein the second memory latch is configured to transfer a data bit from the data input to the data output when receiving the common control signal.

[0022] An advantage with this implementation form is that the data bits that represents a new beamforming setting, i.e. , a new code word, can be uploaded to the antenna array in advance of the moment of a beamforming change. That is to say that the transition time for changing the beamforming setting from one setting to another, as experienced by the radio signal to be reflected, can be reduced significantly. The transition time represents a blurred and undefined beamforming and is thus equivalent to a communication outage. It is a desire to minimize such outage. With the addition of the second memory latch, the new code word is first uploaded to the first memory latches while the present code word is being held by the second memory latches. Once all first memory latches have received their new code data bit, the change from the present array beamforming setting to the new setting is made by toggling the common control signal one cycle. Instead of the array getting an outage period of a number of clock cycles equal to its number of columns, the outage is now reduced to less than one clock cycle.

[0023] In an implementation form of a radio frequency switch according to the first aspect, the radio frequency switch further comprises: a third memory latch comprising: a clock input configured to receive the clock signal, a data input connected to the data output of the first memory latch, and a data output; a fourth memory latch comprising: a clock input configured to receive a common control signal for the antenna unit cells of the reconfigurable surface, a data input connected to the data output of the third memory latch, a data output, wherein the fourth memory latch is configured to transfer a data bit from the data input to the data output when receiving the common control signal; and a second FET comprising: a drain configured to be connected to a third connection point of the antenna unit cell, a source configured to be connected to a fourth connection point of the antenna unit cell, and a gate connected to the data output of the fourth memory latch.

[0024] An advantage with this implementation form is that the antenna element reconfigurability can be further optimized if more than one RF switch is provided. By having two memory switches, connected to different sections of the antenna layout pattern, increased control is enabled of the RF current patterns which is the basis for the antenna radiation properties and performance. This implementation form allows the RF switches to be controlled by independent data bits with the result that the RF switches can be set on or off independently from each other. An example that exploits this advantage is to separately control two different, orthogonal polarizations of the incident RF wave to beamform their reflections in different directions. Furthermore, an advantage coming from the second and fourth memory latches in this implementation form is that a new code word can be uploaded to the array in advance of the moment of change of beamforming setting. This reduces transition time for changing the beamforming setting from one setting to another setting and minimizes the outage of the radio signal. In an implementation form of a radio frequency switch according to the first aspect, the radio frequency switch further comprises: a third memory latch comprising: a clock input configured to receive the clock signal, a data input connected to the data output of the first memory latch, and a data output; a fourth memory latch comprising: a clock input configured to receive a common control signal for the antenna unit cells of the reconfigurable surface, a data input connected to the data output of the third memory latch, a data output, wherein the fourth memory latch is configured to transfer a data bit from the data input to the data output when receiving the common control signal; and a second FET comprising: a drain configured to be connected to the source of the first FET, a source configured to be connected to the second connection point of the antenna unit cell, and a gate connected to the data output of the second memory latch; wherein the first FET has a first gate width and the second FET has a second gate width different to the first gate width.

[0025] An advantage with this implementation form is that it exploits independent control of two internally series-connected switches to present not only two states, on and off, but also intermediate impedance states between the two external connection terminals. These intermediate states appear as different magnitudes of capacitance and the effective result is a stepped capacitor with a low resistance as the end state. With appropriate RF design methods, this stepped capacitance can be used to create a higher number of quantized phase states for the antenna unit cell reflection coefficient than just two. Having several phase states for the unit cell with finer resolution is advantageous to improve the radiation pattern shape of the reconfigurable surface and to increase the sidelobe suppression. The capacitance of the intermediate states is controlled by selection of the FET device sizes, i.e., the gate width. Furthermore, an advantage coming from the second and fourth memory latches in this implementation is that a new beamforming setting can be uploaded to the array in advance of the moment of change of beamforming setting. This reduces transition time for changing the beamforming setting from one setting to another setting and minimizes the outage of the radio signal.

[0026] In an implementation form of a radio frequency switch according to the first aspect, the radio frequency switch further comprises: a second memory latch comprising: a clock input configured to receive the clock signal, a data input connected to the data output of the first memory latch, and a data output; and a second FET comprising: a drain configured to be connected to a third connection point of the antenna unit cell, a source configured to be connected to a fourth connection point of the antenna unit cell, and a gate connected to the data output of the second memory latch.

[0027] This is a simpler form of implementation to achieve the advantages previously described from having two separate, individually controlled switches. This implementation form is suited when speed of operation of the reconfigurable surface is not a priority but rather when low power consumption is prioritized. Furthermore, an advantage is that the RF switch needs one less connection terminal which can help to minimize size, cost and PCB routing.

[0028] In an implementation form of a radio frequency switch according to the first aspect, the radio frequency switch further comprises: a second memory latch comprising: a clock input configured to receive the clock signal, a data input connected to the data output of the first memory latch, and a data output; and a second FET comprising: a drain configured to be connected to the source of the first FET, a source configured to be connected to the second connection point of the antenna unit cell, and a gate connected to the data output of the second memory latch; wherein the first FET has a first gate width and the second FET has a second gate width different to the first gate width.

[0029] This is a simpler form of implementation to achieve the advantages previously described from having two separately controlled, internally series-connected switches. It has the same advantages related to the higher number of phase states for the antenna, which come from the multiple impedance states of the FET series pair. This implementation form is advantageous when low power consumption is prioritized. Further advantages are that the RF switch component needs one less connection terminal which can help to minimize size, cost and PCB routing.

[0030] In an implementation form of a radio frequency switch according to the first aspect, the source of the second FET is connected to a common reference ground via a second resistance.

[0031] An advantage with this implementation form is that the control of the second FET switch from the logic output of the memory latch is made to have reliable logic input transition levels, as the resistor establishes a close to zero potential for the source terminal of the second FET. The resistor ensures this also when the first FET is in the off state. Due to the high gate input resistance, the value of the resistor can be made high as to become practically invisible for the RF circuit to be switched. In an implementation form of a radio frequency switch according to the first aspect, the radio frequency is in the centimeter or millimeter wavelength range.

[0032] According to a second aspect of the invention, the above mentioned and other objectives are achieved with a reconfigurable surface comprising: a plurality of antenna unit cells, wherein each antenna unit cell comprises a radio frequency switch according to any one of the preceding claims connected between connection points of the antenna unit cell; and a control arrangement connected to the plurality of antenna unit cells via a plurality of column lines and a plurality of row lines and configured to control the radio frequency switches of the plurality of antenna unit cells by providing a clock signal on the row lines and a plurality of data bits on the column lines, or vice versa.

[0033] An advantage of the reconfigurable surface according to the second aspect is that the RF switched according to the first aspect employed are suitable for reconfigurable surface applications having strict power requirements. Further advantages that come with the addition of a memory latches are simplified control of the reconfigurable surface with fewer output drive circuits for the control arrangement, and a reduced routing complexity for reconfigurable surface PCB.

[0034] In an implementation form of a reconfigurable surface according to the second aspect, the control arrangement further is connected to the plurality of antenna unit cells via a common control line and configured to transfer data bits at the data inputs of the memory latches to the outputs of the memory latches by providing a common control signal.

[0035] An advantage with this implementation form is that when the control arrangement uses the common control line to clock the memory latches in all RF switches on the array that are connected to it, the data bits that represents a new beamforming setting, i.e. , a code word, can be uploaded to the array in advance of the moment of change of beamforming setting. This significantly reduces the transition time for changing the beamforming setting from one setting to another setting, as experienced by the radio signal. As previously mentioned, the transition time represents a blurred and undefined beamforming and is thus equivalent to a communication outage. It is a desire to minimize such outage. Once all first latches have received their new code data bit, the change from the present array beamforming setting to the new setting is made by toggling the common control signal one cycle. Instead of the array getting an outage period of a number of clock cycles equal to its number of columns, the outage is now reduced to less than one clock cycle.

[0036] In an implementation form of a reconfigurable surface according to the second aspect, the plurality of data bits represents a codeword of a beamforming scheme.

[0037] Further applications and advantages of embodiments of the invention will be apparent from the following detailed description.

[0038] BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The appended drawings are intended to clarify and explain different embodiments of the invention, in which:

[0040] - Fig. 1 shows a RF switch comprising one memory latch and one FET according to embodiments of the invention;

[0041] - Fig. 2 shows a physical layout of a chip device comprising a RF switch as shown in Fig. 1 ;

[0042] - Fig. 3 shows a reconfigurable surface comprising RF switches as shown in Fig. 1 ;

[0043] - Fig. 4 illustrates alteration of phases of an exemplary unit cell of a reconfigurable surface;

[0044] - Fig. 5 illustrates a unit cell connected onto a reconfigurable surface multilayer PCB;

[0045] - Fig. 6 shows an implementation example of a device comprising a reconfigurable surface;

[0046] - Fig. 7 illustrates reflective and transmissive properties of a reconfigurable surface according to embodiments of the invention;

[0047] - Fig. 8 shows a RF switch comprising two memory latches according to embodiments of the invention;

[0048] - Fig. 9 shows a reconfigurable surface comprising RF switches as shown in Fig. 8;

[0049] - Fig. 10 shows a RF switch comprising two memory latches and two FETs;

[0050] - Fig. 11 shows a physical layout of a chip device comprising the RF switch as shown in Fig. 8;

[0051] - Fig. 12 shows a RF switch comprising four memory latches and two FETs according to embodiments of the invention;

[0052] - Fig. 13 shows a RF switch comprising two memory latches and two FETs according to embodiments of the invention;

[0053] - Fig. 14 shows an equivalent model for a single FET acting as a switch; - Fig. 15 shows possible device selection and equivalent model schematics for a series FET pair acting as a combined switch and stepped varactor;

[0054] - Fig. 16 shows a RF switch comprising four memory latches and two FETs according to embodiments of the invention;

[0055] - Fig. 17 shows a physical layout of a chip device according to embodiments of the invention; and

[0056] - Fig. 18a and 18b illustrate the use of a reconfigurable surface in an exemplary communication scenario.

[0057] DETAILED DESCRIPTION

[0058] As aforementioned, the RIS uses passive radio frequency (RF) technology without signal amplification for its operation. Compared to the active repeater the RIS has an advantage of being able to operate without external connection to a power grid supplying power but may instead being provided with power from a battery and / or with support from solar panels. However, for this to be possible both the RIS control system and the electronics for reconfiguration of the RIS need to be designed for smallest possible power consumption. Thus, it is herein disclosed a RF switch fulfilling strict power requirements.

[0059] Fig. 1 shows a RF switch 100 comprising one memory latch and one or more FETs in a first embodiment of the invention while Fig. 2 shows an example of a physical layout of a chip comprising a RF switch as shown in Fig. 1 . In the first embodiment the radio frequency switch 100 comprises a first memory latch 110 which in turn comprises: a clock input 112 configured to receive a clock signal (CLK in the Figs.), a data input 114 configured to receive a data bit (DATA in the Figs.), and a data output 116 configured to output the data bit. The radio frequency switch 100 further comprises a first FET 130 comprising: a drain 132 configured to be connected to a first connection point 212 (also denoted switch drain, SWD) of an antenna unit cell 210 of the reconfigurable surface 200, a source 134 configured to be connected to a second connection point 214 (also denoted switch source, SWS) of the antenna unit cell 210, and a gate 136 connected to the data output 116 of the first memory latch 110. The first FET 130 is configured to be in a closed state when the data bit has a first value and in an open state when the data bit has a second value different to the first value thereby acting as a switch.

[0060] The first memory latch 110 may in non-limiting examples be a so-called D-type flip-flop. It serves the purpose to receive and keep in memory the data bit that controls the state of the FET switch. There is no requirement to read out the state of the memory through the access lines 232 and 234. Further, a VDD connection may exist to provide DC supply voltage for the memory latch 110 from a common PCB power plane, the voltage of which is adapted to the chosen semiconductor process.

[0061] For the logic circuitry of the memory latch 110 to operate it needs connection both to supply voltage VDD and common reference ground 204, which are common with the control system 230. The drain and source terminals 212, 214 (216, 218) of the FET switch may be considered as with floating potential in relation to the RF circuit of the antenna unit cell 210. This is because the antenna pattern may have the freedom of design to be either floating or tied to the RF ground plane. It is important to reliably establish well-defined logic levels at the gate 136 of the first FET 130 in order to properly turn the FET channel on or off. For this purpose, the source 134 of the first FET 130 may be connected to a common reference ground 204 through a first resistance 140 which establishes a defined gate-source voltage for maneuvering the first FET 130 as a switch. The first resistance 140 may be a high-value resistor. Hence, as also disclosed in Fig. 1 , the source 134 of the first FET 130 is connected to a common reference ground 204 via a first resistance 140. From an RF perspective this connection is not visible, and the terminals 212, 214 of the first FET 130 can be treated as floating. The terminals 212 and 214 should however not be connected to a surface with a direct current (DC) potential different to zero ( 0V), as this would upset the switch control of the first FET 130.

[0062] The RF switch 100 may further comprise Electrostatic Sensitive Device (ESD) protection circuits not shown in the appended Figs. However, it is noted that ESD protection circuits should be avoided on the first connection point 212 and the second connection point 214 terminals since the parasitic capacitance to ground of any protection diodes would degrade the performance of the RF switch through capacitive loading.

[0063] In embodiments of the invention, the first FET 130 is a N-channel FET (NFET) since electrons are the NFET majority carrier and have higher mobility than holes in a PFET. This makes the NFET have a lower on-state resistance and thus better RF performance. It is also preferable to use a CMOS process, because digital complementary logic can easily be added on the same chip as the switch FET 130. This is not the case for a GaAs-based semiconductor processes. GaAs MEtal-Semiconductor Field Effect Transistors (MESFET) or pseudomorphic High Electron Mobility Transistors (pHEMT) make excellent RF switches, but complementary logic cannot be implemented and thus the single-chip integration is not possible. The drain and source of the first FET 130 become the switch RF terminals and are thus connected to outer circuitry via the connection points, while the gate of the first FET 130 is used for controlling the switching function of the first FET 130. The NFET device design for the process may be optimized for good performance as an RF switch which could e.g., include features like triplewell device isolation and meandered gate design.

[0064] In embodiments, the first FET 130 and the first memory latch 110 may be integrated on to the same semiconductor die as shown in Fig. 2. Thus, the first memory latch 110 and the first FET 130 may be arranged on a common single chip 202. The first FET 130 may be designed for optimum RF switch performance for the frequency range of interest and laid out on the chip with the shortest possible paths from its drain and source terminals to the first connection point 212 and the second connection point 214. The first connection point 212 and the second connection point 214 are connected to the antenna unit cell between the points where the switch action is wanted.

[0065] The integration of FET(s) and memory latch(es) on the same chip may e.g., be achieved using a suitable CMOS process with optimized features for high frequency design (“RFCMOS”). The small scale of integration and the low number of components does not call for the use of the most advanced nano-scale process nodes. The physical design of the chip device of the first embodiment may be shaped as a small-size component with a symmetrical layout. In Fig. 2 the first embodiment is illustrated as a flip-chip Ball Grid Array (BGA) device with Controlled Collapse Chip Connection (C4) bumps, with the aim of minimizing parasitic series inductance from the connections in order to optimize the RF performance for high frequencies. The pinout is only an example in Fig. 2 and other variants are possible. Adaptation to, and co-design with the antenna element of the antenna unit cell 210 is important for the functionality. The significant point here is the ability to co-localize the memory latch together with the FET on one small chip that may be assembled into every antenna unit cell 210 of the configurable surface 200. This co-localisation of functions enables simple row / column addressing to set a beamforming code on the reconfigurable surface 200 where the switch chip is used. The chip 202 shall be small enough in relation to the wavelength of operation to present very low reactive parasitic elements to the RF switch connection, and to be assembled directly on the antenna surface in each antenna unit cell 210 without covering the antenna elements to any significant extent. The total number of connections to the chip should be kept low in order to make layout integration feasible without compromising RF performance. A package-less, flip chip design with small bumps and low connection pitch may thus be the best choice. If the desire is to use the present RF switch 100 for the low-GHz frequency range, where the negative impact of reactive parasitic elements is lower, the size and package design can be allowed to become larger. From the perspective of RF design of the antenna unit cell 210, the first FET 130 with connections 212, 214 may be considered as a discrete high-frequency semiconductor element similar to conventional discrete transistors or diodes and not as a part of an integrated circuit. The functions related to switch control, e.g., the memory latch 110, the control lines 232, 234, the voltage supply VDD and the control system 230, may in practice be invisible to the RF function of the configurable surface 200 and shall not affect the reflected electromagnetic wave.

[0066] The integration of multiple FET switches into a single chip combined with the unbiased switch channel also solves the problem of achieving an antenna unit cell 210 capable of handling two polarizations. For a single chip to suffice it is required that it be positioned in the centre of the antenna unit cell layout and that the antenna unit cell 210 and switch configuration has 4-fold symmetry. This becomes possible with the present solution and can still benefit from the simplified addressing network and from the liberty of designing the RF pattern without concerns for DC voltage conflicts.

[0067] A general requirement for any component that should act as a lumped element in a RF circuit is that it is small compared to the RF signal wavelength A, i.e. , less than A / 10. The antenna unit cell 210 in the reflective surface 200 is often around half wavelength (A / 2) and e.g., if the operating frequency is 30GHz this corresponds to 5mm. A chip that is assembled may thus be around 0.5mm in length in order not to perturb the antenna operation. Furthermore, reactive parasitic elements from package, with internal lead frame and chip connections, that come in series or parallel to the switch element tend to degrade the phase shifting performance and also to reduce the operation bandwidth. Such small design minimizes reactive parasitic elements and enables operation at high frequencies (FR2 defined by 3GPP). For use and operation at lower frequencies (FR1 defined by 3GPP) the size of the chip 202 would not be expected to change by much, but the size of the antenna unit cell 210 would grow according to the employed wavelength. At 3GHz, the chip size would amount to only ~A / 100 and it would be feasible to use the chip enclosed in a small package, e.g., a 10-pin Lead Frame Chip Scale Package (LFCSP) or Wafer-Level Chip Scale Package (WLCSP), a Land Grid Array (LGA) or similar type.

[0068] Fig. 3 further shows a reconfigurable surface 200 comprising multiple RF switches as shown in Fig. 1. The herein disclosed reconfigurable surface 200 comprises a plurality of antenna unit cells 210, where each antenna unit cell 210 comprises a RF switch 100 according to the first embodiment. The RF switch 100 is connected between connection points of the antenna unit cell 210. The reconfigurable surface 200 further comprises a control arrangement 230 connected to the plurality of antenna unit cells 210 via a plurality of column lines 234 and a plurality of row lines 232. The control arrangement 230 is configured to control the radio frequency switches 100 of the plurality of antenna unit cells 210 by providing a clock signal on the row lines 232 and a plurality of data bits on the column lines 234, or vice versa. Thus, the clock input 112 of the first memory latch 110 is configured to be connected to a column line 234 of the reconfigurable surface 200, and the data input 114 of the first memory latch 110 is configured to be connected to a row line 232 of the reconfigurable surface 200, or vice versa.

[0069] In general terms, the memory latch of the RF switching circuit holds the state of the RF switch and allows a row / column addressing of unit cells on the array of the configurable surface 200, similar to the function of a static random-access memory (SRAM) memory. On a reconfigurable surface 200 having an array of M x M antenna unit cells 210, this solves the problem of needing individual address lines to all M2number of RF switches in conventional solutions, and instead only 2M number of address lines are necessary. Setting a new code word on the array may be done column-by-column or row-by-row depending on the application. One such die per antenna unit cell 210 is used to populate the array. The components enable configuring the phase response of the reflective surface 200. With this arrangement, a new array code pattern can be implemented row-by-row in a progressive scan fashion. Hence, the plurality of data bits may represent a codeword of a beamforming scheme e.g., in 3GPP new radio (NR) communication system. At the edges of the array, the row lines and the column lines can be accessed and connected to the control circuits of the control arrangement 230. This is equivalent to memory cell access in an SRAM memory. The programmed state for the RF switch, i.e., ON or OFF state, will be held by a memory latch as long as supply voltage is present. The static power consumption in hold depends on the leakage current for the used complementary metal-oxide-semiconductor (CMOS) process but can be considered as nearzero.

[0070] Fig. 4 illustrates exemplary antenna unit cells 210 of a reconfigurable surface 200. The reconfigurability may be accomplished on antenna unit cell level by adding an ability for the antenna unit cell to give at least two different equidistant phase shifts to its reflection or transmission coefficient. A 1 -bit antenna unit cell would give a difference in its reflection phase of 36072 = 180° between its two programmable states “0” state and “1” state. Correspondingly, a 2-bit antenna unit cell would show a 360722= 90° quantization of phase states, thus 90° between 00 and 01 states, 180° between 00 and 10 states and 270° between 00 and 11 states.

[0071] To implement reconfigurability, the RF switch 100 is used to change the impedance in the antenna unit cell 210 to alter between different surface current patterns by using RF switches. From general electric circuit theory, we know that an open circuit has a reflection phase shift of 0° while a short circuit has a reflection phase shift of 180°. This property can be transferred to the response of the antenna element by the skilled designer. Intuitively it may be understood that the very large impedance shift from open circuit to short circuit indicates that the present RF switch is a very effective means of adding phase reconfigurability. For the antenna unit cell, the resulting reflection phase may show a specific characteristic curve as a function of frequency with the switch in one of its states. When the switch is toggled to its other state, the reflection phase characteristic curve changes and the difference between the two curves may be optimized by design to be as close to 180° as possible over a working bandwidth. Fig. 4 shows four non-limiting examples a) - c) of antenna unit cells where RF switches are incorporated for changing the reflection response of the reconfigurable surface 200. However, reconfigurability can also be achieved e. g., by switching a reactance coupled to the antenna.

[0072] Fig. 4a shows a single patch antenna, whose reflection phase can be altered by shorting a point on one side to RF ground. This has previously been demonstrated with conventional switches implemented using PIN diodes, which require a DC bias control current to be applied to the antenna patch through a bias arrangement (not shown). Adding a second PIN diode to this unit cell type cannot make it able to control two polarizations independently, because only one bias potential can be applied to the antenna patch. The switch action on this unit cell type is well suited for single-polarization implementation using an embodiment of the invention. Fig. 4b shows another type of single-polarization antenna unit cell, where the reflection phase reconfiguration is made by opening and closing a switch between two sub-patches. This switch action can also be accomplished by a RF switch according to embodiments of the invention. Fig. 4c shows an example type of antenna unit cell designed to control two polarizations and where the RF switches for phase reconfiguration have been localized close to the central point of the unit cell. The motive is that if the connection points for the RF switches can be brought reasonably close, they can be spanned by the size of a single chip which could contain multiple switches. This becomes particularly well adapted to use a switch chip according to embodiments of the invention with the embodiment containing multiple, independently controlled RF switches. Several variants of the design and the switch connectivity pattern is of course possible.

[0073] Figs. 5a - 5d can be viewed as a refinement of Fig. 4d and further illustrate an antenna unit cell 210 connected onto a reconfigurable surface multilayer PCB. Fig. 5a shows the size and shape of a chip in a flip-chip version with C4 solder bumps. Fig. 5b shows a type of an antenna unit cell 210 with 90° rotational symmetry vs. the orthogonal horizontal and vertical polarization planes. By designing for switching functions to be located in the center of the antenna unit cell 210, a one-chip solution becomes possible. In 5c an enlargement of the central area of the antenna unit cell 210 is shown. Control and bias to the chip is routed through vias coming up from lower printed circuit board (PCB) layers, i.e., the A-A cut-plane. On the top layer is the antenna pattern and the RF switch terminals of the chip connected to this pattern, i.e., the B- B cut-plane. Fig. 5d shows sections along the A-A and B-B cut-planes, including both the chip and the multilayer antenna PCB of the configurable surface 200. It is possible to see connections to the chip for control signals coming through micro-vias from rear side layers on the PCB. The RF switch 100 connections operate directly between points 212 + 214 and 216 + 218 on the top layer, thus the switches act to open and close crossing connections between diagonal pairs of sub-patches. The center bump is the common reference ground of the chip, but there is no RF ground among the chip connections as the RF switch 100 is a floating device in terms of potential.

[0074] Fig. 6 shows an implementation example of a communication device 300 comprising a reconfigurable surface 200 shown in a partial exploded view. The purpose of the communication device 300 may be to enhance coverage in cellular infrastructure but is not limited thereto. The reconfigurable surface 200 may be provided in different sizes depending on the needs of the particular installation locations. The exemplary communication device 300 comprises a metal back plate cover 242 which may house a battery compartment 244 at the upper side thereof. A radome front cover 246 is aligned with the metal back plate cover 242 and act as a radio transparent weather protection for the entire reconfigurable surface 200. The substrate of a reconfigurable surface 200 is arranged between the metal back plate cover 242 and the protective radome front cover 246. The antenna of the reconfigurable surface 200 is formed from rows and columns of antenna unit cells 210 arranged in an array of rows and columns. On each unit cell 210 a semiconductor chip 202 is assembled containing an RF switch 100. Further, a control arrangement 230 comprising control circuits may also be located on the reconfigurable surface 200 and connected to RF switches 100 with control lines running on the multi-layered substrate of the reconfigurable surface 200.

[0075] Fig. 7 illustrates reflective and transmissive properties of the reconfigurable surface 200 which implies that the present solution can also be designed to be a transmissive reconfigurable surface (i.e., Fig. 7b) and not only to a reflective reconfigurable surface (i.e., Fig. 7a). In such a case there would be no metal back plate cover 242 as shown in Fig. 6 to make the reconfigurable surface 200 open to EM waves in both normal directions (front and back) of the reconfigurable surface 200. It is also possible to use the present solution in other types of EM surfaces not intended for communication such as EM cloaking or filtering. These aspects are elaborated more in the final section of the present disclosure. Fig. 8 further shows a RF switch 100 comprising two memory latches in a second embodiment of the invention. Thus, the RF switch 100 further comprises a second memory latch 110' comprising: a clock input 112' configured to receive a common control signal CCS for the antenna unit cells 210 of the reconfigurable surface 200, a data input 114' connected to the data output 116 of the first memory latch 110, and a data output 116' connected to the gate 136 of the first FET 130. The second memory latch 110' is configured to transfer a data bit from the data input 114' to the data output 116' when receiving the common control signal CCS.

[0076] Thus, in the second embodiment an additional second memory latch 110' is connected to the output of the first memory latch 110. The clock input of second memory latch 110' is brought out to a common control signal (CCS) which may be denoted LOAD signal. The gate of the first FET 130 is connected to the output of the second memory latch 110'. The first memory latch 110 is configured to receive and hold the upcoming next information bit to set the first FET 130, whereas the second memory latch 110' holds the current information bit and drives the first FET 130 directly. The first memory latch 110 thus becomes a “shadow register” for the next beam code bit. Cycling the common control signal through one clock cycle transfers the “next” bit from the first memory latch 110 to become the “current” bit in the second memory latch 110'.

[0077] Fig. 9 shows a reconfigurable surface 200 comprising RF switches 100 as shown in Fig. 8, each RF 100 switch having two memory latches. In such configurations the control arrangement 230 of the reconfigurable surface 200 is connected to the plurality of antenna unit cells 210 via a common control line 226 and configured to transfer data bits at the data inputs 114', 124' of the memory latches 110', 120' to the outputs 116', 126' of the memory latches 110', 120' by providing a common control signal CCS.

[0078] Compared to the reconfigurable surface 200 comprising RF switches according to the first embodiment, this reconfigurable surface 200 allows an array to change its code word pattern into a new one instantly instead of by progressive scanning. This requires that the common control signal CCS of all chips on the array are connected together and are driven by one control signal from the control arrangement 230, and it follows that for a RIS array of size M x M unit cells, 2M + 1 outputs from the control arrangement 230 are necessary. Depending on the drive capability of the control arrangement 230 it may be necessary to provide buffer stages for the common control signal, e.g., one buffer per column. Uploading a code word to the array is still performed in a progressive scan manner and takes the same time as with the previous embodiment shown in Fig. 3, but the change from one array code word to a new code word can now be made during one clock cycle only. This reduces the time of undefined beamforming that the radio wave experiences, under which period there is a function outage for the reconfigurable surface 200. It is many times an important radio network system aspect to minimize such outage.

[0079] Fig. 10 moreover shows a RF switch 100 comprising two memory latches and two FETs in a third embodiment of the invention. In the third embodiment, the RF switch 100 further comprises a second memory latch 110' and a second FET 130'. The second memory latch 110' comprises: a clock input 112' configured to receive the clock signal CLK, a data input 114' connected to the data output 116 of the first memory latch 110, and a data output 116'; while the second FET 130' comprises: a drain 132' configured to be connected to a third connection point 216 of the antenna unit cell 210, a source 134' configured to be connected to a fourth connection point 218 of the antenna unit cell 210, and a gate 136' connected to the data output 116' of the second memory latch 110'.

[0080] In the third embodiment, a second memory latch 110' and a second FET 130' is added to the RF switch circuit 100 of the first embodiment. The gate 136 of the first FET 130 is connected to the output 116 of the first memory latch 110 and the gate 136’ of the second FET 130' is connected to the output 116’ of the second memory latch 110'. A general expansion of the third embodiment is to use more than two FET switch / latch pairs added in parallel thus forming a multi-bit switch chip that is adapted to creating multiple phase states for the antenna unit cell 210 by controlling multiple surface current paths in different patterns between multiple connection points on the reconfigurable surface 200 and can be seen as duplicating the RF switch circuit 100 of the first embodiment. The two memory latches in Fig. 10 are connected as a shift register. Hence, bits are written to the chip as a sequence on DATA while clocking CLK the required number of cycles. Each data output of a memory latch drives a gate of a FET switch. As in the first embodiment of the RF switch, programming of a code word on the array may be done with progressive scan column-by-column.

[0081] Fig. 11 shows an example of physical layout of a chip device 202 viewed from the bottom side, comprising the RF switch 100 as shown in Fig. 8 with external connections to solder bumps. Two RF switches have in this example been laid out crosswise, making it suitable for them to reconfigure reflection phase for two orthogonal polarizations. The antenna layout is required to bring the four switch connection points very close to each other for the chip to be able to span them all. As is evident from Fig. 11 , the chip size is largely decided by the number of, size of and the spacing of connection bumps. The required chip area to lay out the memory latch(es) and RF switch FET(s) is small in comparison and will fit in the space between the interconnects.

[0082] Fig. 12 shows a RF switch 100 comprising four memory latches and two FETs according to a fourth embodiment of the invention. In this embodiment the RF switch 100 comprises a third memory latch 120 comprising: a clock input 122 configured to receive the clock signal, a data input 124 connected to the data output 116 of the first memory latch 110, and a data output 126. The RF switch 100 also comprises a fourth memory latch 120' comprising: a clock input 122' configured to receive a common control signal for the antenna unit cells 210 of the reconfigurable surface 200, a data input 124' connected to the data output 126 of the third memory latch 120, a data output 126', wherein the fourth memory latch 120' is configured to transfer a data bit from the data input 124' to the data output 126' when receiving the common control signal. The RF switch 100 also comprises a second FET 130' comprising: a drain 132' configured to be connected to a third connection point 216 of the antenna unit cell 210, a source 134' configured to be connected to a fourth connection point 218 of the antenna unit cell 210, and a gate 136' connected to the data output 126' of the fourth memory latch 120'.

[0083] The fourth embodiment stands in relation to the third embodiment in the same way as the second embodiment relates to the first embodiment. The first memory latch 110 and the second memory latch 110' are connected as a shift register which is loaded by sequentially presenting two data bits on DATA while cycling CLK twice. The third memory latch 120 and the fourth memory latch 120' are connected to the outputs of first memory latch 110 and second memory latch 110', respectively. The output of second memory latch 110’ drives the first FET 130 and the output of fourth memory latch 120' drives the second FET 130'. A common control signal is added and connected to the clock inputs of second memory latch 110’ and fourth memory latch 120'. The code word is uploaded to the shadow register of the first memory latch 110 and third memory latch 120 while the present code word remains steady in the array. Same as for the second embodiment, the additional memory latches, i.e., the second memory latch 110’ and the fourth memory latch 120', enable changing the switch states at once upon toggling the common control signal one cycle.

[0084] A general expansion of the fourth embodiment is to use more than two RF switches, the number of memory latches will in that case be scaled accordingly. This forms a multi-bit switch chip that is adapted to creating phase states for the antenna unit cell 210 by controlling multiple surface current paths in different patterns between multiple connection points on the reconfigurable surface 200. In the embodiments when the RF switch 100 comprises two or more FETs, each FET may be connected to a common reference ground 204. Therefore, in Fig. 12 the source 134' of the second FET 130' is connected to a common reference ground 204 via a second resistance 140'.

[0085] Fig. 13 shows a RF switch 100 comprising two memory latches and two FETs in a fifth embodiment of the invention. In this embodiment, the two FETs are connected in series with each other between the first 212 and second 214 connection points. Therefore, the RF switch 100 comprises a second memory latch 110' comprising: a clock input 112' configured to receive the clock signal, a data input 114' connected to the data output 116 of the first memory latch 110, and a data output 116'. The RF switch 100 also comprises a second FET 130' comprising: a drain 132' configured to be connected to the source 134 of the first FET 130, a source 134' configured to be connected to the second connection point 214 of the antenna unit cell 210, and a gate 136' connected to the data output 116' of the second memory latch 110'. In this embodiment, the first FET 130 has a first gate width and the second FET 130' has a second gate width different to the first gate width, which is further explained below.

[0086] Hence, in the fifth embodiment two or more memory latches are integrated with two FETs connected in series to form a multi-bit switch chip that is adapted to creating multiple phase states for the antenna unit cell 210 by varying the capacitance between, and ultimately to create a short circuit or low resistance between two connection points on the reconfigurable surface 200. The fifth embodiment is based on the same principle as the third embodiment, but the first and second FETs 110, 110' are internally connected in series and brought to the two connection points 212 and 214. A distinguishing feature of this configuration is that the “off capacitance” and the “on resistance” of the first and second FETs 110, 110' due to the difference in gate width are used in combination to create a stepped variable impedance that can be used to create phase-change steps with increased resolution on the antenna unit cell 210. In this sense, the first and second FETs 110, 110' operate as a combined switch and stepped varactor whose operation is described as follows: Fig. 14 shows an equivalent model for a single FET operating in switch mode. When in the off-state, the switch exhibits a leakage capacitance determined by the size and geometry of the transistor and for a particular process mainly by its gate width. For maximizing the switch isolation for RF signals, it is desirable to make this capacitance as small as possible as to make its reactance as large as possible. It is however never possible to make the capacitance zero, so there will always be a residual “off capacitance” denoted COff. When in the on-state, the FET channel is brought into conduction and Coff effectively becomes bypassed by an “on resistance” denoted Ronwhose magnitude should be much less than the reactance produced by Coff for effective switch operation. When designing a high-frequency antenna unit cell for a reconfigurable surface 200, it is found that the magnitude of switch COff affects the reflection phase. This is natural, since a capacitance has a 90° phase shift between current and voltage. If one makes the switch design such that Coff can be varied, it is possible to turn this into an advantage for the reconfigurable surface 200. With increased quantization for the phase reconfiguration of the antenna unit cell 210, the beamforming radiation pattern can be improved in terms of better reflection gain, lower sidelobe levels and wider steering angles.

[0087] By putting two switch FETs in series and taking use of the formula for series-connected capacitors we can implement a stepped-impedance device having three capacitance values followed by a fourth resistance value. This is explained in Fig. 15 which shows the possible selections and equivalent model schematics that appear from the upper, the lower or both FETs on and off. With different size of the first and second FETs 130 and 130', it is possible to tailor the capacitance step size. In the example in Fig. 15, the first FET 130 has twice the gate width of the second FET 130’. It will make the first FET 130 have approximately twice the value for Coff as the second FET 130’ and half the value for Ronas the second FET 130’. From the connection points 212 and 214 it will appear as a single component that can take on varied impedance values. By co-design of the antenna unit cell with the FET switch series pair, the reflection phase can be designed to get more quantization levels. Compared to a single FET switch, the fifth embodiment brings an increase in Ronand thus a slight sacrifice of reconfigurable surface reflection loss. More than two FETs could be used, and the switch control be expanded accordingly, at the expense of further increased series resistance Ron.

[0088] Fig. 16 shows a RF switch 100 comprising four memory latches and two FETs in a sixth embodiment of the invention. The two FETs are connected in series with each other between the first 212 and second 214 connection points. Thus, the RF switch 100 comprises a third memory latch 120 comprising: a clock input 122 configured to receive the clock signal CLK, a data input 124 connected to the data output 116 of the first memory latch 110, and a data output 126. The RF switch 100 comprises a fourth memory latch 120' comprising: a clock input 122' configured to receive a common control signal for the antenna unit cells 210 of the reconfigurable surface 200, a data input 124' connected to the data output 126 of the third memory latch 120, a data output 126', wherein the fourth memory latch 120' is configured to transfer a data bit from the data input 124' to the data output 126' when receiving the common control signal. The RF switch 100 comprises a second FET 130' comprising: a drain 132' configured to be connected to the source 134 of the first FET 130, a source 134' configured to be connected to the second connection point 214 of the antenna unit cell 210, and a gate 136' connected to the data output 116' of the second memory latch 110'. As in Fig. 13 the first FET 130 has a first gate width and the second FET 130' has a second gate width different to the first gate width.

[0089] The sixth embodiment is an expansion of the fifth embodiment following the same principle as the fourth embodiment. With reference to Fig. 16, compared to the fourth embodiment, the first FET 130 and the second FET 130' are internally connected in series and brought to the two connection points 212 and 214. The switching function is thus equivalent to the fifth embodiment, while the programming and code word switching functionality is equivalent to the fourth embodiment. This forms a multi-bit RF switch that is adapted to creating multiple phase states for the antenna unit cell 210 by creating a stepped variable impedance between the two connection points 212, 214 on the reconfigurable surface. The addition of the third memory latch 120 and the fourth memory latch 120' allows for pre-loading the next bit pattern to the shadow register consisting of the first memory latch 110 and the third memory latch 120 and then changing to a new switch setting in one instance by cycling the common control signal instead of progressive scanning.

[0090] Fig. 17 shows physical layouts of a chip device where design concepts from the disclosed embodiments can be combined to achieve various goals of RF switch paths with more complexity. 17a illustrates one such combination with two independent switch paths according to the fourth embodiment, each switch path comprising of a 2-bit RF switch according to the sixth embodiment. Independent setting of the two 2-bit switch paths requires four bits to be uploaded, so the shift register needs to have four memory latches to make up the shadow register. The outputs of the four memory latches drive four other memory latches constituting the current register whose outputs drive the gates of the FETs. If instead complementary switch path operation is desired, the number of memory latches can be reduced to four and the complementary outputs Q and Q from the third and fourth memory latches 120, 120' may be used to drive the four switches of the two 2-bit switch paths. The chip pinout is shown at the top and the equivalent circuit diagram is shown at the bottom of Fig. 17a. Yet another example with increased complexity is shown in 17b in which there are two ganged switch sections according to the second embodiment, each holding a 2-bit RF switch using two series connected FETs to create a stepped variable impedance according to the sixth embodiment. The total number of bits to set up the switch condition is four, and hence a shadow register with four memory latches is necessary in this case. There are also four memory latches required for the current register, but as the opposite sections are ganged, the output of each memory latch is shared between the first and second FETs 130, 130' in both paths, respectively. Fig. 18a and 18b together illustrates the use of a reconfigurable surface 200 in a communication scenario. The communication system may e.g., be 3GPP NR using higher frequency bands for high bit rates. Hence, the radio frequencies employed for the RF switch 100 and the configurable surface 200 may be in the centimeter or millimeter wavelength range. Fig. 18a shows a street scenario with one BS on top of building B1 and five users UE1-UE5. The BS can connect to users LIE1-3 by direct beamforming, but users LIE4-5 are shadowed by building B2 and cannot be connected by a BS beam in a line of sight (LOS) path. Neither are there any distinct reflections from other buildings that could provide connection to users LIE4-5 through non-line of sight (NLOS) paths. By arranging a configurable surface 200 according to embodiments of the invention on the wall of building B3 in an open line of sight path from the BS it is possible to create new controllable NLOS paths from the BS to the shadowed area behind building B2 as shown in Fig. 18b. Therefore, it becomes possible to also connect users UE4-5 to the BS, which thereby has increased its coverage zone. The BS directs a beam towards the configurable surface 200, which in its turn can redirect the reflection beam over a wide range of angles to find users. The controlled beamforming by the configurable surface 200 is reciprocal and valid for both downlink and uplink communications. The configurable surface 200 may be controlled by the BS by a separate control link. For low deployment cost, low visual impact and for non-obtrusiveness, installation of configurable surface 200 on buildings shall not require a wired connection to neither power nor data networks. Average power consumption of the configurable surface 200 is low, typically <0.5W, thus powering from a small solar panel with rechargeable battery backup is sufficient. To reach this low power consumption it is necessary to use a technology for beam control on the antenna array which has near-zero static power consumption and very low power consumption when actively switching between beams.

[0091] Besides configurable surface 200 applications such as RIS as coverage enhancers in cellular networks, embodiments of the invention can also be used for reconfigurability in frequency selective surfaces (FSS) and radar cloaking surfaces. An aspect here would be that a reconfigurability property is desired, e.g., that an FSS could be given a bandstop filtering function that could be either turned on or off or moved in frequency, e.g., a 1 -bit filtering surface capable of altering between two frequency responses. An example could be a radome designed to block strong interferes to a communication link. The radome would be aided by an observation receiver which determines the frequency of the interferer and adjusts the stopband frequency for the reconfigurable radome to a range covering the interferer. The radome could be designed with conformal shape or planar surfaces. Taking this concept to a larger scale, another application is that a compartment or an entire room could be sealed or opened for communication with radio waves within a certain frequency range, such as for blocking Bluetooth or cellular communication on certain occasions.

[0092] Finally, it should be understood that the invention is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.

Claims

CLAIMS1 . A radio frequency switch (100) for a reconfigurable surface (200), the radio frequency switch (100) comprising: a first memory latch (110) comprising: a clock input (112) configured to receive a clock signal (CLK), a data input (114) configured to receive a data bit, and a data output (116) configured to output the data bit; and a first field effect transistor, FET, (130) comprising: a drain (132) configured to be connected to a first connection point (212) of an antenna unit cell (210) of the reconfigurable surface (200), a source (134) configured to be connected to a second connection point (214) of the antenna unit cell (210), and a gate (136) connected to the data output (116) of the first memory latch (110), wherein the first FET (130) is configured to be in a closed state when the data bit has a first value and in an open state when the data bit has a second value different to the first value thereby acting as a switch.

2. The radio frequency switch (100) according to claim 1 , wherein the first memory latch (110) and the first FET (130) are arranged on a common single chip (202).

3. The radio frequency switch (100) according to claim 1 or 2, wherein the first FET (130) is a N-channel FET.

4. The radio frequency switch (100) according to any one of the preceding claims, wherein the source (134) of the first FET (130) is connected to a common reference ground (204) via a first resistance (140).

5. The radio frequency switch (100) according to any one of the preceding claims, wherein the clock input (112) of the first memory latch (110) is configured to be connected to a column line (234) of the reconfigurable surface (200), and the data input (114) of the first memory latch (110) is configured to be connected to a row line (232) of the reconfigurable surface (200), or vice versa.

6. The radio frequency switch (100) according to any one of claims 1 to 5, further comprising: a second memory latch (110') comprising: a clock input (112') configured to receive a common control signal (CCS) for the antenna unit cells (210) of the reconfigurable surface (200), a data input (114') connected to the data output (116) of the first memory latch (110), and a data output (116') connected to the gate (136) of the first FET (130), wherein the secondmemory latch (110') is configured to transfer a data bit from the data input (114') to the data output (116') when receiving the common control signal (CCS).

7. The radio frequency switch (100) according to claim 6, further comprising: a third memory latch (120) comprising: a clock input (122) configured to receive the clock signal (CLK), a data input (124) connected to the data output (116) of the first memory latch (110), and a data output (126); a fourth memory latch (120') comprising: a clock input (122') configured to receive a common control signal (CCS) for the antenna unit cells (210) of the reconfigurable surface (200), a data input (124') connected to the data output (126) of the third memory latch (120), a data output (126'), wherein the fourth memory latch (120') is configured to transfer a data bit from the data input (124') to the data output (126') when receiving the common control signal (CCS); and a second FET (130') comprising: a drain (132') configured to be connected to a third connection point (216) of the antenna unit cell (210), a source (134') configured to be connected to a fourth connection point (218) of the antenna unit cell (210), and a gate (136') connected to the data output (126') of the fourth memory latch (120').

8. The radio frequency switch (100) according to claim 6, further comprising: a third memory latch (120) comprising: a clock input (122) configured to receive the clock signal (CLK), a data input (124) connected to the data output (116) of the first memory latch (110), and a data output (126); a fourth memory latch (120') comprising: a clock input (122') configured to receive a common control signal (CCS) for the antenna unit cells (210) of the reconfigurable surface (200), a data input (124') connected to the data output (126) of the third memory latch (120), a data output (126'), wherein the fourth memory latch (120') is configured to transfer a data bit from the data input (124') to the data output (126') when receiving the common control signal (CCS); and a second FET (130') comprising: a drain (132') configured to be connected to the source (134) of the first FET (130), a source (134') configured to be connected to the second connection point (214) of the antenna unit cell (210), and a gate (136') connected to the data output (116') of the second memory latch (110'); wherein the first FET (130) has a first gate width and the second FET (130') has a second gate width different to the first gate width.

9. The radio frequency switch (100) according to any one of claims 1 to 5, further comprising: a second memory latch (110') comprising: a clock input (112') configured to receive the clock signal (CLK), a data input (114') connected to the data output (116) of the first memory latch (110), and a data output (116'); and a second FET (130') comprising: a drain (132') configured to be connected to a third connection point (216) of the antenna unit cell (210), a source (134') configured to be connected to a fourth connection point (218) of the antenna unit cell (210), and a gate (136') connected to the data output (116') of the second memory latch (110').

10. The radio frequency switch (100) according to any one of claims 1 to 5, further comprising: a second memory latch (110') comprising: a clock input (112') configured to receive the clock signal (CLK), a data input (114') connected to the data output (116) of the first memory latch (110), and a data output (116'); and a second FET (130') comprising: a drain (132') configured to be connected to the source (134) of the first FET (130), a source (134') configured to be connected to the second connection point (214) of the antenna unit cell (210), and a gate (136') connected to the data output (116') of the second memory latch (110'); wherein the first FET (130) has a first gate width and the second FET (130') has a second gate width different to the first gate width.

11. The radio frequency switch (100) according to any one of claims 7 to 10, wherein the source (134') of the second FET (130') is connected to a common reference ground (204) via a second resistance (140').

12. The radio frequency switch (100) according to any one of the preceding claims, wherein the radio frequency is in the centimeter or millimeter wavelength range.

13. A reconfigurable surface (200) comprising: a plurality of antenna unit cells (210), wherein each antenna unit cell (210) comprises a radio frequency switch (100) according to any one of the preceding claims connected between connection points (212, 214, 216, 218) of the antenna unit cell (210); and a control arrangement (230) connected to the plurality of antenna unit cells (210) via a plurality of column lines (234) and a plurality of row lines (232) and configured to control the radio frequency switches (100) of the plurality of antenna unit cells (210) by providing a clock signal (CLK) on the row lines (222) and a plurality of data bits on the column lines (224), or vice versa.

14. The reconfigurable surface (200) according to claim 13, wherein the control arrangement (230) further is connected to the plurality of antenna unit cells (210) via a common control line (226) and configured to transfer data bits at the data inputs (114', 124') of the memory latches (110', 120') to the outputs (116', 126') of the memory latches (110', 120') by providing a common control signal (CCS).

15. The reconfigurable surface (200) according to claim 13 or 14, wherein the plurality of data bits represents a codeword of a beamforming scheme.

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