Electro-optical analog to digital conversion

Abstract

Electro-optical conversion of an input analog signal and optical modulation of the optical signal to provide light of different intensity levels to 2n photodetection sites whose outputs can be encoded as an n-bit digital output value. The sample rate can exceed 10 GHz (rates above 100GHz are possible) with much greater simplicity of electronic circuitry.

Description

Electro-Optical Analog to Digital Conversion

[0001] This patent application claims priority to US provisional patent applications 63 / 620,922 filed January 15, 2024 and 63 / 485,322 filed February 16, 2023. US patent 11,885,675 was issued on January 30, 2024 and also claims priority to US provisional patent application 63 / 485,322 filed February 16, 2023.Technical Field

[0002] The present application relates to high-speed analog to digital conversion.Background

[0003] Fast Analog to Digital Converters (ADCs), circuits that convert an analog signal to digital values, use 2narray of comparators that have the input signal applied to one input and an ascending reference voltage to the other. The ascending reference voltage being generated by a 2nseries of equal valued resistors where a voltage is applied at one end and ground at the other. The comparators are then input to an encoder that will convert the 2nsignal to n bits.

[0004] Here n is the resolution of the converter circuit.

[0005] The speed is the clock rate at which the circuits operate, i.e., the rate at which the input analog signal is sampled. Sampling the input signal at twice the frequency of the highest frequency component of the signal (Nyquist frequency) will reproduce the input signal.

[0006] As n increases from n to n+ 1, the complexity of this circuit doubles. The number resistors and comparators doubles with rise in noise and distances, both effecting the maximum speed possible for a given resolution.

[0007] The most significant issues here are not the semiconductor technology used to implement the circuit, which is a limitation also, but the components (resistors and comparators) that are affected by increase of 2n.Summary

[0008] Applicant proposes to use electro-optical conversion of an input analog signal and optical modulation of the optical signal to provide light of different intensity levels to 2nphotodetection sites whose outputs can be encoded as an n-bit digital output value. The sample rate can exceed 10 GHz (rates above 100GHz are possible) with much greater simplicity of electronic circuitry.

[0009] In some embodiments, there is provided an analog to digital conversion device comprising a light source having an analog electrical signal input and an optical output at an output optical power level variable as a function of a level of the electrical input, a waveguide connected to the optical output at an input and emitting over a detection surface of the waveguide a decaying level of optical power in proportion to the output optical power level, an array of 2nphotosensitive circuit elements on a single semiconductor substrate coupled with the surface of the waveguide, each one of the photosensitive circuit elements having a digital output depending on light intensity and positioned to receive a different level of optical power depending on its position in the array, and an encoder responsive to the digital output from each one of the 2nphotosensitive circuit elements and having a digital value output of n-bits.

[0010] The device may include a preamplifier connected to the analog electrical input for amplifying an analog input. The array of 2nphotosensitive circuit elements on a single semiconductor substrate may comprise photodiodes. The photosensitive circuit elements may each comprise a comparator receiving and comparing an output from the photodiodes to a threshold for generating the digital output.

[0011] The photodiodes may be germanium on silicon. The device may be operable to provide the digital value output at a frequency greater than 10 GHz, preferably greater than 100 GHz.

[0012] The array of 2nphotosensitive circuit elements and the encoder may be implemented in germanium.

[0013] The waveguide may be a continuous gradient neutral density waveguide.

[0014] The digital value output may be linearly proportional to the level of theelectrical input.

[0015] The light source, the waveguide, the array of 2nphotosensitive circuit elements and the encoder may be integrated into a common package.

[0016] In some embodiments, there is provided a method for converting an analog electrical signal to a digital value, comprising converting an electrical input signal into an optical signal whose intensity corresponds to an analog level of the electric input signal, modulating the optical signal over a detection area so as to have a locally variable intensity as a function of position on the detection area, detecting at 2nlocations within the detection area a light intensity threshold to provide 2nbits corresponding to 2n levels of the analog level of the electric input signal, and converting the 2n bits into an n-bit digital value.Brief Description of the Drawings

[0017] The invention will be better understood by way of the following detailed description of embodiments of the invention with reference to the appended drawings, in which:

[0018] Figure 1: System diagram of the solution described in the disclosure.

[0019] Figure 2: Continuous Gradient Neutral Density device window and corresponding characteristic profile.

[0020] Figure 3: A plot of laser power output as a function of drive current for a laser and an LED.

[0021] Figure 4: Photodetector array.

[0022] Figure 5: Photo detector array and CGND device arrangement.

[0023] Figure 6: Photodetector array and encoder combinatorial circuit.

[0024] Figure 7: An arrangement of the components in the integrated analog to digital converter of one embodiment.

[0025] Figure 8: 2nelements of the photodetector array.

[0026] Figure 9: A flowchart illustrating the sensitivity calibration of each photosensitive element of the photodetector array.

[0027] Figures 10A and 10B: Tables containing the binary states of the 2nphotosensitive elements.

[0028] Figure 11: A logic circuit of the photodetector array.Detailed Description

[0029] The invention disclosed here provides a solution to the limitation of speed and resolution of the input stage where the detection of the value of the input signal is detected, i.e. the voltage of the input signal through parallel comparison of the signal to 2ndifferent refence voltages. The hmitation comes from the connection and resistors required to do this along with the comparators. The logic conversion of encoding 2nto n is in the digital domain therefore not being limited by the same factors as the comparator circuit.

[0030] Figure 1 shows a schematic block diagram of the ADC device 10 comprising an analog input 12, an amplifier 14 (optional) for amplifying the input 12 that drives an optical source 15 to produce an output power 16, where the optical source 15 may be a semiconductor LED or a laser. The output 16 is then coupled with a modulator 20 that may have an output window 22 with a variability in output intensity over the output window 22. The output 22 of the modulator 20 is optically coupled with an array of light detectors 24 that produces individual digital bits for each light detector responsive to a different light level at the output 22. The photodetectors 24 may be an exact power of 2 in number, i.e., 2n. An encoder 26 can convert the 2nbits into a n-bit digital value or word 28. For example, 4096 detector bits can be encoded by encoder 26 into a 12-bit value 2, which provides a reasonably high precision with respect to the input signal while maintaining a manageable amount of data. Each of such 12-bit values may be stored in a memory (e.g., series of registers, such as RAM, ROM, etc.), which may be included in encoder 26.

[0031] Thus, the input analog signal 12 is first converted to light 16 through modulating a source 15, for example an LED or a laser, with the desired bandwidth.

[0032] The light source 15 can be butt coupled to an optical modulator 20, for example a Continuous Gradient Neutral Density (CGND) device. This device 20 can attenuate the light 16 such that light intensity varies linearly with the distance fromone end of the device to the other at the exit window 22 (see Figure 2). The range of the light intensity versus voltage can be Vmax-Vmin = D. The relationship between voltage and current can be determined by the V to I curve of the device 15 being used to generate the light (Figure 3).

[0033] The CGND device 20 can be a light guide with properties of absorption in the long direction such that the light attenuates as it travels. An elongated quartz glass waveguide member can be used with a cross-section that is round, square or rectangular. On one side of the device, along the length can be a very narrow window, barely bigger than the detector array and at least as long the detector array. On the window can be a coating that provides a continuous gradual increase in density from one end to the device to other along the length of the device. The result can be that if light is injected into one end of the device, some of it will come out through the window with gradually increasing or decreasing intensity. The range of intensity will reflect the range of the neutral density filter being coated on. Normal coatings of continuous gradient density are 0-0.4D to 0-4D, where D is one order of magnitude.

[0034] Therefore, the property of the optical modulator can be such that over the distance X, the length of the device, the total absorption can be between 0.5 D to 4 D (i.e., from 0.5 to 10,000).

[0035] Another example would be a waveguide or optical fiber with side losses that provides for a decreasing intensity of laterally emitted light along the waveguide. Such a variant need not rely on an absorption filter coating.

[0036] Another example would be a waveguide made of a material that slowly absorbs light of the desired wavelength such that light is attenuated along the length of the waveguide. Colored glass can have the desired property for the wavelengths other than the color of the glass seen. The effect can be a continuous gradient neutral density device for the specific wavelength.

[0037] The optical modulator can alternatively rely on free-space optics, however, an optical modulator that is easy to contain in a package with the light source and photodetector array is preferred.

[0038] In all cases the value of density / intensity modulation range may dependon the photodetector array such that the resolution is as desired but limited by the properties of the photodetector. The properties are the sensitivity, the width of the detector and the speed of response of the detector.

[0039] The calculation may be (density r an ge / 2n)* (light Intensity at input).

[0040] The length of the device may be l=width of the photodetector*2n.

[0041] Height of the output window may be a minimum of twice the height of detector.

[0042] The window of the CGND may be coupled to an array of photodetectors (Figure 5).

[0043] This disclosure of the voltage to light conversion and detection of the light intensity via an array of photodetectors can eliminate the limitation on present technology to fabricate high speed and higher resolution analog to digital converters. The photodetectors array may be constructed of an array of identical photodetectors with a threshold detection circuit and buffer connected to a logic encoder of 2nto n bits.

[0044] In the preferred embodiment, the output of the photodetector array 24 is generated when the intensity of light provided by the output 22 of the modulator 20 is above the determined light intensity threshold, which depends on the amplitude of the input signal. Each of the outputs of the photodetector array 24 can be monolithically fabricated with a 2nto n bit encoder, and they can be stored in memory of encoder 26 (e.g., RAM, ROM, SSD, etc.) at the address corresponding to that n bit word.

[0045] The electron mobility of the semiconductors used to fabricate the photodetectors may determine the highest speed and resolution that can be achieved.

[0046] In the preferred embodiment, the semiconductor technology can be Ge on Si that can achieve 500 GHz speed of the transistors and 5 picosecond photodetector response.

[0047] A one-dimensional array of photodetectors, 2n, can be placed in close proximity alongside the CGND device (optical modulator) such that each photodetector can detect the light from a different point in the variable gradient ofthe light from the CGND (Figure 2).

[0048] Each detector may have an amplifier or buffer connected to it and these 2namplifiers or buffers are then input to an encoder circuit (Figure 5) that will encode the 2ninputs to n outputs.

[0049] The speed of this analog to digital converter device can then depend on the speed of the detectors, amplifier and encoder technology. The bandwidth of the system can then be dictated by the smallest of the bandwidth of the signal path, i.e., the receiving buffer / amplifier, the photodetectors, the photodetector buffer / amplifies and the combinatorial logic circuit for forming the encoder. The photodetector and the combinatorial logic encoder can be integrated and fabricated as a monolithic device on a semiconductor substrate.

[0050] One embodiment (see Figure 7) can be germanium on silicon semiconductor technology to implement the circuit in Figure 6, capable of 100 GHz operation. The resolution depends on the number of detectors in the array to be n=antilog (2n).

[0051] As illustrated in Figure 6, photodiodes 24a can be used. The photodiodes can be connected to a voltage source that may be common to all detectors. Resistors R0 to R2n can be connected between the output of the photodiodes and ground. Comparators 24b can be connected to the output of the photodiodes to produce a binary digit on traces 24c. In this way, a light threshold detector circuit can be provided. The comparators act as amplifier / buffer circuits and output a bit each. Such circuits are known in the art and have a very high rate of repeatability and performance.

[0052] While a phototransistor can be used instead of a photodiode, the photodiode can be simpler to implement. It will be appreciated that a photodiode (PD) can be connected in series with the resistor R. Depending on the order, the measured voltage can be zero at zero light or zero at full light. The comparator 24b preferably transitions between a 0 and a 1 logical Boolean output at the same voltage level for all comparators 24b. A common reference voltage may be used for this purpose.

[0053] The arrangement of the components in the integrated analog to digitalconverter as one of the embodiments is in Figure 7. As shown, the array of light detectors 22 can be on the semiconductor substrate, while the optical modulator 20 can be mounted on the detector array 22. The light source 15 can be connected to the modulator 20 above the substrate and connected to the amplifier / buffer 14 on the substrate through a wire bond connection 14b. It will be appreciated that the light source can alternatively be on the substrate surface (e.g., a vertical-cavity surfaceemitting laser) with the modulator 20 adapted to receive and redirect light from the source 15.

[0054] Figure 8 illustrates the photodetector array 24 provided by 2nelements that are arranged in order. For instance, the photodetector array comprising 212(4096) photosensitive elements may be placed on an area of the substrate (for example, germanium on silicon) of 20 mm long and 2 mm wide, namely the spacing between photosensitive elements is about 4.9 microns.

[0055] Each photosensitive element of the photodetector array 24 can be in “off’ or “on” states. The “off’ and “on” states of the photosensitive element mean that the voltage / current generated by the photodiode, when it is exposed to a certain light intensity, is below or above the threshold required to activate it, accordingly.

[0056] Each photosensitive element of the photodetector array 24 can be connected in series with a resistor (for instance, see Figure 11). The latter may be provided, for example, by a thin film resistor with a metal film layer, which is made of nickel-chromium or similar alloys, or a thin film resistor with a metal oxide film, which is typically made from tin oxide. Both types of such resistors can be placed on a glass, ceramic, or silicon substrate. As mentioned above, the photosensitive elements (e.g., photodiodes) may be germanium on silicon, which, therefore, provides the substrate for the resistors as well. It will be appreciated that the photosensitive elements can be located on one side of the silicon substrate and the resistors associated with each of those elements can be located on the opposite side of that same substrate. Also, the silicon substate may be substituted by any other suitable semiconductor substrate.

[0057] For an analog to digital converter, comprising a photodetector arraywith 212(4096) photosensitive elements, in order to obtain a 12-bit digital word, the sensitivity to light of any photosensitive element must be (1 / 4096)* 100% ~ 0.02% of the entire array sensitivity. This means that each photosensitive element must have a sensitivity tolerance of about ±0.01%, which is very challenging to achieve during the manufacturing process. It is helpful that the photosensitive elements and the associated electronic comparators and logic can be provided in proximity on a single substrate. Nevertheless, laser trimming of the resistors associated with each photosensitive element can be advantageous.

[0058] In some embodiments, the resistors can be located on a silicon substrate, which enhances their integration, precision, thermal performance, and reliability. A silicon substrate may also provide a stable platform for a resistor during the laser trimming process (or other suitable techniques), i.e., offering a high-precision resistance adjustment. The latter may allow to determine the reference voltage / current (here denoted as Vref), used for the future comparison with the voltage / current of each photosensitive element.

[0059] In the laser trimming process, a laser is used to selectively remove or modify the resistive material on the resistor, thereby changing the resistance. Such an adjustment is typically made by removing small amounts of material in a controlled manner until the desired resistance is achieved. The laser trimming is a highly controlled process that does not inherently increase or decrease the resistance of a resistor, but rather allows to adjust the resistance to a specific value depending on the intensity and duration of the laser exposure. More specifically, the resistive material modification may be achieved by annealing, where a laser is used to heat a specific area of a resistor to modify the electrical properties of the resistive material without physically removing it, or doping, where a laser can be used to introduce or modify doping elements (i.e., specific impurities) within the resistive material, which, in turn, also alters the electrical conductivity of that material. During the laser trimming, the resistance of the resistor is monitored in real-time, i.e., the feedback is collected immediately, and the laser parameters are adjusted dynamically to ensure that the desired resistance value is achieved. In some embodiments, themeasurement of the change to the resistance is not direct, but instead involves detecting a change in the detection state of the photosensitive element and associated circuitry.

[0060] In some embodiment, the laser trimming process can be applied directly to the continuous neutral density gradient waveguide allowing to adjust or fine-tune its optical characteristics, for example by selectively removing a portion of a waveguide coating, such as a thin film. As an example, if a top side of the waveguide 20 is provided with a reflective metal coating, laser ablation of the coating can be used to increase losses at any of the desired photodetection sites. Laser trimming in general can also allow for wavelength tuning, refractive index tuning and optical loss reduction allowing for guiding and filtering specific wavelength ranges in order to achieve a desired light propagation along that waveguide. Since laser trimming is a highly controlled process, the adjustment of the characteristics of the waveguide can be performed with high accuracy, and therefore there may be no need for additional laser trimming of the resistors corresponding to photosensitive elements.

[0061] Figure 9 depicts the flowchart illustrating the sensitivity calibration of each photosensitive element of the photodetector array 24. At the start, all the photosensitive elements of the array 24 are in the “off’ state. In this example, the array 24 comprises 212(4096) photosensitive elements. To start the calibration process, the intensity of the analog signal produced by the modulator 20 is adjusted using the amplifier 14 in such a way that it should only trigger the response of the first photosensitive element of the photodetector array. This can be considered as an adjustment of a base level or offset (e.g., a constant voltage that is added to the amplifier output signal irrespective of the input signal). Therefore, the intensity value is adjusted to be (1 / 4096)* 100% ~ 0.02% of the intensity value required to trigger the response of all photosensitive elements, and it is considered as the minimum intensity value. As the next step, the nominal gain of amplifier 14 (i.e., expected, or designed amplification factor of an amplifier under normal operating conditions, which may be provided by a ratio of the output voltage to the input voltage) can be set by using an intensity value of 100% and adjusting the gain such that the 4096thphotosensitive element begins to change its state. The output of the amplifier 14 is coupled to the continuous neutral density gradient waveguide, allowing the analog signal input to reach each photosensitive element. It will be understood that the offset of the amplifier 14 is adjusted in such a way that enables the detection of the input signal by the first photosensitive array element, and the analog signal input intensity set to 100% (the maximum signal intensity) allows for the gain of the amplifier 14 to be tuned to allow that the nth element to switch from the “off’ to “on” state.

[0062] Once the maximum input signal intensity required to trigger the response of all the array elements has been determined, tuning of each resistor corresponding to each photosensitive element using the laser trimming process may be required to achieve their individual ordered response to the input signal. In this case, starting from the first array element, the input analog signal intensity is increased by ~0.02% of the maximum intensity value for each next array element at a time. However, when the analog signal of such intensity is passed to the photodetector array, the photosensitive element, which may respond to it, may not necessarily be the next photosensitive array element of interest. It means that the sensitivity of each array element must be considered, and it may be adjusted in such a way that each photosensitive element can respond to the increase of intensity in the ordered manner. To achieve this, the resistance of each resistor associated with each next photosensitive element can be adjusted one at time to ensure finding the point at which that photosensitive element switches from the “off’ state to the “on” state. Once the resistance of every resistor has been adjusted, the calibration process stops.

[0063] In this example, it is considered that the light intensity is gradually increased in a linear manner. However, depending on the desired order in which the array elements appear in the “on” state, it is appreciated that the intensity of the input signal may be increased non-linearly. In the case of a non-linear ADC, the intensity values of the analog input signal at which the individual photosensitive elements change state can be recorded in the encoder 26.

[0064] Figures 10A and 10B illustrate the tables containing the binary statesof the 2nphotosensitive elements. The five array elements m-2, m-1, m, m+1, m+2 of the photodetector array 24 are shown to help explain the resulting output, which is further stored in the encoder 26 and after processed to generate the corresponding n- bit word. The “off’ or “on” states of each photosensitive element of the photodetector array 24, as well as the outputs associated with those elements to be registered in the encoder 26, are provided by the binary logical values 0 and 1. It will be appreciated that the assignment of these binary values in this context and further in the description is arbitrary. However, depending on such an assignment, the circuit logic will achieve an accurate analog to digital conversion.

[0065] Figure 11 illustrates the logic circuit of the photodetector array 24. The output 22 received from modulator 20 and amplified by amplifier 14 is passed to 2nelements of the photodetector array, with three consecutive elements m-1, m, m+1 demonstrated. Since the photodiodes and their corresponding resistors may be located on the opposite sides of the silicon substrate, the continuous neutral density gradient waveguide is illustrated by the dashed segment passing between the photodiodes and resistors.

[0066] Each array element (e.g., photodiode) can comprise a comparator (or be connected to a comparator) for comparing the output volt age / curr ent of that photodiode to the intensity threshold volt age / curr ent value. The threshold value should be the same for all photodiodes in the array. The light intensity threshold level is provided by a continuous neutral density layer of density D, which can be adjusted using neutral density filters. Also, the sensitivity of each comparator must be the same for all the corresponding photodiodes to ensure accurate current / voltage comparison.

[0067] In the current example, the “off’ or “on” states of each photosensitive element (for simplicity, further referred as photodiode) of the photodetector array 24 are denoted by the binary values 0 and 1, respectively. Also, if the volt age / curr ent of the photodiode is below the threshold, the output of the corresponding comparator may then be 0, and it is 1 otherwise. As mentioned above, such an assignment of binary values is arbitrary, and it can be changed, if it does not affect further describedcircuit logic. Regardless of the current / voltage of a photodiode being below or above the threshold level, that photodiode is still activated, i.e., it is in the “on” state.

[0068] The output of a comparator is passed as an input to the corresponding AND gate, which can also comprise a comparator, and it is registered in the encoder 26. The AND gate also takes as an input the output of the NOT gate associated with the previous photodiode. However, for the very first photodiode, which is activated by the input signal (for instance, see element 0 in Figures 10A and 10B), there is no NOT gate output from the previous photodiode to contribute to the corresponding AND gate input. Thus, if the current / voltage of a photodiode is below the threshold level, then the output of the comparator is 0, and it is passed as a two-input to the corresponding AND gate to produce the resulting 0 output. The output is registered in the encoder 26, and it is further passed to the NOT gate, which outputs 1 if the output of the previously connected to it AND gate is 0 and outputs 1 otherwise. This means that, for the next array element activated by the signal, the AND gate now has two inputs: the output out the corresponding comparator and the output of the previously connected NOT gate (for instance, see element 1 shown in Figures 10A and 10B).

[0069] As mentioned above, when the photodiode voltage / current is below the threshold level, the output of the associated comparator is 0, and the output of the corresponding AND gate is then 0 as well (see the states and the outputs of the photodiodes 0, 1, 2, m-2 and m-1 in Figures 10A and 10B). This output is then passed to the NOT gate that, in this case, converts it to 1. When the voltage / current of the photodiode is above the threshold, the output of the corresponding comparator is 1. As the result, the output of the corresponding AND gate becomes 1 as well (see state and output of the photodiode m in Figures 10A and 10B). This implies that the next NOT gate takes 1 as the input and outputs 0, which is then passed as an input to the AND gate associated with the next photodiode also responding to the input signal. If the current / voltage of the next photodiode is below the threshold value, then, following the same logic, the output of the AND gate is 0 (see elements m+1, m+2, etc. in Figures 10A). In this case, the element m is the last element above thethreshold, and its output further determines the resulting n-bit word. It is possible to have, for example, the current / voltage of the photodiode m to be above the threshold, then the photodiode m+1 to be “below the threshold”, and after that the photodiode m+2 to be “above the threshold” again (see Figure 10B), which results in two outputs provided by the logical value 1. It can be caused by the sensitivity of the corresponding comparator, slight change in characteristics of the corresponding resistor, and the current / voltage values of the abovementioned photodiodes being extremely close to the threshold value. In this case, the photodiode m would still be considered as the last photodiode “above the threshold”, and its corresponding output 1 would contribute to the n-bit word. Once the last photodiode “above the threshold” is determined, the rest of the photodiodes that have not been activated are considered to be in the “off’ state.

[0070] It will be appreciated that the logic circuit elements, such as, in this example, the NOT and AND gates, could be replaced by the combination of other circuit logic elements (e.g., NAND, OR and NOR gates, etc.) to achieve the same functionality of the present device. Moreover, in the example described above, the output of an AND gate associated with one photodiode is compared to the AND gate output of the next photodiode, to determine the last photodiode with its voltage / current being above the intensity threshold level. It will be obvious to the person skilled in the art that the logic circuit could be designed in such a way to allow comparing the output of one AND gate to, for example, the output of the neighboring AND gate(s), in order to achieve a higher accuracy for determining the last photodiode above the threshold.

Claims

What is claimed is:

1. An analog to digital conversion device comprising: a light source having an analog electrical signal input and an optical output at an output optical power level variable as a function of a level of said electrical input; a waveguide connected to the optical output at an input and emitting over a detection surface of said waveguide a decaying level of optical power in proportion to said output optical power level; an array of 2nphotosensitive circuit elements on a single semiconductor substrate coupled with said surface of said waveguide, each one of the photosensitive circuit elements having a binary digital output depending on light intensity and positioned to receive a different level of optical power depending on its position in said array; and an encoder responsive to said binary digital output from each one of the 2nphotosensitive circuit elements and having a digital value output of n-bits.

2. The device of claim 1, further comprising a preamplifier connected to said analog electrical input for amplifying an analog input.

3. The device of claim 1 or 2, wherein said array of 2nphotosensitive circuit elements on a single semiconductor substrate comprise photodiodes.

4. The device of claim 3, wherein said photosensitive circuit elements each comprise a comparator receiving and comparing an output from said photodiodes to a threshold for generating said binary digital output.

5. The device of claim 3 or 4, wherein said photodiodes are germanium on silicon.

6. The device of any one of claims 1 to 5, wherein said device is operable to provide said digital n-bit value output at a frequency greater than 10 GHz.

7. The device of claim 6, wherein said frequency is greater than 100 GHz.

8. The device of claims 6 or 7, wherein said array of 2nphotosensitive circuit elements and said encoder are implemented in germanium.

9. The device of any one of claims 1 to 8, wherein said waveguide is a continuous gradient neutral density waveguide.

10. The device of any one of claims 1 to 9, wherein optical parameters of said waveguide are adjusted by selectively modifying a coating of said waveguide at locations associated with 2nphotosensitive circuit elements using laser trimming allowing to deliver enough energy to said waveguide locations to achieve desired waveguide performance.

11. The device of any one of claims 1 to 10, wherein said n-bit digital value output is linearly proportional to said level of said electrical input.

12. The device of any one of claims 1 to 11, wherein said light source, said waveguide, said array of 2nphotosensitive circuit elements and said encoder are integrated into a common package.

13. The device in any one of claims 1 to 12, wherein each of said 2nphotosensitive circuit elements comprises a photosensitive element having a conduction variable with a light level and connected in series with a resistor and a common voltage, wherein a voltage drop across one of said photosensitive element and said resistor varies with said light level.

14. The device of claim 13, wherein said resistors are spaced on said single semiconductor substrate to allow adjusting their resistance using laser trimming.

15. The device in any one of claims 1 to 14, wherein said encoder further comprises series of registers.

16. The device in claim 15, wherein each of said 2nphotosensitive circuit elements comprises an AND gate having inputs from consecutive pairs of said photosensitive elements for outputting a logic level when said binary digital output changes state.

17. The device of claim 16, wherein said AND gate further comprises a comparator for comparing said voltage drop to a common reference voltage.

18. The device of claim 16 or 17, wherein each consecutive pair of 2n-l AND gates comprise a connection to a NOT gate.

19. The device of claim 18, wherein said encoder further comprises a light intensity tracking logic circuit that takes as an input a binary digital output of said comparator, said AND gate and said NOT gate associated with each of said 2nphotosensitive circuit elements and produces a resulting binary digital output that is stored in at least one of said series of registers to be further converted to the n-bit digital value output.

20. A method for calibrating the 2nphotosensitive circuit elements of the analog to digital conversion device of any one of claims 1 to 19 comprising: setting a minimum intensity level of the analog electrical signal input to (l / 2n)*100% of a maximum analog electrical signal value; adjusting an offset of the light source until a first element of said 2nphotosensitive circuit elements responds to the analog electrical signal input; setting a maximum intensity level of the analog electrical signal input and adjusting a gain of the light source to a point when a last one photosensitive circuit element of said 2nphotosensitive circuit elements detects the analog electrical signalinput; and laser trimming at least one of the resistors and the coating of said waveguide at the locations associated with 2nphotosensitive circuit elements to allow them to respond to the input light intensity in a particular order while the light intensity is increased by (l / 2n)*100% for each consecutive photosensitive circuit element.

21. A method for converting an analog electrical signal to a digital value, comprising: converting an electrical input signal into an optical signal whose intensity corresponds to an analog level of said electric input signal; modulating said optical signal over a detection area so as to have a locally variable intensity as a function of position in the detection area; detecting at 2nlocations within the detection area a light intensity threshold to provide 2nbits corresponding to 2nlevels of said analog level of said electric input signal; and converting the 2nbits into an n-bit digital value.

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