Laser alignment and supporting fixture

Abstract

A device, that includes (a) a distributed feedback laser (DFL), (b) a photonics integrated circuit (PIC) that includes a PIC trench, the DFL is positioned within the PIC trench, (c) a PIC trench contact formed within the PIC trench, (d) an adaptor, wherein the adaptor is attached to a region of the PIC and to the DFL using one or more bonding elements, and (e) one or more traps for receiving excess bonding material formed during an attaching of the adaptor to at least one of the DFL and the region of the PIC, and to prevent the excess bonding material from electrically coupling the DFL distal contact to the DFL proximal contact.

Description

LASER ALIGNMENT AND SUPPORTING FIXTUREBACKGROUND OF THE INVENTION

[0001] There is a growing need to affix a laser to a photonics integrated circuit (IC) .

[0002] Figure 1 illustrates an example of a distributed feedback (DFB) laser affixed to a photonics integrated circuit (PIC).

[0003] DFB laser (DFL) 20 is an electrical bi-polar diode with a typical thickness of lOOum.

[0004] DFL 20 includes DFL distal contact 21, DFL proximal contact 22, DFL body (or bulk) 27, laser waveguide 23.

[0005] First wire bonding 11 is connected to the DFL distal contact 21.

[0006] Conductive bonding material 36 is used to attach the DFL proximal contact 22.

[0007] Second wire bonding 12 is connected to metalized pad 34 (formed on PIC) that is electrically coupled to the DFL proximal contact 22.

[0008] Index matching material 30 is located between DFL and a sidewall formed within PIC. The PIC includes a PIC waveguide 32 that is aligned with a DLF waveguide 23.

[0009] Cross sectional view (taken alone plane A-A) illustrates that due to the attachment of the DFL to the PIC, there is excess bonding material 36-1 that electrically couples the DFL distal contact 21 to the DFL proximal contact 22.

[0010] The arrangement of figure 1 suffers from some disadvantages: a. The area available for the pick and place tool on top of the DFL is very small, in the order of 200um by 600um, requiring an expensive holding tool. b. It is nearly impossible to test the DFL prior to assembly by standard means and thus, it is impossible to sort out faulty lasers. c. Wire bonding is harmful to the DFL and frequently causes defects to the laser waveguide and its operation. d. When placing the laser anode is facing up (the laser anode may include the DFL distal contact 21 or be coupled to the DFL distal contact 21) there is a temperature difference from the DFL top to the DFL bottom, causing a mechanical stress and hence laser is prone to create mode hopsand deteriorated Relative Intensity Noise (RIN), harmful to optical signal used in e.g., optical communication. e. When placing the laser anode is “face-down” (opposite position from those illustrated in figure 1), improving thermal dissipation it is most likely that the bonding material will short the laser on its side walls because distance from laser top (anode) to waveguide where short may occur is in the order of several um. Thus, laser operation gets obstructed.

[0011] In addition - when attaching a laser to an electrical contact , there is a risk of excess bonding material creeping up (see reference number 36-1) on the sides of the laser. Due to the vertical structure of the DFB, the close proximity of P and N contacts and the singulation process which is exposing the N contact at the side walls - this excess bonding material creepage is running the risk of creating an electrical short between the two polarities of the laser. See Cross section A-A in figure 2.

[0012] As indicated above - using a small laser results in having a testing problem. DFB lasers screening test done at vendor are not sufficient to predict yield loss and sort out early failures. Testing laser devices at the bare die level is impractical due to the inherently high thermal resistance which exists between a very small die and the testing fixture's substrate it is resting on.

[0013] Hence, laser performance and Bum in testing are normally done at the chip level ,post the bonding of the DFB lasers to the PIC (A chip comprising of laser and a coupled PIC - Photonic IC).

[0014] Due to the above, certain yield loss at the chip level is to be expected, particularly for applications in which multiple DFB laser source are integrated - such as DR8 or CWDM TX applications

[0015] DFB lasers screening test done at vendor are not sufficient to predict yield loss and sort out early failures.

[0016] Testing laser devices at the bare die level is impractical due to the inherently high thermal resistance which exists between a very small die and the testing fixture's substrate it is resting on.

[0017] In addition, there is trench Metallization problem. In order to bond a DFB laser inside the laser trench, a metal contact has to be created inside the trench.

[0018] Due to the trench indentation inside the wafer, it is very difficult to create a metal contact inside the laser trench, creating the metal contact at a standard CMOS process requires masking, photolithography , metallization and cleaning must beapplied. All these mentioned process create an inherent risk of wafer contamination which can be catastrophic and lead to complete wafer loss. These contaminations are also very difficult to identify since even some tens of nano-meter scale particles can lead to device failure.

[0019] Examples of some prior documents are listed below. They are not deemed to be relevant: US patent 10976488, US patent 11163126, US patent 5544184, and Packaging of laser bars, K. BOUCKE, 2011, DOE 10.1007 / 978-3-642-14177-5 13.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

[0021] FIG. 1 illustrates an example of a prior art DFL affixed to a photonics IC;

[0022] FIGs. 3-6 illustrate examples of DFL and a device; and

[0023] FIG. 7 illustrates a testing of the DFL.DETAILED DESCRIPTION OF THE DRAWINGS

[0024] The term "proximal" means closer to a photonics integrated circuit (PIC), while "distal" means further away from the PIC. In figures 2-6 proximal means bottom and distal means top.

[0025] According to an embodiment, there is provided a device that includes: a. A distributed feedback laser (DFL) that includes a DFL waveguide, a DFL distal contact (see, for example reference number 21 of figure 6), and a DFL proximal contact (see, for example reference number 22 in figure 6). b. A photonics integrated circuit (PIC) that includes a PIC trench (see, for example, reference number 81 of figure 3) wherein the DFL is positioned within the PIC trench. c. A PIC trench contact (see, for example reference number 82 of figure 3) formed within the PIC trench. d. an interface (also referred to as a shim or a fixture - see, for example, reference number 60 in figures 2 and 3), wherein when the device is assembled - the interface is attached to a region of the PIC and to theDFL using one or more bonding elements (see, for example reference number 36, 73 and 36 of figure 3). e. One or more traps for receiving excess bonding material formed during an attaching of the interface to at least one of the DFL and the region of the PIC, and to prevent the excess bonding material from electrically coupling the DFL distal contact to the DFL proximal contact.

[0026] According to an embodiment, the interface includes a first trap (see, for example, reference number 101 in figure 3) configured to receive excess bonding material formed during an attaching of the interface to the DFL.

[0027] According to an embodiment, the first trap is formed by one or more interface recesses (see, for example, reference numbers 61 and 62 in figure 3). The interface includes a primary protrusion (see, for example, reference number 66 in figure 2) that is attached to the DFL distal contact, and secondary protrusions (see, for example, reference numbers 64 and 65 in figure 3) that are attached to the region of the PIC.

[0028] According to an embodiment, the device includes a second trap (see, for example, reference number 102 in figure 3) configured to receive excess bonding material formed during an attaching of the interface to the PIC region.

[0029] According to an embodiment, the second trap includes a grating of metal and dielectric elements (see, for example, elements of the grating - reference numbers 51, 52, 53 and 54 in figure 5).

[0030] According to an embodiment, the second trap includes one or more capillary force conduits - the conduits are formed by dielectric element denoted 52 in figure 5).

[0031] According to an embodiment, the device includes a third trap (see, for example, reference number 103 in figure 6) that is configured to receive excess bonding material formed during an attaching of the DFL to the PIC trench contact.

[0032] According to an embodiment, the third trap is formed in the PIC trench (see, for example, reference number 81 in figure 6) and includes one or more additional recesses (see, for example, reference numbers 88 and 89 in figure 6) formed at one or more sides of the PIC trench contact.

[0033] According to an embodiment, the interface includes an interface distal portion and an interface proximal portion that is electrically coupled to the interface distal portion, wherein the interface proximal portion is attached to the DFL distal contact.

[0034] According to an embodiment, the area of a distal surface of the interface distal portion exceeds an area of the DFL. This difference allows to easily contact the distalsurface - even when the proximal surface is small. According to an embodiment, the difference assists in providing electrical signals to the DFL distal contact - and allows to easily test the DFL.

[0035] According to an embodiment, the device includes an index matching material (see, for example, reference number 91 in figure 6) that is located between the DFL waveguide output and the PIC trench.

[0036] According to an embodiment, the device includes a fourth trap (see, for example, reference number 104 in figure 6) that is configured to receive excess index matching material formed during a provision of the index matching material. In figure 6, the fourth trap 104 includes sidewalls 99-1 and 99-2 located at both sides of silicon fin 93 - and spaced apart from the silicon fin 93 - to form two cavities 98-1 and 98-2 for receiving the excess index matching material. The silicon fin includes a part of the PIC waveguide.

[0037] According to an embodiment, the interface comprises an interface distal portion, a primary protrusion and secondary protrusions.

[0038] According to an embodiment, the primary protrusion and secondary protrusions extend from the distal portion (see, for example, reference number 65 in figure 2 ). The distal portion 65 includes a distal surface 95-1. The DFL can be tested before being attached to the PIC by contacting the distal surface, as shown in figure 7.

[0039] According to an embodiment, the primary protrusion is longer than the secondary protrusions.

[0040] According to an embodiment, a lateral distance (measured from the centers of the secondary protrusions) between the secondary protrusions exceeds a width of the PIC trench.

[0041] There is provided a solution (device and / or method) regarding an adaptor such as a fixture aimed at assisting in the alignment and fixing a DFL in its place on a PIC during the process of a butt coupling, to a tapered wave-guide in the PIC.

[0042] The solution, once applied, obtains repeatedly a production-line high-yield standard, an alignment of a light beam emerging out of the side edge of a DFL into a PIC waveguide to achieve high coupling efficiency, under various mechanical, temperature and other environmental stress, without a degradation in the coupling efficiency, without creating conditions for unacceptable mode hoping in the DFL and most importantly keeping the RIN at the required level.

[0043] To achieve this goal a high precision pick-and-place tool is used.

[0044] After an acceptable alignment result is achieved, an attachment process of the DFL to its place in the PIC is subsequently followed.

[0045] Figure 2 is an example of an adaptor 60 that includes a distal portion 65 having a distal surface 65-1 that may be contacted by a probe, and a proximal portion that is closer to the DFL and includes primary protrusion 66, secondary protrusions 64 and 65, and recesses or channels (such as side channels 61 and 62)) formed between the protrusions.

[0046] Figure 2 Also illustrates DFL 20 and bonding material 37.

[0047] Figures 3 and 4 illustrate a cross sectional view and a top view of the bonding of a DFL on a PIC, figure 5 illustrates a cross sectional view and a top view of a part of a second trap (denoted 102 in figure 3).

[0048] Figure 5 illustrates a second trap 102 that includes a bonding area on the PIC that forms a cavity. In this design the bonding area fabricated from at least one metal layer composed of internal rectangular pad shape part and a surrounding rectangular ring shape part. In another design the metalized Pad is covered by a passivation dielectric stack fabricated from nit and ox layers (shown at Fig. 4D). The later passivation layer is etched and is opened above the metal layer creating a patterned topography area composed of a top dielectric elements (denoted 52 and 54) and a bottom exposed metal layer (denoted 51 and 53).

[0049] This “grating” design can be adjusted in dimensions so that the wetting of the conductive bonding material drop is tightly controlled to a desired size , shape and height - enabling highly precise and repeatable Bonding in place procedure.

[0050] This design ensures also that the PIC trench , the DFL waveguide and all other area on the PIC are free from the UV Epoxy glue residues - which allows better precision, avoiding conductive bonding material “mixing” during the bonding process and enables the use of non-transparent UV conductive bonding material since the UV is guaranteed to not be in contact with the DFL facet Note that In this particular design that shim is bonded along its two sides on the Si chip, as shown in figures 3 and 4.

[0051] The fixture, the DFL and the PIC may be assembled in the following manner: a. Prior to alignment and attachment of the DFL to the Si chip, a DFL is attached to a customized fixture, providing mechanical support, electrical contact and an effective dissipation route to the heat generated by the DFL . The active region of the DFL may be attached either in proximity to the fixture or the other side.b. DFL - fixture attachment can be achieved by standard industry bonding methods for active semiconductor components. c. Two channels are fabricated in the fixture and once attached to the DFL , are located (at least in part) to the sides of the DFL . These channels allow for excess of bonding material to propagate in the channels volume - instead of contaminating the sidewalls of the DFL - (known in the industry as bonding “fillet”). Contaminated DFL sidewall is unwanted as it leads to electrical-short of the active region. d. Sorting out failed devices is conveniently done in this stage of the process. Using the fixture, it is possible to touch using electrical probes on the fixture and on the cathode side of the DFL and activate the DFL fortesting. e. Next, an alignment procedure is performed by using an alignment signal produced by either the activated DFL itself, or by an external source while the DFL is passive. Once a satisfactory alignment signal is obtained the unit is bonded in place. f. In this stage a transparent index matching epoxy may be applied between the DFL and the SiN waveguide as some applications require that. See Fig. 6.

[0052] It should be noted that recesses that differ from channels may be formed in the fixture.

[0053] The fixture can be made from various materials - for example: a. A material that exhibits high electrically conductive, providing good Ohmic contact when tested from face to face of the fixture. For that purpose, any metal or highly conductive metalized semiconductor e.g. Si are options. b. It may have a thermal expansion coefficient matched to that of the DFL c. For example - using InP or AIN may be used because they have their coefficient of thermal expansion (CTE, 4.6 ppm / C°) matched to the InP based DFL . d. In some applications it may be beneficial to use AIN material thanks to its superb thermal conductivity.

[0054] Figure 6 illustrates a solution that includes preparing a dedicated volume that will serve as an expansion buffer to which the bonding scrap can expand: a. In the wafer manufacturing level, cavities are etched around the location of the DFL on the PIC leaving a raised ridge on which the DFL is placed. b. Cavities are etched from 3 sides of the DFL , see figure 6. c. On the front side of the DFL , where the DFL output is aimed at the waveguide, a recess in the wall facing the DFL is etched, leaving an elongated taper ridge (also referred to a silicon fin) in the center of the wall to support the waveguide. Thus, when placing the DFL , bonding scrap from the front of the DFL can expand into the sides of this taper ridge.

[0055] All the drawings may be off scale or may not be off scale. Any values illustrated in any of the figures is just an example.

[0056] For example - the maximal thickness of the fixture may range between 100 micrometer and 500 micrometer. Yet for another example - the width of the tunnels may range between 150 and 390 micrometer, - for example may range between 200 and 325 micrometer. The thickness of the coating may range between 0. 1 and 35 micrometer - for example may be 20 micrometer.

[0057] In a further embodiment, the etching direction of the cavities of the third trap is vertical with respect to the PIC trench contact, 82 area, shown at figure 6. As previously disclosed theses cavities areas are formed in the PIC trench on one or more sides of the PIC trench contact (see, for example, reference number 81 in figure 6) and includes one or more additional recesses (see, for example, reference numbers 88 and 89 in figure 6) on one or more sides of the PIC trench contact. That can be done by an anisotropic etching of Si at the around the area of the PIC trench contact in etching angles which can vary from 90 to 45 degrees with respect to PIC trench contact. In this design the DFL proximal contact 22 area can be smaller equal or larger with respect to the area of the PIC trench contact 82, and a results, its size is not limited to the sizes of the area of the PIC trench contact 82.

[0058] Figure 7 illustrates an example of a DFL being tested by probes 101, 102 and 103 that are in electrical contact with the secondary protrusions 64 and 65 of the adaptor and with the DFL distal contact 21.

[0059] In the foregoing detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will beunderstood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

[0060] The subject matter regarding the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

[0061] It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

[0062] Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

[0063] Any reference in the specification to a method should be applied mutatis mutandis to a device capable of executing the method.

[0064] Any reference in the specification to a device should be applied mutatis mutandis to a method that may be executed by the device.

[0065] In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0066] Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

[0067] The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.

[0068] Although specific conductivity types or polarity of potentials have been described in the examples, it will be appreciated that conductivity types and polarities of potentials may be reversed.

[0069] Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein may be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

[0070] Furthermore, the terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

[0071] Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architecturesdepicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

[0072] Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

[0073] Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0074] Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

[0075] However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

[0076] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or otherprioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

[0077] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

WE CLAIM1. A device, comprising: a distributed feedback laser (DFL) that comprises a DFL waveguide output, a DFL distal contact, and a DFL proximal contact; a photonics integrated circuit (PIC) that comprises a PIC trench, wherein the DFL is positioned within the PIC trench; a PIC trench contact formed within the PIC trench; an adaptor; wherein the adaptor is attached to a region of the PIC and to the DFL using one or more bonding elements; and wherein the device comprises one or more traps for receiving excess bonding material of the one or more bonding elements that was formed during an attaching of the adaptor to at least one of the DFL and the region of the PIC, and to prevent the excess bonding material from electrically coupling the DFL distal contact to the DFL proximal contact.

2. The device according to claim 1, wherein the one or more traps comprise a first trap that is formed in the adaptor, wherein the first trap is configured to receive excess bonding material formed during an attaching of the adaptor to the DFL.

3. The device according to claim 2, wherein the first trap is formed by one or more adaptor recesses, wherein the adaptor further comprises a primary protrusion that is attached to the DFL distal contact, and secondary protrusions that are attached to the region of the PIC.

4. The device according to claim 1, wherein the one or more traps comprise a second trap that is configured to receive excess bonding material formed during an attaching of the adaptor to the PIC region.

5. The device according to claim 4, wherein the second trap comprises a grating of metal and dielectric elements formed on the PIC region.

6. The device according to claim 4, wherein the second trap comprises one or more capillary force conduits.

7. The device according to claim 1, further comprising a third trap that is configured to receive excess bonding material formed during an attaching of the DFL to the PIC trench contact.

8. The device according to claim 7, wherein the third trap is formed in the PIC trench and comprises one or more additional recesses formed at one or more sides of the PIC trench contact.

9. The device according to claim 1, wherein the adaptor comprises an adaptor distal portion and an adaptor proximal portion that is electrically coupled to the adaptor distal portion, wherein the adaptor proximal portion is attached to the DFL distal contact.

10. The device according to claim 9, wherein an area of a distal surface of the adaptor distal portion exceeds an area of a distal surface of the DFL.

11. The device according to claim 1 , further comprising an index matching material that is located between the DFL waveguide output and the PIC trench.

12. The device according to claim 11, further comprising a fourth trap that is configured to receive excess index matching material formed during a provision of the index matching material.

13. The device according to claim 1, wherein the adaptor comprises an adaptor distal portion, a primary protrusion and secondary protrusions.

14. The device according to claim 13, wherein the primary protrusion and secondary protrusions extend from the distal portion.

15. The device according to claim 13, wherein the primary protrusion is longer than the secondary protrusions.

16. The device according to claim 13, wherein a lateral distance between the secondary protrusions exceeds a width of the PIC trench.

17. The device according to claim 1 wherein a bonding material attaching the adaptor to the DFL is electrically conductive.

18. The device according to claim 1 wherein a bonding material attaching the adaptor to the PIC region is electrically insulative.

19. A kit, comprising: a distributed feedback laser (DFL) that comprises a DFL distal surface, a DFL waveguide output, a DFL distal contact, and a DFL proximal contact; and an adaptor that comprises a first trap, an adaptor distal portion, a primary protrusion and secondary protrusions, wherein the first trap is configured to receive excess bonding material formed during an attaching of the adaptor to the DFL and prevent the excess bonding material from electrically coupling the DFL distal contact to the DFL proximal contact; andwherein the adaptor is wider than the DFL.

20. A method for assembling a device, the method comprising:(a) first attaching an adaptor to a distributed feedback laser (DFL) that comprises a DFL waveguide output, a DFL distal contact, and a DFL proximal contact;(b) first receiving, by a first trap, excess bonding material of a bonding element that was formed during the first attaching;(c) positioning the DFL within a photonics integrated circuit (PIC) trench of a PIC, and aligning the DFL waveguide to a PIC waveguide;(d) second attaching the adaptor to a PIC region located outside the PIC trench; and(e) second receiving, by a second trap, excess bonding material of a bonding element that was formed during the second attaching; and wherein steps (b) and (e) prevent any excess bonding material from electrically coupling the DFL distal contact to the DFL proximal contact.

21. The method according to claim 20, further comprising testing the DFL, using the adaptor, between a completion of the first receiving and before the second attaching.

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