Solar cell, solar cell semi-finished product and method for producing a solar cell

Abstract

The invention relates to a solar cell, to a solar cell semi-finished product and to a method for producing a solar cell. In particular, the invention relates to a solar cell and a solar cell semi-finished product, which each have a substrate (1), a tunnel oxide layer (2) arranged on the substrate (1) and a rear layer stack arranged thereon, which has at least two phosphorus-doped silicon layers (3, 5, 6) the respective phosphorus contents of which differ from one another, and a barrier layer (4) which is arranged between the at least two phosphorus-doped silicon layers (3, 5, 6) such that a doping profile with at least two doping stages is formed, wherein within each of the at least two doping stages the phosphorus content remains substantially constant along a layer thickness of the respective phosphorus-doped silicon layers (3, 5, 6).

Description

[0001] Title: Solar cell, solar cell semi-finished product and method for producing a solar cell

[0002] Description:

[0003] The invention relates to a solar cell, a solar cell semi-finished product, and a method for producing a solar cell. In particular, the invention relates to a solar cell and a solar cell semi-finished product, each comprising a substrate, a tunnel oxide layer arranged on the substrate, and a rear-side layer stack arranged thereon, which layer stack comprises a phosphorus-doped silicon layer. It also relates to a method in which a phosphorus-doped silicon layer is deposited on a substrate.

[0004] EP 3 685 446 A1 describes a solar cell comprising a silicon substrate and a layer stack arranged thereon comprising a thin oxide layer and a polysilicon layer or polysilicon layer, wherein the polysilicon layer is constantly doped across its thickness and the silicon substrate is gradually doped near the rear surface. The solar cell further comprises a rear electrode in the form of a metal contact which locally penetrates the polysilicon layer. Weaknesses of such a solar cell are - with thin polysilicon layers - the unsatisfactory transverse conductivity and poor contact with the metal contact or a paste used to produce it. However, polysilicon layers which are as thin as possible are desirable in order to achieve low absorption losses and a high current (Isc).Improving the contact resistance by high phosphorus doping over the entire polysilicon layer thickness will also lead to absorption losses.

[0005] It is an object of the invention to provide a solar cell and a method for producing a solar cell having a backside layer stack with improved transverse conductivity and improved contact of the backside layer stack to the backside electrode or its manufacturing paste. According to the invention, this object is achieved by a solar cell having the features of patent claim 1, a solar cell semi-finished product having the features of patent claim 5, and a method having the features of patent claim 6. Advantageous developments and modifications are specified in the subclaims.

[0006] The backside layer stack, in particular the phosphorus-doped polysilicon layers, are characterized by a low sheet resistance and / or a high transverse conductivity with, at the same time, good contactability by the backside electrode.

[0007] Since after the deposition of the a-Si:H(n) layers or phosphorus-doped, amorphous silicon layers on the substrate, a so-called annealing process is carried out, i.e. exposure to a temperature of, for example, approximately 800 to 950°C in order to produce a poly-Si(n) layer from the respective a-Si:H(n) layer so that hydrogen diffuses out and Si crystals form, it is not sufficient to deposit a-Si:H(n) sublayers with different phosphorus contents, since phosphine has a high mobility due to the increased temperature during annealing. Without the barrier layer, a flat phosphorus profile or a phosphorus gradient will develop instead of the stepped phosphorus profile after annealing. The barrier layer does not allow the phosphorus to pass through, or at least only to a greatly reduced extent, so that a doping profile with at least two levels is created.By means of the barrier layer, larger doping differences in the phosphorus-doped, amorphous silicon layers separated by the barrier layer can therefore be achieved during annealing by preventing or at least minimizing diffusion of the phosphorus from one of the phosphorus-doped, amorphous silicon layers into the other.

[0008] The invention relates to a solar cell comprising a substrate with a tunnel oxide layer and a rear-side layer stack arranged thereon, which has at least two phosphorus-doped, polysilicon layers whose respective phosphorus content differs from one another, and a barrier layer which is arranged between the at least two phosphorus-doped, polysilicon layers, so that a doping profile with at least two doping levels is formed, wherein within each of the at least two doping levels the phosphorus content is substantially constant along a layer thickness of the respective polysilicon layers.

[0009] The solar cell is designed as a TopCon solar cell. The advantages of n-type TopCon solar cells are relatively low degradation and relatively high efficiency. The solar cell is preferably designed as a bifacial TopCon solar cell.

[0010] In a preferred embodiment, the barrier layer is formed as an oxygen-containing layer. More preferably, the barrier layer is formed as an oxygen-rich intrinsic silicon layer. Alternatively, more preferably, the barrier layer is formed as an oxygen-rich doped layer. Before annealing, the barrier layer can be formed as an oxygen-rich amorphous silicon layer or a-SiOx layer. The higher the oxygen content in the a-SiOx layer, the more electrically conductive phosphorus is bound. The barrier layer is preferably electrically conductive. The phosphorus-doped silicon layer arranged on the side of the barrier layer facing the substrate can be amorphous or intrinsic before annealing.

[0011] Preferably, the respective phosphorus content of the at least two phosphorus-doped polysilicon layers increases with increasing distance from the substrate. The inventors have found that the phosphorus-doped, amorphous silicon layers, which are present after annealing as polysilicon or poly-Si(n) layers, which were deposited with a relatively low PHB FUSS and have a relatively low phosphorus content, have a surprisingly lower sheet resistance and better transverse conductivity than the poly-Si(n) layers deposited with a relatively high PHB FUSS and have a relatively high phosphorus content. However, the poly-Si(n) layers deposited with the relatively low PHB FUSS exhibit a relatively high contact resistance with respect to the backside metallization, which is reflected in a relatively lower fill factor.Therefore, it is advantageous to design the solar cell with increasing phosphorus content in the at least two phosphorus-doped polysilicon layers with increasing distance from the substrate. A distinction must be made here between electrically conductive phosphorus, which is detectable in ECV (electrochemical capacitance voltage) measurements, and a total phosphorus content, which can be determined using ToF SIMS (Time-of-Flight Secondary Ion Mass Spectrometry) measurements.

[0012] The solar cell can have two, three or more phosphorus-doped polysilicon layers, each separated by a barrier layer. The phosphorus-doped polysilicon layer furthest from the substrate preferably has the highest phosphorus content to provide good contact with the backside electrode, while the phosphorus-doped polysilicon layer closest to the substrate preferably has the lowest phosphorus content to provide a depleted source for tail formation, and an intermediate phosphorus-doped polysilicon layer preferably has an intermediate phosphorus content to provide maximum transverse conductivity. A tail means phosphorus that has diffused into the substrate, such as a Si wafer, after annealing, in particular into a region up to about 1000 nm from the substrate surface or SiOx layer (tunnel oxide layer).

[0013] A layer thickness of the tunnel oxide layer is preferably 1 to 3 nm. A layer thickness of the barrier layer is preferably 5 nm to 30 nm. A layer thickness of the at least two phosphorus-doped polysilicon layers is preferably in the range of 20 nm to 60 nm. A layer thickness of the rear-side layer stack is preferably in the range of 50 to 150 nm.

[0014] The invention further relates to a solar cell semi-finished product comprising a substrate, a tunnel oxide layer arranged on the substrate, and a rear-side layer stack arranged thereon, which has at least two phosphorus-doped, amorphous silicon layers whose respective phosphorus contents differ from one another, and an oxygen-rich barrier layer arranged between the at least two phosphorus-doped, amorphous silicon layers, so that a doping profile with at least two doping levels is formed, wherein within each of the at least two doping levels, the phosphorus content is essentially constant along a layer thickness of the respective phosphorus-doped, amorphous silicon layers. The solar cell according to the invention can be produced from the solar cell semi-finished product by means of annealing.

[0015] The invention further relates to a method for producing a solar cell, comprising the following steps: a) providing a substrate, b) producing a tunnel oxide layer on a back side of the substrate, c) depositing a phosphorus-doped silicon layer on a back side of the substrate using a first phosphine partial pressure, d) depositing a barrier layer using oxygen or an oxygen-containing molecule on the phosphorus-doped, amorphous silicon layer, e) depositing a phosphorus-doped, amorphous silicon layer on the barrier layer using a further phosphine partial pressure which is different from the first phosphine partial pressure, and f) exposing the substrate together with the back layer stack to a temperature in the range from 800 to 950°C.

[0016] Step a) preferably comprises providing a silicon substrate. The silicon substrate is preferably formed as an n-type Si wafer with a thickness of approximately 150-180 pm and is doped relatively consistently across its thickness. In step b), an interface or tunnel oxide is deposited, which is important for adjusting the phosphor profile to be generated in steps c) to e). It also forms a barrier for the phosphor. The tunnel oxide layer is preferably SiO x The tunnel oxide layer is preferably produced as a plasma oxide using a low-pressure plasma or as a thermal oxide, e.g., in a tube furnace at a temperature > 500°C, or as a wet-chemical oxide in an aqueous solution containing ozone or H2O2.

[0017] In step f), the Si:H(n) layers deposited in steps c) and e) are converted into poly-Si(n) layers by crystallization. A two-stage doping profile is present across the entire thickness of the backside layer stack with the phosphorus-doped polysilicon layers. The phosphorus-doped layer deposited in step c) can be intrinsically or preferably amorphous. The phosphorus-doped layer deposited in step e) is amorphous.

[0018] In a preferred embodiment, steps c) and e) are carried out using SiH4, H2, and PH3. With the resulting rear-side layer structure, different requirements for the layer can be realized, such as good contact with a rear-side electrode, where a high phosphine partial pressure is advantageous, and good transverse conductivity, where a low phosphine partial pressure is advantageous. Preferably, the phosphine partial pressure in step c) is less than 1% relative to SiH4 and H2. Preferably, the phosphine partial pressure in step e) is more than 1% relative to SiH4 and H2. For good transverse conductivity of a silicon layer, a rather low phosphine partial pressure of, for example, approximately 15-25% of an initial value (<1%) is advantageous during the deposition of the amorphous, doped silicon (a-Si(n)).The initial value preferably refers to a process in which a predetermined PH3 flow is started, representing the initial value and defined as 100%, and then preferably reduced in a varied manner, with the varied value being defined in relation to the initial value. For example, a PECVD process is carried out in which a flow of 2000 sm PH3, which is diluted to 5% PH3 in H?, is started, this value representing the initial value of 100%, and then reduced to a flow of 500 sm PH3, this value being 25% of the initial value.

[0019] The PH3 partial pressure is preferably varied between 0.6 and 1.5%.

[0020] On the other hand, to achieve a low contact resistance of the back electrode paste used to produce the back electrode on the phosphorus-doped, amorphous silicon layer, it is advantageous to incorporate as much phosphine as possible into this layer, which requires a high phosphine partial pressure of, for example, > 1% during the deposition of the a-Si(n) or a-Si:H(n). The phosphine partial pressure, i.e. the PH3 Flux, during the deposition in steps c) and e) influences the crystal size of the phosphorus-doped, amorphous silicon layers. The higher the PH3 Flux, the smaller the crystal size. For example, a typical crystal size is 0.1 to 0.3 pm at a phosphine partial pressure of 1.5%, whereas the typical crystal size at a phosphine partial pressure of 0.8% is only 0.2 to 0.6 pm, which can increase the transverse conductivity of up to 20%.

[0021] Preferably, in steps b) - e), a deposition temperature is 300 to 500 °C, preferably 450 °C. Preferably, in steps c) - e), a pressure is 0.5 to 10 mbar, preferably 2 mbar.

[0022] Preferably, step d) is carried out using SiH4, H2 and an oxygen-containing molecular gas. The oxygen-containing gas is preferably selected from the group consisting of N2O, CO2, NO2, NO and / or CO. Using these process gases, a layer is deposited that provides a good phosphorus barrier. Preferably, in step d), an oxygen-containing layer such as an oxygen-containing intrinsic or amorphous silicon layer (a-SiO x:H). In a preferred embodiment, step d) is further carried out using phosphine or PH3, wherein the amount of PH3 used in step d) is less than the amount of PH3 used in steps c) and e). This results in electrical conductivity of the barrier layer. The barrier layer is preferably formed as a doped oxygen-containing amorphous silicon layer (a-SiO x (n):H) deposited.

[0023] In a preferred embodiment, step c) comprises the following sub-steps: c1) depositing the phosphorus-doped silicon layer on the substrate during a predetermined first time period and / or until a predetermined first layer thickness is reached, c2) exposing the substrate and the phosphorus-doped silicon layer to a plasma using an uncoating process gas during a predetermined second time period or interrupting the plasma for approximately 10 - 60 seconds, c3) continuing the deposition of the phosphorus-doped silicon layer on the substrate during a predetermined third time period and / or until a predetermined second layer thickness of the phosphorus-doped silicon layer is reached.

[0024] This procedure results in a seed layer produced by steps c1) and c2). The seed layer deposited in step c1) is relatively thin compared to the layer produced in step c3) and has, for example, a layer thickness of 1 nm. The layer produced in step c3), in contrast, has a layer thickness of 20 nm or more. By producing the seed layer, the phosphorus doping profile and the crystallinity of the poly-Si(n) layer produced in step f) can be positively influenced.

[0025] In a preferred embodiment, the process is carried out in a PECVD (plasma-enhanced chemical vapor deposition) system or an LPCVD (low-pressure chemical vapor deposition) system. The PECVD or LPCVD system is preferably designed as a tube furnace. By using a tube PECVD or tube LPCVD system, the layers produced in the respective steps can be deposited in their respective sequence by temporally changing the process gas flow, without having to move the substrate with its rear-side layer stack or interrupting the vacuum.

[0026] The process is preferably carried out in a PECVD system. In a preferred embodiment, a pulsed, capacitively coupled low-pressure plasma is ignited between the substrates, preferably in the frequency range of 40 to 400 kHz and / or with a power range of 2 to 20 kW.

[0027] Preferably, step a) comprises providing a plurality of substrates arranged in a wafer boat. The substrates to be coated are preferably loaded into a graphite wafer boat, in which the substrates are positioned opposite one another in pockets and contacted by means of contact pins. This allows for savings in manufacturing costs. The substrate is preferably a wafer, more preferably a silicon wafer.

[0028] Preferably, steps d) and e) are repeated alternately one after the other, with the phosphine partial pressure increasing with the increasing number of repeated steps e). As a result, the phosphorus content of the layers produced in steps e) increases with increasing distance from the substrate. Preferably, the respective phosphorus content of the phosphorus-doped silicon layers deposited in steps c) and e) increases with increasing distance from the substrate. Step d) can be repeated multiple times.

[0029] Preferably, after step f), a SiNx:H layer is applied as a passivation and RS anti-reflective layer, and a backside metallization paste is applied to create a backside electrode on the backside layer stack. Further advantages and properties of the invention are explained with reference to preferred embodiments described below. However, the figures are not drawn to scale, but are to be understood purely schematically and as examples. They show:

[0030] Fig. 1 is a cross-sectional view of a solar cell according to the invention;

[0031] Fig. 2 shows a doping profile of the solar cell shown in Fig. 1;

[0032] Fig. 3 is a cross-sectional view of another solar cell according to the invention;

[0033] Fig. 4 is a flowchart of a method according to the invention; and Fig. 5 is a flowchart of another method according to the invention.

[0034] Fig. 1 shows a cross-sectional view of a solar cell according to the invention. The solar cell comprises a substrate 1 with a backside layer stack. A tunnel oxide layer 2 is also arranged between the substrate 1 and the backside layer stack. The backside layer stack comprises two phosphorus-doped polysilicon layers 3, 5 and a barrier layer 4 arranged between the two phosphorus-doped polysilicon layers 3, 5. The two phosphorus-doped polysilicon layers 3, 5 each have a different phosphorus content.

[0035] The substrate 1 is a Si wafer. The tunnel oxide layer 2 is made of SiOx with a layer thickness of 1-3 nm and is non-conductive. The two phosphorus-doped polysilicon layers 3 and 5 have a layer thickness of 70 nm and 30 nm, respectively. The barrier layer 4 has a layer thickness of 10 nm and is formed as oxygen-doped / enriched poly-SiOx.

[0036] A solar cell semi-finished product according to the invention corresponds to the solar cell shown in Fig. 1, with the difference that instead of the two phosphorus-doped polysilicon layers 3, 5, it has two phosphorus-doped, amorphous silicon layers 3, 5. The phosphorus-doped, amorphous silicon layer 3 was deposited with a relatively low phosphine partial pressure, while the phosphorus-doped, amorphous silicon layer 5 was deposited with a relatively high phosphine partial pressure. The barrier layer 4 separates the two phosphorus-doped, amorphous silicon layers 3, 5 with a phosphorus barrier made of nitrous oxide.

[0037] Fig. 2 shows a doping profile of the solar cell shown in Fig. 1. Shown are the phosphorus content vs. the layers of the solar cell. The two phosphorus-doped polysilicon layers 3, 5 each have a different phosphorus content, forming a doping profile with two doping levels. Within each of the two doping levels, the phosphorus content is essentially constant along a layer thickness of the respective silicon layers 3, 5. The phosphorus-doped polysilicon layer 5 has a higher phosphorus content than the phosphorus-doped polysilicon layer 3, with the barrier layer 4 forming a gradient between the two doping levels.

[0038] Fig. 3 shows a cross-sectional view of another solar cell according to the invention. The solar cell shown in Fig. 3 corresponds to the solar cell shown in Fig. 1 with the difference that the rear-side layer stack further comprises a further phosphorus-doped, polysilicon layer 6, which is separated from the phosphorus-doped polysilicon layer 5 by a further barrier layer 4. In addition, the solar cell has an RSSiNx layer 7 on the phosphorus-doped, polysilicon layer 6 and a rear-side electrode 8, which is arranged in a strip shape on a side of the RSSiNx layer 7 facing away from the substrate 1. The respective phosphorus content of the three phosphorus-doped silicon layers 3, 5, 6 increases with increasing distance from the substrate 1.

[0039] Fig. 4 shows a flow diagram of a method according to the invention. The method has the following steps in the specified order: First, step a) providing a substrate is carried out. Step a) is followed by step b) in which a tunnel oxide layer is produced on a back side of the substrate, e.g. a plasma oxide by means of a low-pressure plasma or a thermal oxide, e.g. in a tube furnace at a temperature > 500°C or a wet-chemical oxide in ozone or H2O2-containing aqueous solution. Step b) is followed by step c) depositing a phosphorus-doped, amorphous or intrinsic silicon layer on a back side of the substrate, ie on the tunnel oxide layer using a first phosphine partial pressure. Step c) is followed by step d) depositing a barrier layer on the phosphorus-doped, amorphous or intrinsic silicon layer.Step d) is followed by step e) of depositing a phosphorus-doped, amorphous silicon layer on the barrier layer using a further phosphine partial pressure that differs from the first phosphine partial pressure. Step e) is followed by step f) of exposing the substrate, including the rear-side layer stack, to a temperature in the range of 800 to 950°C. The solar cell shown in Fig. 1 can be produced using the process shown in Fig. 4.

[0040] Fig. 5 shows a flowchart of another method according to the invention. The method shown in Fig. 5 corresponds to the method shown in Fig. 4, with the difference that steps d) and e) are repeated between steps e) and f) shown in Fig. 4, and optionally, a step g) of depositing an RS SiNx layer and a step h) of applying a backside electrode paste to create a backside electrode are performed. The solar cell shown in Fig. 3 can be produced using the method shown in Fig. 5.

[0041] List of reference symbols:

[0042] 1 substrate

[0043] 2 Tunnel oxide layer 3 Phosphorus-doped silicon layer

[0044] 4 Barrier layer

[0045] 5 additional phosphorus-doped silicon layers

[0046] 6 additional phosphorus-doped silicon layers

[0047] 7 RS SiNx layer 8 backside electrode

Claims

Patent claims:

1. A solar cell comprising a substrate (1), a tunnel oxide layer (2) arranged on the substrate (1), and a rear-side layer stack arranged thereon, which has at least two phosphorus-doped, polysilicon layers (3, 5, 6), the respective phosphorus contents of which differ from one another, and an oxygen-rich barrier layer (4) arranged between the at least two phosphorus-doped, polysilicon layers (3, 5, 6), such that a doping profile with at least two doping levels is formed, wherein within each of the at least two doping levels the phosphorus content is substantially constant along a layer thickness of the respective phosphorus-doped, polysilicon layers (3, 5, 6).

2. Solar cell according to claim 1, characterized in that the barrier layer (4) is formed as an oxygen-rich intrinsic silicon layer or an oxygen-rich doped silicon layer.

3. Solar cell according to claim 1 or 2, characterized in that the respective phosphorus content of the at least two phosphorus-doped polysilicon layers (3,5,6) increases with increasing distance from the substrate (1).

4. Solar cell according to one of the preceding claims, characterized in that a layer thickness of the barrier layer (4) is 5 nm to 30 nm, a layer thickness of the at least two phosphorus-doped polysilicon layers (3, 5, 6) is each in the range from 20 nm to 60 nm and / or a layer thickness of the rear-side layer stack is in the range from 50 to 150 nm.

5. Solar cell semi-finished product, comprising a substrate (1), a tunnel oxide layer (2) arranged on the substrate (1) and a rear-side layer stack arranged thereon, which comprises at least two phosphorus-doped, amorphous silicon layers (3, 5, 6) whose respective phosphorus contents differ from one another, and an oxygen-rich barrier layer (4) which is arranged between the at least two phosphorus-doped, amorphous silicon layers (3, 5, 6), so that a doping profile with at least two doping levels is formed, wherein within each of the at least two doping levels the phosphorus content is substantially constant along a layer thickness of the respective phosphorus-doped, amorphous silicon layers (3, 5, 6).

6. A method for producing a solar cell, comprising the following steps a) providing a substrate (1), b) producing a tunnel oxide layer (2), c) depositing a phosphorus-doped silicon layer (3) on a back side of the substrate (1) using a first phosphine partial pressure, d) depositing a barrier layer (4) using oxygen or an oxygen-containing molecule on the phosphorus-doped silicon layer (3), e) depositing a phosphorus-doped, amorphous silicon layer (5) on the barrier layer (4) using a further phosphine partial pressure which is different from the first phosphine partial pressure, and f) exposing the substrate together with the back layer stack to a temperature in the range from 800 to 950°C.

7. The method according to claim 6, characterized in that steps c) and e) are carried out using SiH4, H? and PH3.

8. The method according to claim 6 or 7, characterized in that step d) is carried out using SiH4, H2 and an oxygen-containing gas selected from the group consisting of N2O, CO2, NO2, NO and / or CO.

9. The method according to claim 8, characterized in that step d) is further carried out using PH3, wherein an amount of PH3 used in step d) is less than an amount of PH3 used in each of steps c) and e).

10. The method according to one of claims 6 to 9, characterized in that step c) has the following sub-steps: c1) depositing the phosphorus-doped silicon layer (3) on the substrate (1) during a predetermined first time period and / or until a predetermined first layer thickness is reached, c2) exposing the substrate (1) and the phosphorus-doped silicon layer (3) to a plasma using an uncoating process gas during a predetermined second time period or interrupting the plasma for approximately 10 - 60 seconds, c3) continuing the deposition of the phosphorus-doped silicon layer (3) on the substrate (1) during a predetermined third time period and / or until a predetermined second layer thickness of the phosphorus-doped silicon layer (3) is reached.

11. Process according to one of claims 6 to 10, characterized in that in steps b) to e) the deposition temperature is 300 to 500 °C, preferably 450 °C.

12. Method according to one of claims 6 to 11, characterized in that it is carried out in a PECVD or LPCVD system.

13. Method according to one of claims 6 to 12, characterized in that step a) comprises providing a plurality of substrates (1) arranged in a wafer boat.

14. The method according to any one of claims 6 to 13, characterized in that steps d) and e) are repeated alternately one after the other, the phosphine partial pressure increasing with increasing number of repeated steps e).

15. Method according to one of claims 6 to 14, characterized in that a respective phosphorus content of the phosphorus-doped silicon layers (3, 5, 6) deposited in steps c) and e) increases with increasing distance from the substrate (1).

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