Pulse output device, laser system and method for outputting pulses
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- TRUMPF LASER SE
- Filing Date
- 2024-07-11
- Publication Date
- 2026-05-20
AI Technical Summary
Existing pulse output devices and laser systems experience significant jitter when generating pulses triggered by external signals, making synchronization with other systems difficult and costly to mitigate, especially when using high clock rates.
A pulse output device that synchronizes the clock signal with the trigger signal by stopping and restarting the clock generator or clock divider, allowing the digital pulse generator to sample the trigger event asynchronously, thereby reducing jitter without increasing the clock rate of the digital pulse generator.
This approach significantly reduces jitter to less than 300 ps, enabling precise synchronization of laser pulses with external triggers and improving the 'pulse-on-demand' operation of laser systems, allowing for precise timing and reduced operational costs.
Smart Images
Figure EP2024069631_16012025_PF_FP_ABST
Abstract
Description
[0001] Pulse output device, laser system and method for outputting pulses
[0002] The present invention relates to a pulse output device, comprising: a digital pulse generator for outputting at least one pulse triggered by a trigger signal, wherein the digital pulse generator has a trigger input for the trigger signal and a clock input for a clock signal, wherein the pulse output device also has a clock generator for generating the clock signal. The invention also relates to a laser system with such a pulse output device and to a method for outputting at least one pulse triggered by a trigger signal by a digital pulse generator, comprising: supplying the trigger signal to a trigger input of the digital pulse generator, supplying a clock signal to a clock input of the digital pulse generator, and outputting the at least one pulse triggered by the trigger signal by the digital pulse generator.
[0003] The digital pulse generator is used for discrete sampling or discrete reading of the (external) trigger signal. As in all digital clock-based systems, when the digital pulse generator reads in the external event (trigger) that is not synchronized with the clock, a temporal discretization of the event occurs, which leads to what is known as jitter (clock jitter) compared to the external trigger signal. The jitter is primarily determined by the selected base clock of the clock signal or the sampling rate of the discrete or digital clock-based system. For many applications, the occurrence of jitter is undesirable because ideal synchronization with other systems or components is no longer possible.
[0004] The digital pulse generator or pulse output device can, for example, be used to control a laser source of an (ultrashort pulse) laser system in order to use the laser system in "pulse-on-demand" operation, i.e., to generate laser pulses with freely selectable triggering. A digital pulse generator of a laser control system of such a laser system generally operates with clock signals having clock rates in the range of approximately 50 MHz to approximately 100 MHz, or possibly up to 200 MHz. If clock rates of the order of magnitude described here are used to sample an external, random trigger signal (e.g., for a laser pulse request), a discrete jitter in the range of + / - 5 ns is typically generated. A reduction in the jitter could be achieved by increasing the sampling rate or clock rate of the digital pulse generator, but this would result in an increase in the cost of the electronic components.In addition, increasing the clock rate of the digital pulse generator is technically limited.
[0005] So-called "phase-locked loops" are typically used to synchronize circuit components. However, these typically do not require a trigger event, but rather a recurring clock to which another clock can synchronize. Furthermore, this process requires multiple clock edges of the external signal, which requires a time period on the order of approximately 10 to 100 ps.
[0006] CN112968690A describes a high-precision, low-jitter pulse generator. The pulse generator includes a time-to-digital converter module in the form of an FPGA that determines the time interval between the external trigger signal and the clock signal to compensate for the pulse's output jitter. A jitter compensation module processes the time information measured by the time-to-digital converter module and the delay time specified by an operator to obtain the final delay information for pulse compensation. The delay is designed to achieve a precision of 22 ps, and the output pulse's jitter is designed to be 500 ps.
[0007] TW201249107A describes a mechanism for generating an event-triggered pulse wave, which includes a microcontroller. Using an algorithm, the width of the output pulse wave can be adapted to the clock width of a clock signal, and the rising edge of the system can be synchronized. For this purpose, the microcontroller has two interrupt terminals. Object of the invention
[0008] The invention is based on the object of providing a pulse output device, a laser system with such a pulse output device and a method for outputting pulses with very small jitter relative to an external trigger signal.
[0009] Subject of the invention
[0010] This object is achieved according to a first aspect by a pulse output device of the type mentioned at the outset, which is designed to stop a clock divider of the pulse output device, which is designed to reduce a clock rate of the clock signal, and / or the clock generator in order to synchronize the clock signal with the trigger signal before the clock signal is supplied to the clock input of the digital pulse generator, and to restart the clock divider and / or the clock generator synchronously with the trigger signal.
[0011] In the pulse output device described here, the clock generator or a clock divider designed to reduce the clock signal generated by the clock generator is stopped or reset and restarted synchronously with the trigger signal. The external event in the form of the trigger signal, which can be in the form of a single edge or a single trigger pulse, for example, is not read in or sampled directly by the digital pulse generator in this case, but is used to asynchronously reset or stop the clock generator or the clock divider and start it again at a defined time in response to the external event. In this way, the sampling clock of the digital pulse generator can be synchronized to the external event. The event itself or the trigger signal, e.g. in the form of a trigger pulse, is then read in by the synchronized digital pulse generator. In this way, the jitter can be significantly reduced.Basically, there are two options or approaches for synchronizing the clock signal with the trigger signal, which can also be combined with each other:
[0012] In the first option, the pulse output device has a clock divider that is designed to be reset or stopped by the trigger signal and restarted synchronously with the trigger signal. In this case, the clock generator is typically designed to generate a clock signal with a significantly higher clock rate than the clock rate that the digital pulse generator can process. The clock divider serves to reduce the clock rate to a predetermined (integer) proportion of the clock rate of the clock generator, which corresponds to the sampling clock of the digital pulse generator. By synchronizing the clock signal with the trigger signal, the jitter can be significantly reduced in this option, namely to a jitter that corresponds to the higher clock rate of the clock generator, without the digital pulse generator having to be operated at the higher clock rate of the clock generator for this purpose.For example, with a clock rate of the clock generator of 800 MHz, a jitter of + / - 1 / 800 MHz = + / - 1.25 ns can be generated, which corresponds to an improvement of a factor of 16 compared to the jitter generated with a clock rate of the digital pulse generator of, for example, 50 MHz.
[0013] In the second option, the clock generator is designed to be reset or stopped by the trigger signal and then restarted synchronously with the external trigger signal (so-called "free-running oscillator"). In the second option, a clock divider is not necessarily required, but one can still be used, especially to combine both options. With the second option or approach, the jitter can be reduced to less than 500 ps. Combining both approaches makes it possible to reduce the jitter to less than 300 ps.
[0014] In both cases, the digital pulse generator can be synchronized to the external trigger signal within a few tens to hundreds of nanoseconds. In one embodiment, the pulse output device comprises a supply device for supplying the trigger signal to the clock generator and / or the clock divider. The supply device (e.g., in the form of trigger / stop logic) supplies the trigger signal to the clock generator and / or the clock divider. The supply device is typically also configured to additionally route the trigger signal toward the trigger input of the digital pulse generator.
[0015] In a further embodiment, the clock divider and / or the clock generator is / are designed to stop at a first edge of the supplied trigger signal and to restart at a second edge of the supplied trigger signal. In this case, the trigger signal is typically in the form of a trigger pulse having a first, rising edge and a second, falling edge, or vice versa. It is fundamentally possible for the external trigger signal to consist of only a single rising or falling edge, and for a trigger pulse to be generated from the external trigger signal or the trigger edge by means of the supply device, e.g., in the form of the trigger / stop logic.
[0016] In a further embodiment, the pulse output device comprises a delay device for temporally delaying the trigger signal before it is applied to the trigger input of the digital pulse generator. In this embodiment, the trigger signal is delayed before it is applied to the trigger input. The temporal delay allows sufficient time to synchronize other components with the clock signal that has been synchronized with the trigger signal.
[0017] In a further embodiment, the pulse output device comprises a clock distributor for distributing the clock signal synchronized with the trigger signal. The clock distributor serves to transmit the clock signal to digital components or circuit parts other than the digital pulse generator in order to synchronize them appropriately with the pulse generated by the digital pulse generator.
[0018] In one embodiment, the digital pulse generator is designed to delay the output pulse by a predetermined number of clock cycles of the clock signal. The digital pulse generator can generally output the pulse or at least one pulse as soon as the trigger signal or trigger pulse synchronized with the clock signal is applied to the trigger input. However, the digital pulse generator can also be designed to delay the synchronously read trigger by a predetermined or predeterminable number of clock cycles and only output the pulse after this fixed delay. In this case, before the pulse is output, other components can be triggered / controlled by the digital pulse generator, which must be configured before the pulse is triggered.In the event that the output pulse is used to generate a laser pulse, such a component may, for example, be a mechanical shutter that must be opened before the laser pulse is generated.
[0019] In a further embodiment, the clock divider is designed to reduce the clock rate of the clock signal generated by the clock generator by at least 1:8, preferably by at least 1:16. As described above, the jitter can typically be reduced at least in the ratio by which the clock rate is reduced by the clock divider. The clock rate of the clock generator can be significantly higher than the clock rate of the digital pulse generator. For example, the digital pulse generator can be operated at a clock rate of 50 MHz and the clock generator at a clock rate of 800 MHz. In this case, the clock divider reduces the clock rate by a ratio of 1:16.
[0020] In another embodiment, the digital pulse generator is embodied as an FPGA (Field Programmable Gate Array) or as a microcontroller. An FPGA is a digital integrated circuit into which a logic circuit can be loaded. A microcontroller is a semiconductor chip that performs peripheral functions in addition to a processor. As described above, a digital pulse generator embodied in this way cannot be operated at an arbitrarily high clock rate, which is why the use of a clock divider to reduce the clock rate of the clock generator has proven advantageous.
[0021] Another aspect of the invention relates to a laser system comprising: a pulse output device configured as described above, and a laser source for generating laser pulses synchronized with the pulses output by the digital pulse generator. Typically, the starting time of each laser pulse coincides with the starting time of each pulse generated by the digital pulse generator (or each laser pulse has a fixed delay).
[0022] The jitter of the laser pulses requested with the trigger signal can be reduced to less than 2 ns (3 sigma), or even significantly less than 2 ns, using the method described above. Demanding the laser pulses ("pulse on demand") is possible with a trigger-to-light delay of just a few microseconds.
[0023] In principle, it would also be possible to trigger the laser pulses of the laser source directly with an external trigger signal, but in this case it is not possible to start several circuit components at different times or synchronously, as is the case when using the digital pulse generator for generating or triggering the (laser) pulses.
[0024] A further aspect of the invention relates to a method of the type mentioned above for outputting at least one pulse triggered by a trigger signal by a digital pulse generator, in which method, in order to synchronize the clock signal with the trigger signal, a clock generator for generating the clock signal and / or a clock divider for reducing a clock rate of the clock signal is stopped before the clock signal is fed to the clock input of the digital pulse generator and the clock generator and / or the clock divider is restarted in synchronization with the trigger signal. The method described here has the advantages described above in connection with the pulse output device. Further advantages of the invention emerge from the description and the drawing. Likewise, the features mentioned above and those listed below can be used individually or in groups in any combination.The embodiments shown and described are not to be understood as an exhaustive list, but rather have an exemplary character for the description of the invention.
[0025] They show:
[0026] Fig. 1 is a schematic representation of a block diagram of a laser system for generating laser pulses, comprising a pulse output device and a laser source,
[0027] Fig. 2 schematic representations of temporal signal curves at different positions of the laser system of Fig. 1 without synchronization of a clock signal of a digital pulse generator with a trigger signal,
[0028] Fig. 3 is a schematic diagram analogous to Fig. 2 with a synchronization of the clock signal with the trigger signal by stopping and restarting a clock divider, as well as
[0029] Fig. 4 is a schematic diagram analogous to Fig. 2 with an additional temporal synchronization of the clock signal with the trigger signal by stopping and restarting a clock generator.
[0030] In the following description of the drawings, identical reference symbols are used for identical or functionally identical components.
[0031] Fig. 1 shows a laser system 1 comprising a laser source 2 and a
[0032] Pulse output device 3. The pulse output device 3 has a digital pulse generator 4, which in the example shown is designed as an FPGA and is operated at a clock rate of 50 MHz. Alternatively, the pulse output device 3 can also be designed as a microcontroller or the like and operated at a different clock rate. The digital pulse generator 4 is designed to output pulses P triggered by an external trigger signal 5. Such a pulse P is shown in Fig. 2, Fig. 3 and Fig. 4, in which the temporal signal curves at the points designated (a) to (f) in Fig. 1 are illustrated.
[0033] The laser source 2 serves to generate laser pulses LP (cf. (f) in Fig. 2 to Fig. 4) that are synchronized with the pulses P output by the digital pulse generator 4, i.e., the starting times of the laser pulses LP almost coincide with the starting times of the pulses P. The pulse output device 3 thus serves to trigger the laser pulses LP depending on the external trigger signal 5, which is used to request a respective laser pulse LP (pulse-on-demand).
[0034] The digital pulse generator 4 has a trigger input 6 for supplying the trigger signal 5 and a clock input 7 for a clock signal 8 generated by a clock generator 9 of the pulse output device 3. In the example shown, the clock generator 9 is designed to generate a clock signal 8 with a clock rate of 800 MHz (cf. (a) in Fig. 2 to Fig. 4). In the example shown, the pulse output device 3 has a clock divider 10 designed to divide or reduce the clock rate of the clock generator 9 in a ratio of 1:16 in order to reduce the clock rate of the clock signal 8 to 50 MHz (cf. (d) in Fig. 2 to Fig. 4), which corresponds to the clock rate of the digital pulse generator 4.
[0035] In the example shown, the trigger signal 5 has the form of a trigger pulse TP (cf. (b), (c) in Fig. 2 to Fig. 4). A delay unit 11 serves to delay the trigger signal 5 or the trigger pulse TP. In Fig. 2, the trigger pulse TP is indicated by a dashed line at point (c) after passing through the delay unit 11. If the clock signal 8 with a clock rate of 50 MHz, which is present at the clock input 7, is used without providing further measures for sampling the trigger signal 5, a jitter on the order of approximately + / - 10 ns (20 ns in total) is generated. Such a sampling, in which no synchronization takes place between the trigger signal 5 and the clock signal 8, is shown in Fig. 2.
[0036] In order to reduce the temporal jitter that occurs when sampling the trigger signal 5 by means of the digital pulse generator 4, the pulse output device 3 is designed to synchronize the clock signal 8 with the trigger signal 5 before supplying the clock signal 8 to the clock input 7 of the digital pulse generator 4. For synchronization, the clock divider 10 and / or the clock generator 9 can be designed to be paused or stopped and restarted synchronously with the trigger signal 5. In the example shown, the pulse output device 3 has a supply device 12 that is designed to supply the trigger signal 5 to both the clock divider 10 and the clock generator 9.
[0037] To reduce jitter, it is not absolutely necessary to stop and restart both the clock divider 10 and the clock generator 9. Rather, it is sufficient to stop and restart only the clock divider 10, as illustrated by the signal waveforms shown in Fig. 3. In this case, the temporal jitter can be reduced by the ratio of 1:16 of the clock divider 10 and corresponds to the temporal jitter that would be generated if the digital pulse generator 4 were operated at the clock rate of the clock generator 9.
[0038] Fig. 4 illustrates the case in which both the clock divider 10 and the clock generator 9 are stopped and restarted. In this case, the temporal jitter can be reduced even more than in the case described in Fig. 4. It is also possible for only the clock generator 9 to be stopped and restarted, in which case the clock divider 10 can be omitted. In the cases described in Fig. 2 and Fig. 3, the clock divider 10 and the clock generator 9 are stopped after a first, rising edge 13a of the trigger pulse TP of the trigger signal 5 and restarted after a second, falling edge 13b of the trigger pulse TP. The pulse P of the digital pulse generator 4 is triggered by the falling edge 13b of the (time-delayed) trigger pulse TP. It is understood that the stopping or restarting of the clock divider 10 or the clock generator 9 depending on the trigger signal 5 can be realized in other ways.
[0039] In the cases described in Fig. 2 and Fig. 3, the clock signal 8 is synchronized with the trigger signal 5 after passing through the clock divider 10 and is distributed by a clock distributor 14 to further components or circuit parts not shown in the figure in order to synchronize them with the pulse P generated by the digital pulse generator 4 or with the laser pulse LP.
[0040] In the example shown in Fig. 1, the digital pulse generator 4 is designed to delay the output pulse P by a predetermined number of cycles of the clock signal 8. In this case, before the pulse P is output, other components can be triggered / controlled by the digital pulse generator 4, which must be set before the output of the pulse P. Fig. 1 shows an example of such a component 15, which is a mechanical shutter that must be opened before the laser pulse LP is generated.
Claims
Patent claims 1. Pulse output device (3), comprising: a digital pulse generator (4) for outputting at least one pulse (P) triggered by a trigger signal (5), wherein the digital pulse generator (4) has a trigger input (6) for the trigger signal (5) and a clock input (7) for a clock signal (8), and a clock generator (9) for generating the clock signal (8), characterized in that the pulse output device (3) is designed to synchronize the clock signal (8) with the trigger signal (5) before supplying the clock signal (8) to the clock input (7) of the digital pulse generator (4), a clock divider (10) of the pulse output device (3), which is designed to reduce a clock rate of the clock signal (5), and / or to stop the clock divider (10) and / or the clock generator (9) and to restart the clock divider (10) and / or the clock generator (9) synchronously with the trigger signal (5).
2. Pulse output device according to claim 1, further comprising: a supply device (12) for supplying the trigger signal (5) to the clock divider (10) and / or to the clock generator (9).
3. Pulse output device according to claim 2, wherein the clock divider (10) and / or the clock generator (9) are designed to stop at a first edge (13a) of the supplied trigger signal (5) and to restart at a second edge (13b) of the supplied trigger signal (5).
4. Pulse output device according to one of the preceding claims, further comprising: a delay device (11) for delaying the trigger signal (5) before it is fed to the trigger input (6) of the digital pulse generator (4).
5. Pulse output device according to one of the preceding claims, further comprising: a clock distributor (14) for distributing the clock signal (8) synchronized with the trigger signal (5).
6. Pulse output device according to one of the preceding claims, in which the digital pulse generator (4) is designed to delay the output pulse (P) by a predetermined number of clock cycles of the clock signal (8).
7. Pulse output device according to one of the preceding claims, in which the clock divider (10) is designed to reduce the clock rate of the clock signal (8) generated by the clock generator (9) by at least 1:8, preferably by at least 1:
16.
8. Pulse output device according to one of the preceding claims, in which the digital pulse generator (4) is designed as an FPGA or as a microcontroller.
9. Laser system (1), comprising: a pulse output device (3) according to one of the preceding claims, and a laser source (2) for generating at least one laser pulse (LP) which is synchronized with the at least one pulse (P) output by the digital pulse generator (4).
10. A method for outputting at least one pulse (P) triggered by a trigger signal (5) by a digital pulse generator (4), comprising: supplying the trigger signal (5) to a trigger input (6) of the digital pulse generator (4), Supplying a clock signal (8) to a clock input (7) of the digital pulse generator (4), and Outputting the at least one pulse (P) triggered by the trigger signal (5) by the digital pulse generator (4), characterized in that in order to synchronize the clock signal (8) with the trigger signal (5) before the clock signal (8) is fed to the clock input (7) of the digital pulse generator (4), a clock generator (9) for generating the clock signal (8) and / or a clock divider (10) for reducing a clock rate of the clock signal (9) is stopped and the clock generator (9) and / or the clock divider (10) is restarted synchronized with the trigger signal (5).