Selective reuse in analog simulation of an integrated circuit

Abstract

A computing system can identify result data corresponding to a simulation of a first circuit design (301) utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry (302), determine a second circuit design describing an integrated circuit is compatible with the first circuit design based on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design (342), and reuse at least a portion of the result data when simulating the second circuit design utilizing values from the distribution describing the manufacturing variation identified based, at least in part, the result data corresponding to the simulation of the first circuit design. The computing system can estimate a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the simulation (306).

Description

SELECTIVE REUSE IN ANALOG SIMULATION OF AN INTEGRATED CIRCUIT TECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, more specifically, to selective reuse in analog simulation of an integrated circuit. BACKGROUND

[0002] In circuit design verification, conditions for manufacturing an integrated circuits can be included in foundry models, for example, SPICE models of various manufacturing parameters. The foundry models can describe distributions of parameters that can vary during manufacture, such as an oxide thickness, oxide length, or the like.

[0003] A design verification tool can be utilized to evaluate a circuit design describing an integrated circuit relative to the manufacturing variability described in the foundry models. A designer can define outputs of the circuit design and define performance specifications for the outputs, which can be utilized during the evaluation. The design verification tool can utilize the evaluation to determine a probability that a particular manufacturing variation described in the foundry models might cause the circuit design to fail to meet the performance specifications.

[0004] When designers of integrated circuits have concerns about occurrences of rare failure events, for example, when designing computer memory devices, a popular technique can include performing Monte Carlo sampling of variable parameters in the foundry model, selecting a subset of the samples farthest from a nominal parameter value, and thenperform analog simulation of the circuit design with the selected subset of samples at one or more process, voltage, and temperature (PVT) corners. The design verification tool can compare the results of the simulation against the performance specifications to determine whether failures occurred, which can inform the designers about whether the worst of the Monte Carlo samples from the foundry models would cause outputs of the circuit design to fail to meet the performance specification. While this sampling and analog simulation technique can be effective, the design verification tool typically runs thousands of analog simulations for each circuit design, which can be time and resource intensive. When an integrated circuit manufacturer releases new versions of the foundry models, rerunning the analysis on a circuit design library can become infeasible given the time and resource consumption, leaving many designers with having to accept a trade-off, such as extending their design schedule, acquiring more computing resources, over-margining the circuit design, for example, by increasing circuitry size or die area, increasing power, reducing clock speed, or the like. SUMMARY

[0005] This application discloses a computing system implementing a design verification tool to identify result data corresponding to a simulation of a first circuit design utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry. In some embodiments, the computing system implementing the design verification tool can select the set of samples from the distribution describing the manufacturing variation utilizing a machine-learning model of the first circuit design. The computing system implementing the design verification tool can determine a second circuitdesign describing an integrated circuit can be compatible with the first circuit design based, at least in part, on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design , and reuse at least a portion of the result data when simulating the second circuit design. In some embodiments, the simulation of the second circuit design can reuse values from the distribution describing the manufacturing variation identified from the simulation of the first circuit design. The computing system implementing the design verification tool can estimate a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the simulation.

[0006] The computing system implementing the design verification tool also can compare the estimated yield associated with the second circuit design against an estimated yield in the result data associated with the first circuit design. The computing system implementing the design verification tool can select a different set of samples from the distribution describing the manufacturing variation based on the comparison of the yield associated with the second circuit design and the yield associated with the first circuit design. The computing system implementing the design verification tool can simulate the second circuit design utilizing the different set of samples from the distribution describing the manufacturing variation. In some embodiments, the computing system implementing the design verification tool can select the different set of samples from the distribution describing the manufacturing variation uses the machine-learning model of the first circuit design. Embodiments of will be described below in greater detail. DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments.

[0008] Figure 3 illustrates an example design verification tool with additive learning by selectively resuing prior circuit design simulation data that may be implemented according to various embodiments.

[0009] Figure 4 illustrates a flowchart showing an example implementation of estimating integrated circuit yield by sampling a distribution of manufacturing variability according to various examples.

[0010] Figure 5 illustrates a flowchart showing an example implementation of additive learning by selectively resuing prior circuit design simulation data according to various examples. DETAILED DESCRIPTION Illustrative Operating Environment

[0011] Various examples may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processor unit 105 and a system memory 107. The processor unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random accessmemory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processor unit 105.

[0012] The processor unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processor unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0013] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communicationprotocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0014] It should be appreciated that the computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0015] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting,multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0016] Each processor core 201A and 201B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments. Selective Reuse in Analog Simulation of an Integrated Circuit

[0017] Figure 3 illustrates an example design verification tool 300 with additive learning by selectively resuing prior circuit design simulation data that may be implemented according to various embodiments. Figure 4 illustrates a flowchart showing an example implementation of estimating integrated circuit yield by sampling a distribution of manufacturing variability according to various examples. Referring to Figures 3 and 4, a design verification tool 300, for example, implemented with the computing device 101 described in Figure 1, can receive a circuit design 301 describing an electronic device, such as an integrated circuit, in a transistor-level netlist format. The circuit design 301 can correspond to transistor-level netlists describing electronic circuits using metal-oxide- semiconductor (MOS) transistors, resistances, capacitors, inductances, or the like, for example, in a Simulation Program with Integrated Circuit Emphasis (SPICE) file format. In some embodiments, the circuit design 301 can be a standard cell design, for example, within a library of standard cells for the design verification tool 300 to characterize or to estimate a yield.

[0018] The design verification tool 300 can receive foundry models 302 to describe manufacturing parameters, such as oxide thickness, oxide length, or the like, and how those parameters can vary during manufacturing. In some embodiments, the foundry models 302 can describe the statistical conditions for manufacturing the circuit design 301, for example, defining a distribution of values for the manufacturing parameters. In some embodiments, the foundry models 302 can be specified in a SPICE file format.

[0019] The design verification tool 300 can receive a specification 303 for the performance or operation of the circuit design 301. In some embodiments, the specification 303 candefine outputs associated with the circuit design 301 and define when values for the outputs would correspond to a failure. For example, the specification 303 can define a minimum value and a maximum value for an output in the circuit design 301 and deem the performance of the circuit design 301 a failure when the output value falls below the minimum value or exceeds the maximum value. The design verification tool 300 also can receive process corners defining a combination of factors, such as process, voltage, and temperature (PVT), for the manufacture and / or operation of integrated circuits described by the circuit design 301.

[0020] The design verification tool 300 can include a surrogate modeling system 310 to build a surrogate model that approximates an output response of the circuit design 301 to variability of the manufacturing parameters described in the foundry models 302. The surrogate model, when simulated with different sets of manufacturing variations, can provide an output response similar to an output response of the circuit design 301 simulated with the same sets of the manufacturing variations, and the analog simulation system 350 can simulate the surrogate model more quickly than the circuit design 301. In some embodiments, the surrogate model can be a machine-learning model of the circuit design 301, a simple linear regression model, polynomial model, a piece-wise linear regression model, or the like.

[0021] The surrogate modeling system 310 can receive training samples of a manufacturing variation distribution, for example, from a sampling system 320. The sampling system 320 can include a sample generator to sample the distribution of values for the manufacturing parameters in the foundry model 302. In some embodiments, each of the training samplescan be a Monte Carlo sample randomly drawn from the distribution of values for the manufacturing parameters.

[0022] The surrogate modeling system 310 can direct an analog simulation system 350 to iteratively set the manufacturing parameters of the circuit design 301 to correspond to the different training samples and, in a block 401 of Figure 4, simulate the circuit design 301 set with the different training samples utilizing a test bench. The test bench can define test stimulus, for example, clock signals, activation signals, power signals, control signals, data signals, or the like, that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in an analog simulation environment. In some embodiments, the test bench can be written in an object-oriented programming language, for example, SystemVerilog or the like, that, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design 301. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench. The surrogate modeling system 310, in a block 402 of Figure 4, can generate the surrogate model of the circuit design 301 based, at least in part, on the results of the simulation of the circuit design 301 set with the different training samples.

[0023] After the surrogate model of the circuit design 301 has been generated by the surrogate modeling system 310, the sampling system 320 can perform a sampling of parameter values in the foundry models 302 describing variations of parameter values for amanufacturing process. For example, in a block 403 of Figure 4, the sampling system 320 can select samples from the manufacturing variation distribution for simulation of the surrogate model for the circuit design 301. The sampling of the distribution can be performed by randomly selecting parameter values from the distribution, such as a Monte Carlo sample randomly drawn from the distribution of values for the manufacturing parameters.

[0024] The analog simulation system 350, in a block 404 of Figure 4, can simulate the surrogate model with the samples to generate simulation results and identify outlier samples 305. Since the operation of the circuit design 301 as modeled by the surrogate model can vary based on the values of the parameters, the analog simulation system 350 simulating the surrogate model can generate values for outputs defined in the specification 303 that also vary. The design verification tool 300 can determine whether any of the values of the outputs determined during simulation fall outside of the specification 303, for example, exceed a maximum value for the output or fall below a minimum value for the output. The design verification tool 300 can identify the outlier samples 305 as those of the samples that caused the outputs determined during simulation of the surrogate model to fall outside of the specification 303.

[0025] The design verification tool 300 can direct the analog simulation system 350 to, in a block 405 of Figure 4, simulate the circuit design 301 with the outlier samples 305 corresponding to parameter values within the foundry models 302. The analog simulation system 350 can generate simulation results 351, which can include values of the parameters utilized during the simulation and the values of the outputs generated with thevalues of the parameters. In some embodiments, the analog simulation system 350 can perform the simulation of the circuit design 301 using multiple process corners, for example, an integrated circuit manufactured using different processes, operating with different drive voltages, and / or operating with different environment conditions, such as temperatures.

[0026] The design verification tool 300 can include a yield estimation system 330 that, in a block 406 of Figure 4, can estimate a yield for an output in the circuit design 301 describing the integrated circuit based, at least in part, on the simulation results 351. The yield estimation system 330 can determine when the values of the output in the simulation results 351 fell outside of the specification 303 and estimate the yield based, at least in part, on the determination. The yield estimation system 330 can output the yield estimate 306, which can predict a yield for an output defined in the specification 303 given the parameter distributions described in the foundry models 302. The yield estimation system 330 can determine the yield estimate 306 for the output based on the estimated failure probability of the output for the distribution of parameters. The design verification tool 300 and the analog simulation system 350 can record the simulation results 351 in a results database 360 along with the circuit design 301, the foundry models 302, the specification 303, the surrogate model, the outlier samples 305, and the yield estimate 306.

[0027] The design verification tool 300 can include a simulation reuse system 340 to identify when the design verification tool 300 can reuse simulation data from prior circuit design simulations to speed up the simulation process for the circuit design 301, for example, by skipping at least a portion of the simulation process described above withreference to Figure 4, such as generating the surrogate model or identifying outlier samples 305. Embodiments of circuit simulation reuse implemented by the simulation reuse system 340 will be described below with reference to Figures 3 and 5.

[0028] Figure 5 illustrates a flowchart showing an example implementation of additive learning by selectively resuing prior circuit design simulation data according to various examples. Referring to Figures 3 and 5, the simulation reuse system 340, in a block 501 of Figure 5, can receive the circuit design 301 describing an integrated circuit to simulate using a distribution of manufacturing variation, such as from the foundry models 302. In some embodiments, rather than directly performing the entire yield estimate analysis on the circuit design 301 as described above with reference to Figure 4, the design verification tool 300 can first allow the simulation reuse system 340 to analyze the circuit design 301 to determine whether any previous circuit design simulations can include information, such as previously-identified outlier samples, a previously-generated surrogate model, or the like, which can be reused in the simulation of the circuit design 301, for example, to speed up the overall simulation process.

[0029] The simulation reuse system 340 can include a compatibility system 342 that, in a block 502 of Figure 5, can perform a compatibility check of the circuit design 301 against at least another circuit design previously simulated using the distribution of manufacturing variation. When the compatibility system 342 determines the circuit design 301 is compatible with at least another previously simulated circuit design, the design verification tool 300 can access result data 307 corresponding to the previously simulated circuit design,for example, stored in the results database 360, and selectively reuse some of the result data 307 in the analysis of the circuit design 301.

[0030] The compatibility system 342 can include a circuit topology system 343 to identify variables for manufacturing variation input to the circuit design 301 and input to previously simulated circuit designs, for example, stored in the results database 360. In some embodiments, the circuit topology system 343 can identify the variables for manufacturing variation as statistical variables having an associated manufacturing variation distribution, for example, in a netlist associated with the circuit design 301 or the previously simulated circuit designs. The circuit topology system 343 can compare the identified variables for manufacturing variation associated with the circuit design 301 and previously simulated circuit designs against each other. In some embodiments, the circuit topology system 343 can determine the circuit design 301 is compatible with at least one of the previously simulated circuit designs when the circuit design 301 and the previously simulated circuit designs have the same or substantially similar variables for manufacturing variation.

[0031] The circuit topology system 343 also can identify topologies of the circuit design 301 and previously simulated circuit designs, for example stored in the results database 360. In some embodiments, the circuit topology system 343 can identify the topologies by identifying the transistors and possibly their corresponding parameter values within the circuit design 301 and within the previously simulated circuit designs. The circuit topology system 343 can compare the identified topologies of the circuit design 301 and previously simulated circuit designs against each other. In some embodiments, the circuit topologysystem 343 can determine the circuit design 301 is compatible with at least one of the previously simulated circuit designs based on a comparison of the transistors and possibly their corresponding parameter values within the circuit design 301 and within the previously simulated circuit designs. For example, when the circuit design 301 has the same transistors as a previously simulated circuit design, the circuit topology system 343 can deem the circuit design 301 and the previously simulated circuit design compatible.

[0032] The compatibility system 342 can include an ordinal consistency system 344 to confirm compatibility determinations made by the circuit topology system 343. The ordinal consistency system 344 can direct the analog simulation system 350 to simulate the circuit design 301 with samples from across the distribution used in the previously simulated circuit design and determine an order of the samples based on the outputs from the circuit design 301 during the simulations. The ordinal consistency system 344 can access the results database 360 to obtain the result data 307 that includes an order of the samples for the previously simulated circuit design and compare the orders of the samples between the circuit design 301 and the previously simulated circuit design. In some embodiments, the ordinal consistency system 344 can confirm the compatibility of the circuit design 301 with the previously simulated circuit design when the orders of the samples are the same and / or when the ordered samples that correspond to failing outputs are the same in both the circuit design 301 and the previously simulated circuit design.

[0033] When, in a block 503 of Figure, the compatibility system 342 determines the circuit design 301 is not compatible with a previously simulated circuit design, execution can proceed to block 510 of Figure 5, where the design verification tool 300 performs a full yieldanalysis, as described above with reference to Figure 4, and stores the simulation results into the results database 360. In some embodiments, the stored simulation results can be available for reuse by the simulation reuse system 340 when analyzing a different circuit design in the future.

[0034] When, in a block 503 of Figure, the compatibility system 342 determines the circuit design 301 is compatible with a previously simulated circuit design, execution can proceed to block 504 of Figure 5, where the analog simulation system 350 simulates the circuit design 301 with outlier samples used in the previous simulation of the compatible circuit design.

[0035] The yield estimation system 330, in a block 505 of Figure 5, can estimate a yield for an output in the circuit design 301 describing the integrated circuit as simulated with the outlier samples used in the previous simulation of the compatible circuit design. The yield estimation system 330 can determine when the values of the output in the simulation results fell outside of the specification 303 and estimate the yield based, at least in part, on the determination.

[0036] The simulation reuse system 340 can compare the estimated yield for the circuit design 301 simulated with the outlier samples used in the previous simulation of the compatible circuit design against the yield that was estimated for the compatible circuit design. When, in block 506 of Figure 5, the simulation reuse system 340 has determined the estimated yield did not change between the simulation of the circuit design 301 and the simulation of the compatible circuit design, execution can proceed to a block 509 in Figure 5, where the design verification tool 300 can record the simulation results in the resultsdatabase 360 along with the circuit design 301, the foundry models 302, the specification 303, the yield estimate, and the outlier samples used to estimate the yield.

[0037] When, in block 506 of Figure 5, the simulation reuse system 340 has determined the estimated yield did change between the simulation of the circuit design 301 and the simulation of the compatible circuit design, execution can proceed to a block 507 in Figure 5, where the sampling system 320 can utilize the surrogate model associated with the compatible circuit design to identify a different set of outlier samples from the distribution of manufacturing variation, for example, in the foundry models 302. By reusing the surrogate model associated with the compatible circuit design, the design verification tool 300 can skip generating a new surrogate model for the circuit design 301, which can speed up throughput and reduce processing and simulation resource consumption. In some embodiments, such as where a yield estimate procedure does not include a surrogate model, execution can instead proceed to the block 510, where the design verification tool 300 performs a full yield analysis and stores the simulation results into the results database 360. In some embodiments, rather than performing a yield analysis, the design verification tool 300 can construct an output distribution of the circuit design 301 from simulations of the circuit design 301 using samples of manufacturing variation.

[0038] In some embodiments, instead of performing blocks 504-506, the simulation reuse system 340 can perform a confirmation of the compatibility between the circuit design 301 and the previously simulated circuit designs by simulating the circuit design 301 with samples from across the distribution of manufacturing variation, determine an order of the samples based on the outputs from the circuit design 301 during the simulations, andcompare the orders of the samples between the circuit design 301 and the previously simulated circuit design. When the simulation reuse system 340 determines a consistency in the orders of the samples, the simulation reuse system 340 can construct an output distribution for the circuit design 301 based on the simulated samples and the results data 307. When the simulation reuse system 340 determines a lack of consistency in the orders of the samples, execution can proceed to block 510, where a full analysis is performed to generate an output distribution for the circuit design 301.

[0039] In a block 508 of Figure 5, the analog simulation system 350 simulates the circuit design 301 with different set of outlier samples used in the previous simulation of the compatible circuit design. In some embodiments, prior to simulation by the analog simulation system 350, the simulation reuse system 340 can determine whether the different set of outlier samples have ordinal consistency with the outlier samples used in the prior simulation of the compatible circuit design, and the analog simulation system 350 can simulate the circuit design 301 with the different set of outlier samples when they are ordinally consistent with the outlier samples used in the prior simulation of the compatible circuit design. When the different set of outlier samples is not ordinally consistent with the outlier samples used in the prior simulation of the compatible circuit design, execution can proceed to the block 510, where the design verification tool 300 performs a full yield analysis and stores the simulation results into the results database 360.

[0040] After simulation of the circuit design with the different set of outlier samples by the analog simulation system 350, execution can return to the block 505, where the yield estimation system 330 can estimate a yield for an output in the circuit design describingthe integrated circuit as simulated with the different set of outlier samples. The yield estimation system 330 can determine when the values of the output in the simulation results fell outside of the specification 303 and estimate the yield based, at least in part, on the determination.

[0041] Execution can then proceed to the decision block 506, where the simulation reuse system 340 can compare the estimated yield for the circuit design simulated with the different set of outlier samples against the yield that was estimated for the compatible circuit design. When, in block 506 of Figure 5, the simulation reuse system 340 has determined the estimated yield did not change between the simulation of the circuit design and the simulation of the compatible circuit design, execution can proceed to the block 509 in Figure 5, where the design verification tool 300 can record the simulation results in a results database 360 along with the circuit design 301, the foundry models 302, the specification 303, the yield estimate, and the outlier samples used to estimate the yield.

[0042] When in block 506 of Figure 5, the simulation reuse system 340 has determined the estimated yield did change between the simulation of the circuit design and the simulation of the compatible circuit design, execution can proceed to a block 510 in Figure 5, where the design verification tool 300 performs a full yield analysis and stores the simulation results into the results database 360.

[0043] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented inhardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0044] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0045] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine- readable" and may be readable by a processing device.

[0046] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0047] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Conclusion

[0048] While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to design processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of electronic design automation processes.

[0049] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0050] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

CLAIMS 1. A method comprising: identifying, by a computing system, result data corresponding to a simulation of a first circuit design utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry described by the first circuit design; determining, by the computing system, a second circuit design describing an integrated circuit is compatible with the first circuit design based, at least in part, on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design; and simulating, by the computing system, the second circuit design utilizing values from the distribution describing the manufacturing variation identified based, at least in part, the result data corresponding to the simulation of the first circuit design.

2. The method of claim 1, wherein determining the second circuit design is compatible with the first circuit design is based, at least in part, on a comparison of topologies and parameter values between the first circuit design and the second circuit design.

3. The method of claim 1, wherein determining the second circuit design is compatible with the first circuit design further comprises: simulating the second circuit design with compatibility samples taken from across the distribution of manufacturing variation;comparing an order of the compatibility samples associated with the simulation of the second circuit design to an order of the set of samples in the result data corresponding to the simulation of the first circuit design; and determining the second circuit design is compatible with the first circuit design based, at least in part, on the comparison.

4. The method of claim 1, further comprising estimating, by the computing system, a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the set of samples from the distribution describing manufacturing variation for integrated circuitry described by the first circuit design.

5. The method of claim 4, further comprising: comparing, by the computing system, the yield associated with the second circuit design against a yield in the result data corresponding to the simulation of the first circuit design; selecting, by the computing system, a different set of samples from the distribution describing the manufacturing variation based on the comparison of the yield associated with the second circuit design and the yield associated with the first circuit design; and simulating, by the computing system, the second circuit design utilizing the different set of samples from the distribution describing the manufacturing variation.

6. The method of claim 5, wherein the simulation of the first circuit design includes selecting the set of samples from the distribution describing the manufacturing variationutilizing a machine-learning model of the first circuit design, and wherein selecting the different set of samples from the distribution describing the manufacturing variation uses the machine-learning model of the first circuit design.

7. The method of claim 1, wherein the distribution describing manufacturing variation for integrated circuitry is a distribution of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating the integrated circuitry described in the first circuit design.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: identify result data corresponding to a simulation of a first circuit design utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry described by the first circuit design; determine a second circuit design describing an integrated circuit is compatible with the first circuit design based, at least in part, on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design; and simulate the second circuit design utilizing values from the distribution describing the manufacturing variation identified based, at least in part, the result data corresponding to the simulation of the first circuit design.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the second circuit design is compatible with the first circuit design based, at least in part, on a comparison of topologies and parameter values between the first circuit design and the second circuit design.

10. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine the second circuit design is compatible with the first circuit design by: simulating the second circuit design with compatibility samples taken from across the distribution of manufacturing variation; comparing an order of the compatibility samples associated with the simulation of the second circuit design to an order of the set of samples in the result data corresponding to the simulation of the first circuit design; and determining the second circuit design is compatible with the first circuit design based, at least in part, on the comparison.

11. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to estimate a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the set of samples from the distribution describing manufacturing variation for integrated circuitry described by the first circuit design.

12. The system of claim 11, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to: compare the yield associated with the second circuit design against a yield in the result data corresponding to the simulation of the first circuit design; select a different set of samples from the distribution describing the manufacturing variation based on the comparison of the yield associated with the second circuit design and the yield associated with the first circuit design; and simulate the second circuit design utilizing the different set of samples from the distribution describing the manufacturing variation.

13. The system of claim 12, wherein the simulation of the first circuit design includes selecting the set of samples from the distribution describing the manufacturing variation utilizing a machine-learning model of the first circuit design, and wherein the computing system, in response to execution of the computer-executable instructions, is further configured to select the different set of samples from the distribution describing the manufacturing variation using the machine-learning model of the first circuit design.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:identifying result data corresponding to a simulation of a first circuit design utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry described by the first circuit design; determining a second circuit design describing an integrated circuit is compatible with the first circuit design based, at least in part, on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design; and simulating the second circuit design utilizing values from the distribution describing the manufacturing variation identified based, at least in part, the result data corresponding to the simulation of the first circuit design.

15. The apparatus of claim 14, wherein determining the second circuit design is compatible with the first circuit design is based, at least in part, on a comparison of topologies and parameter values between the first circuit design and the second circuit design.

16. The apparatus of claim 14, wherein determining the second circuit design is compatible with the first circuit design further comprises: simulating the second circuit design with compatibility samples taken from across the distribution of manufacturing variation; comparing an order of the compatibility samples associated with the simulation of the second circuit design to an order of the set of samples in the result data corresponding to the simulation of the first circuit design; anddetermining the second circuit design is compatible with the first circuit design based, at least in part, on the comparison.

17. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising estimating a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the set of samples from the distribution describing manufacturing variation for integrated circuitry described by the first circuit design.

18. The apparatus of claim 17, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising: comparing the yield associated with the second circuit design against a yield in the result data corresponding to the simulation of the first circuit design; selecting a different set of samples from the distribution describing the manufacturing variation based on the comparison of the yield associated with the second circuit design and the yield associated with the first circuit design; and simulating the second circuit design utilizing the different set of samples from the distribution describing the manufacturing variation.

19. The apparatus of claim 18, wherein the simulation of the first circuit design includes selecting the set of samples from the distribution describing the manufacturing variation utilizing a machine-learning model of the first circuit design, and whereinselecting the different set of samples from the distribution describing the manufacturing variation uses the machine-learning model of the first circuit design.

20. The apparatus of claim 14, wherein the distribution describing manufacturing variation for integrated circuitry is a distribution of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating the integrated circuitry described in the first circuit design.

Images