Semiconductor assembly comprising a first semiconductor element and a substrate
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- SIEMENS AG
- Filing Date
- 2024-10-29
- Publication Date
- 2026-07-01
AI Technical Summary
Semiconductor devices face reliability issues due to wiring elements detaching from load contacts during operation, often caused by uneven current flow leading to different shearing forces on connections.
A semiconductor arrangement with a substrate having a structured metallization with line sections, where the first semiconductor element is connected to a first line section, and wiring elements are connected to second and third line sections on opposite sides, configured to ensure even current distribution by flowing on diagonally opposite sides.
This configuration significantly reduces the probability of wiring detachment by ensuring even loading of connections, thereby enhancing the reliability and extending the service life of semiconductor devices.
Smart Images
Figure EP2024080513_05062025_PF_FP_ABST
Abstract
Description
[0001] Description
[0002] Semiconductor arrangement with a first semiconductor element and a substrate
[0003] The invention relates to a semiconductor device comprising a first semiconductor element and a substrate.
[0004] Furthermore, the invention relates to a power converter with at least one such semiconductor arrangement.
[0005] Furthermore, the invention relates to a method for producing a semiconductor device comprising a first semiconductor element and a substrate.
[0006] Furthermore, the invention relates to a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate the behavior of such a semiconductor device.
[0007] Such a semiconductor arrangement is generally used in a power converter. A power converter can be, for example, a rectifier, an inverter, a converter or a DC-DC converter. The semiconductor elements used in the semiconductor module include transistors, triacs, thyristors or diodes. Transistors are designed, for example, as insulated-gate bipolar transistors (IGBTs), field-effect transistors or bipolar transistors. The semiconductor elements of a semiconductor arrangement are usually contacted via wiring elements on a substrate. Such wiring elements can include, among other things, bond wires and / or bond strips. In particular, load contacts of a semiconductor element, including an emitter contact of an IGBT, are usually contacted with a plurality of wiring elements on the substrate.The published patent application WO 2022 / 002464 A1 describes a power module with at least two power units, each comprising at least one power semiconductor and a substrate. In order to reduce the installation space required for the power module and to improve heat dissipation, it is proposed that the respective at least one power semiconductor is connected, in particular in a materially bonded manner, to the respective substrate, wherein the substrates of the at least two power units are each directly bonded to a surface of a common heat sink. A side of the power semiconductors facing away from the substrate is each connected to an upper metallization of the substrate via a bond connection.
[0008] During operation of the semiconductor devices, wiring elements can detach from the load contact, leading to failure of the semiconductor device. More robust wiring leads to improved reliability of the semiconductor device.
[0009] Against this background, the object of the present invention is to provide a semiconductor device which has improved reliability.
[0010] The object is achieved according to the invention by a semiconductor arrangement with a first semiconductor element and a substrate, wherein the substrate has a substrate metallization with line sections arranged electrically insulated from one another, wherein the first semiconductor element is connected, in particular materially, to a first line section of the substrate metallization, wherein the first semiconductor element has a contact surface on a side facing away from the substrate, wherein a second line section and a third line section of the substrate metallization are arranged on opposite sides of the first semiconductor element, wherein wiring elements are each electrically and mechanically connected to the second line section, the contact surface of the first semiconductor element and the third line section, wherein the second line section and the third line section are configured such thatthat a load current flowing between the second line section and the third line section via the wiring elements during operation of the semiconductor device flows in or out on one side on diagonally opposite sides.
[0011] Furthermore, the object is achieved according to the invention by a power converter with at least one such semiconductor arrangement.
[0012] Moreover, the object is achieved according to the invention by a method for producing a semiconductor arrangement with a first semiconductor element and a substrate, wherein the substrate has a substrate metallization with line sections arranged electrically insulated from one another, wherein the first semiconductor element is connected, in particular materially, to a first line section of the substrate metallization, wherein the first semiconductor element has a contact surface on a side facing away from the substrate, wherein a second line section and a third line section of the substrate metallization are arranged on opposite sides of the first semiconductor element, wherein wiring elements are each electrically and mechanically connected to the second line section, the contact surface of the first semiconductor element and the third line section,wherein the second line section and the third line section are configured such that a load current flowing between the second line section and the third line section via the wiring elements during operation of the semiconductor device flows in or out on one side on diagonally opposite sides.
[0013] Furthermore, the object is achieved according to the invention by a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate a behavior, in particular thermal, mechanical and / or electrical, of such a semiconductor device.
[0014] The advantages and preferred embodiments listed below with regard to the semiconductor device can be transferred analogously to the power converter, the method and the computer program product.
[0015] The invention is based on the idea of improving the reliability of a semiconductor device by significantly reducing the probability of a failure during operation of the semiconductor device due to wiring elements becoming detached from a semiconductor element. Such detachment can occur, among other things, due to different loading of wiring elements in the event of uneven current flow. Such a semiconductor device has a substrate with a structured substrate metallization which comprises line sections arranged so as to be electrically insulated from one another. A first semiconductor element, for example a vertical transistor such as an IGBT, is connected, in particular in a material-to-material connection, to a first line section of the substrate metallization. The material-to-material connection is produced, for example, by soldering, sintering or adhesively.Furthermore, the semiconductor element has a contact area on a side facing away from the substrate, which contact area is connected to the substrate metallization via wiring elements. For example, the semiconductor element is designed as an IGBT, which is soldered or sintered on the collector side onto the first line section of the substrate metallization, while on the emitter side it is connected to the substrate metallization via the wiring elements. The wiring elements are designed, for example, as bonding wires or bonding strips, the connection between the substrate metallization and the contact area of the semiconductor element being able to be produced by ultrasonic bonding connections. The wiring elements are each connected to a second line section and a third line section of the substrate metallization, which are arranged on opposite sides of the first semiconductor element.During operation of the semiconductor arrangement, a current, in particular load current, flows via the second line section, the wiring elements and the third line section. If the current, in particular load current, flows through the wiring elements, a shearing force acts on connections, in particular ultrasonic bonded connections, between the contact surface of the semiconductor element and the respective wiring elements. If different currents flow via the wiring elements, different shearing forces act on the connections, wherein the shearing forces are greater at higher currents and detachment of the wiring element can occur earlier. The current distribution is influenced, among other things, by wiring impedances of the wiring elements and line impedances of the line sections, in particular between the wiring elements.
[0016] In order to achieve the most even current distribution possible, the current is supplied or discharged on one side on diagonally opposite sides of the second and third line sections. In this context, a one-sided supply or discharge means that the current first flows via a connection between one of the outermost wiring elements and the respective line section. In this context, a one-sided supply or discharge of the current on diagonally opposite sides means that the current first flows in via a connection between an outermost wiring element and a line section and then flows out via a connection between the opposite outermost wiring element and the line section arranged on the other side of the first semiconductor element.Thus, the current in each path generated via one of the wiring elements flows across a very similar, in particular substantially identical, impedance, which is composed of the sum of the respective wiring and line impedances, whereby the current is distributed at least approximately evenly among the wiring elements. In this way, the connections of the wiring elements to the semiconductor element are loaded substantially evenly, which leads to improved reliability of the semiconductor device.
[0017] A computer program product which comprises instructions which, when the program is executed by a computer, cause the computer to simulate a behavior, in particular thermal, mechanical and / or electrical, of the described semiconductor arrangement can comprise a “digital twin” or be designed as such. Such a digital twin is described, for example, in the published patent application US 2017 / 0286572 A1. The disclosure content of US 2017 / 0286572 A1 is incorporated by reference into the present application. The “digital twin” is, for example, a digital representation of the components relevant for the operation of the semiconductor arrangement.
[0018] A further embodiment provides that the second line section and the third line section each have line impedances between the wiring elements, wherein the line impedances of the line sections are each dimensioned such that the current is distributed evenly between the wiring elements. For example, the line impedances of the line sections have a resistive component, in particular a series resistance, an inductive component and / or a capacitive component. In a simplified view, the line impedance can be regarded as a series resistance or as a series resistance with a series inductance. The line impedances can be dimensioned, among other things, by adapting the position and / or geometry of the line sections.By dimensioning the line impedances in this way, the current is distributed evenly among the wiring elements, which leads to improved reliability of the semiconductor device. A further embodiment provides for the wiring elements to be arranged parallel, particularly in a straight line. Such an arrangement achieves uniform current flow while simultaneously requiring minimal space.
[0019] A further embodiment provides that a first wiring element and a second wiring element are each electrically and mechanically connected to the second line section, the contact surface of the first semiconductor element and the third line section, wherein the wiring elements are each connected via a first connection to the second line section and via a second connection to the third line section, wherein the second line section is configured such that the current flows in a first current direction which is designed to run from the first connection of the first wiring element to the first connection of the second wiring element, wherein the third line section is configured such that the current flows in a second current direction which is designed to run from the second connection of the first wiring element to the second connection of the second wiring element.Thus, the partial currents of the current flowing via the first wiring element and the second wiring element flow via very similar, in particular substantially identical, impedances, so that at least approximately a uniform current distribution occurs and the connections of the wiring elements to the semiconductor element are loaded substantially uniformly, which leads to improved reliability of a semiconductor device and extends its service life.
[0020] A further embodiment provides that the second current direction essentially corresponds to the first current direction. Such an arrangement achieves uniform current conduction while simultaneously requiring little space. A further embodiment provides that the first current direction and the second current direction each run essentially perpendicular to at least one wiring element. Such an arrangement achieves uniform current conduction while simultaneously requiring little space, particularly with wiring elements arranged in parallel.
[0021] A further embodiment provides that at least a first line impedance of the second line section is adjusted by varying the width. Such a variation is simple and space-saving to implement.
[0022] A further embodiment provides that the semiconductor arrangement has a second semiconductor element which is connected, in particular in a materially bonded manner, to the second line section and has a contact surface on a side facing away from the substrate, wherein the contact surface of the second semiconductor element is connected via further wiring elements to an electrically insulated fourth line section of the substrate metallization, wherein the fourth line section is arranged directly adjacent to the second line section, wherein the first line impedance of the second line section is dimensioned by a position and / or geometry of the fourth line section. In this context, directly adjacent is to be understood as meaning that no further line section and no electrical component, such as a semiconductor element, is arranged between the fourth line section and the second line section.Such an arrangement ensures uniform current flow while requiring minimal space.
[0023] A further embodiment provides that the fourth line section is arranged in an open-circuit manner on the substrate. An open-circuit arrangement means that, apart from the further wiring elements, it is not electrically connected to any further components. In particular, during operation of the semiconductor arrangement, no current flows to or from the fourth line section. The fourth line section is therefore suitable both for compensating for shear forces which act on the connections of the further wiring elements to the contact surface of the second semiconductor element during operation of the semiconductor arrangement and for adjusting the first line impedance of the second line section. Therefore, in addition to extending the service life of the semiconductor arrangement, the space requirement is also reduced.
[0024] A further embodiment provides that the fourth line section has at least one narrow side and one long side, with one long side of the fourth line section being arranged directly adjacent to the second line section. Thus, the first line impedance of the second line section can be varied over a wide range by the length of the adjacent region.
[0025] A further embodiment provides that the contact surface of the second semiconductor element is connected via the further wiring elements to an electrically insulated fifth line section of the substrate metallization, wherein the fourth line section and the fifth line section are arranged on opposite sides of the second semiconductor element. Due to the additional connection of the further wiring elements to the fourth line section, which is in particular arranged open-circuit, which is also called "overbonding", a counterforce also acts on the second semiconductor element to counteract the shear forces acting on the connections of the further wiring elements to the contact surface of the semiconductor element during operation.Thus, the connections of the additional wiring elements to the contact surface are more robust, especially under load, which has a positive effect on the reliability of the semiconductor device and extends its service life. A further embodiment provides for the wiring elements and the additional wiring elements to be arranged essentially parallel. Such an arrangement achieves uniform current flow while simultaneously requiring minimal space.
[0026] A further embodiment provides for the first semiconductor element to be designed as a high-side switch and the second semiconductor element as a low-side switch of a half-bridge. Such an arrangement enables a compact layout, which has a positive effect on space requirements, optimized current flow of the half-bridge, and, particularly when the first and second semiconductor elements are overbonded, uniform utilization and thus an extended service life of the semiconductor arrangement.
[0027] In the following, the invention is described and explained in more detail with reference to the exemplary embodiments shown in the figures.
[0028] It shows :
[0029] FIG 1 is a schematic representation of a first embodiment of a semiconductor device in a plan view,
[0030] FIG 2 shows a simplified equivalent circuit diagram of the first embodiment of the semiconductor device,
[0031] FIG 3 is a schematic representation of a second embodiment of a semiconductor device in a plan view,
[0032] FIG 4 is a schematic representation of a third embodiment of a semiconductor device in a plan view,
[0033] FIG 5 is a schematic representation of a power converter. The exemplary embodiments explained below are preferred embodiments of the invention. In the exemplary embodiments, the described components of the embodiments each represent individual features of the invention that are to be considered independently of one another, which also further develop the invention independently of one another and are thus to be regarded as a component of the invention, either individually or in a combination other than that shown. Furthermore, the described embodiments can also be supplemented by further features of the invention already described.
[0034] The same reference symbols have the same meaning in the different figures.
[0035] FIG 1 shows a schematic representation of a first embodiment of a semiconductor arrangement 2 in a plan view, which comprises a first semiconductor element 4 which is contact-connected to a substrate 6. By way of example, the first semiconductor element 4 is designed as a vertical transistor, in particular an insulated-gate bipolar transistor (IGBT). Further examples of such semiconductor elements are triacs, thyristors, diodes or other transistor types such as field-effect transistors or bipolar transistors. The IGBT comprises a control terminal, which is designed as a gate terminal G, and load terminals, which are designed as a collector terminal C and an emitter terminal E, the collector terminal C being materially connected to the first substrate 6 on a side of the first semiconductor element 4 facing the first substrate 6.
[0036] The emitter terminal E has a contact area 8, wherein the gate terminal G has a control contact area 10 which is electrically insulated from the contact area 8 of the emitter terminal E. The contact area 8 and the control contact area 10 have at least one metallic layer which contains, for example, aluminum, copper and / or gold. The collector terminal C of the IGBT is materially connected, for example via a soldered or sintered connection, to a first line section 12 of a substrate metallization 14 of the substrate 6. The substrate metallization 14 contains, for example, copper and is structured, wherein a substantially flat surface of the substrate metallization 14 defines an xy plane.A second line section 16 and a third line section 18 of the substrate metallization 14 are arranged on opposite sides of the first semiconductor element 4, wherein the line sections 12, 16, 18 are arranged electrically insulated from one another. Furthermore, the substrate 6 comprises a dielectric material layer 20 which contains, for example, a ceramic material, in particular aluminum nitride or aluminum oxide. The dielectric material layer 20 of the substrate 6 has a thickness of 25 pm to 400 pm, in particular 50 pm to 250 pm. The substrate 6 can be designed, among other things, as a DOB (Direct Copper Bonded) substrate.
[0037] By way of example, two wiring elements 22, 24, which are designed as bonding wires, are each electrically and mechanically connected to the second line section 16, the contact area 8 of the first semiconductor element 4 and the third line section 18, wherein a connection between the emitter E of the first semiconductor element 4 and the substrate 6 is established via the wiring elements 22, 24. The wiring elements 22, 24 are each connected to the second line section 16 via a first connection 26 and to the third line section 18 via a second connection 28. The wiring elements 22, 24 further form a plurality of chip connections 30 on the contact area 8 of the first semiconductor element 4, wherein the wiring elements 22, 24 are connected to the first semiconductor element 4 and the substrate 6 by means of ultrasonic bonding.The chip connections 30 to the contact area 8 of the first semiconductor element 4 are established by looping through the respective wiring element 22, 24, in particular by means of multi-stitch wedge-to-wedge wire bonding. This multiple bonding is also called "stitching." Such chip connections 30 are typically also referred to as "stitch contacts" or "stitch bonds" and can, for example, be designed as "wedge bonds."
[0038] The second line section 16 is, for example, L-shaped and, in the region of the first connections 26 of the wiring elements 22, 24, is designed to run straight in the y-direction, so that a load current IL flows in a first current direction II, which runs from the first connection 26 of the first wiring element 22 to the first connection 26 of the second wiring element 24. For example, the first current direction II runs in the y-direction and thus perpendicular to the wiring elements 22, 24 arranged to run in the x-direction. Due to the L-shaped design of the second line section 16, the load current IL is supplied in the x-direction before it flows straight in the y-direction in the region of the first connections 26 of the wiring elements 22, 24. Alternatively, the second line section 16 can be I-shaped, with the load current IL being supplied in the y-direction in this embodiment.
[0039] The third line section 18 is, for example, I-shaped and runs straight in the y-direction, so that the load current IL flows in a second current direction 12, which runs from the second connection 28 of the first wiring element 22 to the second connection 28 of the second wiring element 24. Just like the first current direction II, the second current direction 12 runs in the y-direction. In particular, the second current direction 12 essentially corresponds to the first current direction II. The load current IL is thus supplied on one side on opposite sides via the second line section 16 and discharged via the third line section 18.
[0040] In the region of the connections 26, 28 of the wiring elements 22, 24, the second line section 16 and the third line section 18 each have the same width b1, b2. Furthermore, the wiring elements 22, 24 are arranged rectilinearly in the x-direction and running parallel, so that a first distance a1 between the first connections 26 on the second line section 16 and a second distance a2 between the second connections 28 on the second line section 16 are essentially the same. The line impedances between the wiring elements 22, 24 of the second line section 16 and the third line section 18 are therefore essentially the same.
[0041] Since the wiring elements 22, 24 arranged in parallel have the same wiring diameters dl, d2 and essentially the same wiring lengths 1, the wiring impedances of the wiring elements 22, 24 are essentially the same and the load current IL is distributed evenly between the two wiring elements 22, 24, for example. For an even distribution of the load current IL, for example with different wiring lengths 1 and / or wiring elements 22, 24 that do not run parallel, the line impedance of the second line section 16 can be adjusted, for example by varying the first width bl.
[0042] FIG. 2 shows a simplified equivalent circuit diagram of the first embodiment of the semiconductor arrangement, which illustrates the relationship described in FIG. 1. The wiring impedances ZV1, ZV2 of the wiring elements 22, 24 and the line impedances ZL1, ZL2 of the second and third line sections 16, 18 between the respective connections of the wiring elements 22, 24 are shown. Furthermore, the supply line impedances ZZ1, ZZ2 of the first and second line sections 16, 18 and idle impedances ZLL1, ZLL2 of the idle line sections of the second and third line sections 16, 18 are shown. A first node Kl is located at the point at which a first load current IL1 is branched off via the first wiring element 22, while a second load current IL2 flows via the second line section 16 to the second wiring element 24.Accordingly, a second node K2 is located at the point where the first load current IL1 from the third line section 18 and the second load current IL2 from the second wiring element 24 are combined. A supply can be made analogously via the second node K2. For example, the impedances can have a resistive component, in particular a series resistance, an inductive component, and / or a capacitive component.
[0043] The load current IL flows unilaterally, i.e., via only one node K1, K2, K3, K4, as well as via diagonally opposite nodes K1, K2; K3, K4. In addition, the sum of the respective wiring impedances ZVI, ZV2 and line impedances ZL1, ZL2 are very similar, in particular, essentially the same, i.e.:
[0044] ZL1 + ZV2 = ZV1 + ZL2 , leads to an even current distribution: IL1=IL2= IL / 2.
[0045] The simplified equivalent circuit diagram results in an essentially Z-shaped current flow.
[0046] If the wiring impedances ZVI, ZV2 are essentially the same, which results from wiring elements 22, 24 running parallel and of equal length and having the same diameter, as shown in FIG 1, the line impedances ZL1, ZL2 must also be dimensioned essentially the same.
[0047] FIG. 3 shows a schematic representation of a second embodiment of a semiconductor arrangement in a plan view, wherein the contact surface 8 of the first semiconductor element 4 is connected to the second line section 16 and the third line section 18 via, for example, four wiring elements 22, 24, 32, 34 arranged rectilinearly in the x-direction and running parallel. As shown in FIG. 1, the wiring elements 22, 24, 32, 34 have the same wiring diameters and substantially the same wiring lengths 1. The distances a1, a2, a3, a4, a5, a6 between the wiring elements 22, 24, 32, 34 arranged in parallel are essentially the same, with the second line section 16 and the third line section 18 each having the same width b1, b2 in the region of the connections 26, 28 of the wiring elements 22, 24, 32, 34.The dissipated current IL is distributed evenly between the wiring elements 22, 24, 32, 34: IL1=IL2= IL3=IL4=IL / 4.
[0048] The further design of the semiconductor device 2 in FIG 3 corresponds to that in FIG 1 or FIG 2.
[0049] FIG. 4 shows a schematic representation of a third embodiment of a semiconductor arrangement 2 in a plan view, wherein the contact surface 8 of the first semiconductor element 4 is connected to the second line section 16 and the third line section 18 via, for example, six wiring elements 22, 24, 32, 34, 36, 38 arranged rectilinearly in the x-direction and running parallel. As shown in FIG. 1, the wiring elements 22, 24, 32, 34, 36, 38 have the same wiring diameters and substantially the same wiring lengths. The distances between the wiring elements 22, 24, 32, 34, 36, 38 arranged in parallel are essentially the same, with the second line section 16 and the third line section 18 in the region of the connections 26, 28 of the wiring elements 22, 24, 32, 34, 36, 38 each having the same width b1, b2.The current IL dissipated is distributed evenly between the wiring elements 22, 24, 32, 34, 36, 38.
[0050] The semiconductor arrangement 2 further comprises a second semiconductor element 40, which is connected, in particular by a material fit, to the second line section 16 and has a contact surface 8 on a side facing away from the substrate 6. A fourth line section 42 and a fifth line section 44 of the substrate metallization 14 are arranged on opposite sides of the second semiconductor element 40, wherein the contact surface 8 of the second semiconductor element 40 is connected to the fourth line section 42 and the fifth line section 44 via further wiring elements 46. The fourth line section 42 is designed to be open-circuited and is arranged directly adjacent to the second line section 16.By way of example, the fourth line section 42 has a substantially rectangular outer contour with a narrow side 48 and a long side 50, wherein a long side 50 of the fourth line section 42 is arranged directly adjacent to the second line section 16. By varying the position and / or the geometry of the fourth line section 42, the first width bl of the second line section 16 can be varied. Thus, the first line impedance ZL1 of the second line section 16 can be dimensioned by the position and / or the geometry of the fourth line section 42.
[0051] By way of example, the first semiconductor element 4 is designed as a high-side switch and the second semiconductor element 40 as a low-side switch of a half-bridge. The fifth line section 44 is connected to a negative DC connection DCN of the half-bridge, while the first line section 12 is connected to a positive DC connection DCP and the third line section 18 is connected to an AG connection AG of the half-bridge. Furthermore, the semiconductor arrangement 2 comprises a sensor 52, in particular a temperature sensor, which is designed, for example, as an NTC thermistor (Negative Temperature Coefficient Thermistor). The sensor 52 is arranged in the region of the semiconductor elements 4, 40. The further embodiment of the semiconductor arrangement 2 in FIG. 4 corresponds to that in FIG. 3.
[0052] FIG 5 shows a schematic representation of a power converter 54, which comprises, for example, a semiconductor arrangement 2.
[0053] In summary, the invention relates to a semiconductor arrangement 2 with a first semiconductor element 4 and a substrate 6, wherein the substrate 6 has a substrate metallization 14 with line sections 12, 16, 18, 42, 44 arranged electrically insulated from one another, wherein the first semiconductor element 4 is connected, in particular in a materially bonded manner, to a first line section 12 of the substrate metallization 14, wherein the first semiconductor element 4 has a contact surface 8 on a side facing away from the substrate 6, wherein a second line section 16 and a third line section 18 of the substrate metallization 14 are arranged on opposite sides of the first semiconductor element 4, wherein wiring elements 22, 24, 32, 34, 36, 38 are each electrically and mechanically connected to the second line section 16, the contact surface 8 of the first semiconductor element 4 and the third line section 18 .In order to achieve improved reliability, it is proposed that the second line section 16 and the third line section 18 are configured such that a current IL flowing between the second line section 16 and the third line section 18 via the wiring elements 22, 24, 32, 34, 36, 38 during operation of the semiconductor device 2 flows in or out on one side on diagonally opposite sides.
Claims
Patent claims 1. Semiconductor arrangement (2) with a first semiconductor element (4) and a substrate (6), wherein the substrate (6) has a substrate metallization (14) with line sections (12, 16, 18, 42, 44) arranged in an electrically insulated manner from one another, wherein the first semiconductor element (4) is connected, in particular by a material fit, to a first line section (12) of the substrate metallization (14), wherein the first semiconductor element (4) has a contact surface (8) on a side facing away from the substrate (6), wherein a second line section (16) and a third line section (18) of the substrate metallization (14) are arranged on opposite sides of the first semiconductor element (4), characterized in that wiring elements (22, 24, 32, 34, 36, 38) are each electrically and mechanically connected to the second line section (16), the contact surface (8) of the first semiconductor element (4) and the third line section (18),wherein the second line section (16) and the third line section (18) are configured such that a load current (IL) flowing between the second line section (16) and the third line section (18) via the wiring elements (22, 24, 32, 34, 36, 38) during operation of the semiconductor device (2) flows in or out on one side on diagonally opposite sides.
2. Semiconductor arrangement (2) according to claim 1, wherein the second line section (16) and the third line section (18) are arranged between the wiring elements (22, 24, 32, 34, 36, 38) each have line impedances (ZL1, ZL2), wherein the line impedances (ZL1, ZL2) of the line sections (16, 18) are each dimensioned such that the current (IL) is distributed evenly between the wiring elements (22, 24, 32, 34, 36, 38).
3. Semiconductor arrangement (2) according to one of claims 1 or 2, wherein the wiring elements (22, 24, 32, 34, 36, 38) are arranged, in particular rectilinearly, running parallel.
4. Semiconductor arrangement (2) according to one of claims 1 to 3, wherein a first wiring element (22) and a second wiring element (24) are each electrically and mechanically connected to the second line section (16), the contact surface (8) of the first semiconductor element (4) and the third line section (18), wherein the wiring elements (22, 24) are each connected via a first connection (26) to the second line section (16) and via a second connection (28) to the third line section (18), wherein the second line section (16) is configured such that the current (IL) flows in a first current direction (II), which is designed to run from the first connection (26) of the first wiring element (22) to the first connection (26) of the second wiring element (24), wherein the third line section (18) is configured such that the current (IL) flows in a second current direction (II),which extends from the second connection (28) of the first wiring element (22) to the second connection (28) of the second, Wiring element (24) is designed to run.
5. Semiconductor device (2) according to claim 4, wherein the second current direction (12) substantially corresponds to the first current direction (II).
6. Semiconductor arrangement (2) according to one of claims 4 or 5, wherein the first current direction (II) and the second current direction (12) are each designed to run substantially perpendicular to at least one wiring element (22, 24).
7. Semiconductor arrangement (2) according to one of the preceding claims, wherein at least a first line impedance (ZL1) of the second line section (16) is adapted by varying the width (b).
8. Semiconductor arrangement (2) according to one of the preceding claims, which has a second semiconductor element (40) which is connected, in particular materially, to the second line section (16) and has a contact surface (8) on a side facing away from the substrate (6), wherein the contact surface (8) of the second semiconductor element (40) is connected via further wiring elements (46) to an electrically insulated fourth line section (42) of the substrate metallization (14), wherein the fourth line section (42) is arranged directly adjacent to the second line section (16), wherein the first line impedance (ZL1) of the second line section (16) is dimensioned by a position and / or geometry of the fourth line section (42).
9. Semiconductor arrangement (2) according to claim 8, wherein the fourth line section (42) is arranged open-circuit on the substrate (6).
10. Semiconductor arrangement (2) according to one of claims 8 or 9, wherein the fourth line section (42) has at least one narrow side (48) and one long side (50), wherein a long side (50) of the fourth line section (42) is arranged directly adjacent to the second line section (16).
11. Semiconductor arrangement (2) according to one of claims 8 to 10, wherein the contact area (8) of the second semiconductor element (40) is connected via the further wiring elements (46) to an electrically insulated fifth line section (44) of the substrate metallization (14), wherein the fourth line section (42) and the fifth line section (44) are arranged on opposite sides of the second semiconductor element (40).
12. Semiconductor arrangement (2) according to one of claims 8 to 11, wherein the wiring elements (22, 24, 32, 34, 36, 38) and the further wiring elements (46) are arranged substantially parallel.
13. Semiconductor arrangement (2) according to one of claims 8 to 12, wherein the first semiconductor element (4) is designed as a high-side switch and the second semiconductor element (40) is designed as a low-side switch of a half-bridge.
14. Power converter (54) with at least one semiconductor arrangement (2) according to one of the preceding claims.
15. A method for producing a semiconductor arrangement (2) with a first semiconductor element (4) and a substrate (6), wherein the substrate (6) has a substrate metallization (14) with line sections (12, 16, 18, 42, 44) arranged electrically insulated from one another, wherein the first semiconductor element (4) is connected, in particular by a material fit, to a first line section (12) of the substrate metallization (14), wherein the first semiconductor element (4) has a contact surface (8) on a side facing away from the substrate (6), wherein a second line section (16) and a third line section (18) of the substrate metallization (14) are arranged on opposite sides of the first semiconductor element (4), characterized in that wiring elements (22, 24, 32, 34, 36, 38) are each electrically and mechanically connected to the second line section (16),the contact surface (8) of the first semiconductor element (4) and the third line section (18) are connected, wherein the second line section (16) and the third line section (18) are configured such that a load current (IL) flowing between the second line section (16) and the third line section (18) via the wiring elements (22, 24, 32, 34, 36, 38) during operation of the semiconductor arrangement (2) flows in or out on one side on diagonally opposite sides.
16. The method according to claim 15, wherein the second line section (16) and the third line section (18) between the wiring elements (22, 24, 32, 34, 36, 38) each have line impedances (ZL1, ZL2), wherein the line impedances (ZL1, ZL2) of the line sections (16, 18) are each dimensioned such that the current (IL) flows uniformly via the wiring elements (22, 24, 32, 34, 36, 38).
17. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to simulate a behavior, in particular electrical, mechanical and / or thermal, of a semiconductor device (2) according to one of claims 1 to 13.