METHOD AND DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES

Abstract

DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES The invention relates to a method for protecting an input or input / output terminal (P) of an integrated circuit (IC1) against electrostatic discharges, the method comprising steps consisting in: generating a control signal (CS) resulting from a comparison of a voltage on the terminal (P) with a threshold voltage, the terminal being isolated from a supply voltage of the integrated circuit, closing a switch (N3) between the terminal and ground if the control signal indicates that the voltage of the terminal is higher than the threshold voltage, and providing a component (CRC) connected between the terminal and the switch, to lower an equivalent capacitance of the integrated circuit, seen from the terminal. Figure for abstract: Fig. 3

Description

Title of the invention: METHOD AND DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES

[0001] The present invention relates to a device for protecting integrated circuits against electrostatic discharges, suitable for protecting wireless communication interfaces, in particular RF (Radio Frequency) circuits, and wired communication interfaces. The present invention applies in particular to integrated circuits for RFID (Radio-Frequency Identification) tags and NFC (Near-Field Communication) tags, as well as to integrated circuits comprising a communication interface such as I2C (Inter-Integrated Circuit), used in particular in loT (Internet of Things) connected objects.

[0002] Generally, integrated circuits include ESD protection circuits connected to the input and input / output terminals of the wired and wireless communication interface circuits.

[0003] However, the performance of such integrated circuits is particularly sensitive to stray capacitances and leakage currents appearing in particular on the interface terminals for connection with an antenna, and wire. These stray capacitances and leakage currents are generally due to the presence of ESD ("ElectroStatic Discharge") protection circuits, or to functional components of the integrated circuit having suffered ESD damage. It is therefore desirable for the ESD protection circuits to have an equivalent stray capacitance as low as possible.

[0004] ESD protection circuits are preferably of the passive type to prevent them from being triggered during normal operation of the integrated circuit, in particular when the signal received by an input terminal varies rapidly during a communication. Some ESD protection circuits include an RC type trigger circuit. It turns out that such a circuit is sensitive to rapid voltage variations. It is therefore poorly suited to RF communication interfaces, because each rising or falling edge of the carrier of the received electromagnetic field can trigger the ESD protection circuit. Part of the received current can therefore be evacuated by the protection circuit, which results in a loss of the energy available for the operation of the integrated circuit, this loss of energy being likely to prevent the processing of the received signals, and to disturb the response signal emitted by the integrated circuit with the introduction of parasitic back-modulation.Such an ESD protection circuit is . also incompatible with wired communications that must be voltage level tolerant.

[0005] Some ESD protection circuits comprise a gate-grounded NMOS (N-channel Metal Oxide Semiconductor field-effect transistor) or gate-coupled NMOS (gcNMOS) transistor, comprising parasitic bipolar transistors which are exploited for their capacity to conduct large currents. However, the characteristics of such components prove to be very dependent on the manufacturing conditions of the integrated circuit and therefore vary significantly from one circuit to another even if they come from the same manufacturing chain. The behavior of such a protection circuit is therefore very difficult to simulate. This drawback is particularly penalizing in the context of integrated circuit manufacturing, in which manufacturing times and costs, as well as the performance to be achieved, are increasingly restrictive.For reasons of time and cost, it is therefore not possible to integrate into the integrated circuit manufacturing process an iterative development phase including a step of manufacturing test integrated circuits, performance tests of the integrated circuits, modifications of the manufacturing mask sets, the manufacturing of new test integrated circuits from the modified mask sets, and the conduct of tests on the new integrated circuits.

[0006] Furthermore, there are ESD protection circuits whose behavior can be easily simulated. However, these circuits have a high equivalent parasitic capacitance. In integrated circuits comprising an RF communication interface, such parasitic capacitance can detune the antenna / RF circuit assembly, and therefore reduce the energy likely to be captured by the antenna and supplied to the integrated circuit, and reduce the sensitivity of the RF circuit, and therefore reduce the signal-to-noise ratio of the received signals. Such parasitic capacitance also has disadvantages in the case of a wired communication interface such as that compliant with the I2C protocol.

[0007] It is therefore desirable to provide an ESD protection circuit that can receive communication signals with fast edges without triggering and without disturbing the received signals. It is also desirable that the behavior of the protection circuit in response to an ESD event can be accurately simulated so that it can be determined whether the protection circuit meets precise specifications without the need to first fabricate an integrated circuit for testing purposes.

[0008] Embodiments relate to a method of protecting an input or input / output terminal of an integrated circuit against electrostatic discharges, the method comprising steps of: generating a control signal resulting from a comparing a voltage at the terminal with a threshold voltage, the terminal being isolated from a supply voltage of the integrated circuit, closing a switch between the terminal and ground if the control signal indicates that the voltage at the terminal is higher than the threshold voltage, and providing a component connected between the terminal and the switch, to lower an equivalent capacitance of the integrated circuit, seen from the terminal.

[0009] According to one embodiment, the control signal acts directly on a grounding circuit of the terminal.

[0010] According to one embodiment, the control signal acts on a grounding circuit of the terminal via a circuit for inverting and shaping the control signal.

[0011] According to one embodiment, the threshold voltage is set as a function of respective resistance values ​​of a resistance bridge connected to a gate terminal of a first transistor producing the control signal.

[0012] According to one embodiment, the threshold voltage is set as a function of a threshold voltage of a first diode connected upstream of the resistance bridge.

[0013] According to one embodiment, the threshold voltage is set as a function of a threshold voltage of a zener diode connected to a gate terminal of a first transistor producing the control signal.

[0014] According to one embodiment, the threshold voltage is set as a function of a threshold voltage of a second diode connected to a source terminal of the first transistor.

[0015] Embodiments may also relate to an integrated circuit comprising: an input or input / output terminal, capable of being subjected to electrostatic discharges, the terminal being isolated from a supply voltage of the integrated circuit, a circuit for comparing a voltage of the terminal with a threshold voltage, providing a control signal capable of triggering the closing of a grounding switch of the terminal P when the voltage of the terminal is higher than the threshold voltage, and a component connected between the terminal and the switch, to lower an equivalent capacitance of the integrated circuit, seen from the terminal.

[0016] According to one embodiment, the component comprises an output connected only to the switch.

[0017] According to one embodiment, the integrated circuit comprises a circuit for inverting and shaping the control signal, arranged between the voltage comparison circuit and the terminal grounding circuit.

[0018] According to one embodiment, the voltage comparison circuit comprises a first transistor producing the control signal and a resistance bridge connected to a gate terminal of the first transistor, the threshold voltage being set as a function of respective values ​​of resistances forming the resistance bridge.

[0019] According to one embodiment, the voltage comparison circuit comprises a diode connected upstream of the resistor bridge, the threshold voltage being set as a function of a threshold voltage of the first diode.

[0020] According to one embodiment, the voltage comparison circuit comprises a zener diode connected to a gate terminal of a first transistor producing the control signal, the threshold voltage being set as a function of a threshold voltage of the zener diode.

[0021] According to one embodiment, the voltage comparison circuit comprises a second diode connected to a source terminal of the first transistor, the threshold voltage being set as a function of a threshold voltage of the second diode.

[0022] According to one embodiment, the component comprises a diode, a Schottky type diode, a Zener diode or a bipolar transistor.

[0023] Examples of embodiments of the invention will be described in the following, without limitation, in relation to the attached figures, among which:

[0024] [fig. 1] figure 1 schematically represents an integrated circuit comprising an ESD protection circuit, according to one embodiment,

[0025] [fig.2] figure 2 schematically represents an integrated circuit comprising a ESD protection circuit, according to another embodiment,

[0026] [fig.3] figure 3 is an electrical diagram of an embodiment of a circuit of ESD protection in an integrated circuit,

[0027] [fig.4] [Fig. 5] [Fig. 6] [Fig. 7] Figures 4 to 7 are electrical diagrams of a circuit of the ESD protection circuit of Figure 3, according to various embodiments.

[0028] Figure 1 represents an integrated circuit IC comprising an input or input / output terminal P and internal circuits INC comprising a signal input connected to the terminal P, the internal circuits being configured in particular to process the signal received from outside the integrated circuit by the terminal P. According to one embodiment, the integrated circuit IC comprises an electrostatic discharge protection circuit ESDC. comprising an input also receiving the signals from the terminal P.

[0029] Figure 2 shows an integrated circuit ICI, and in particular the terminal P, the internal circuits INC, and the circuit ESDC, according to one embodiment. The internal circuits INC of the integrated circuit ICI are connected between a supply voltage source Vdd and a ground plane of the integrated circuit ICI. The ESDC protection circuit comprises circuits CRC, VDT, DVC and BYC connected between the terminal P and the ground plane of the integrated circuit ICI. The CRC circuit comprises a diode DI having an anode terminal connected to the terminal P and a cathode terminal connected to a respective input of each of the circuits VDT, DVC and BYC. The ESDC protection circuit also comprises a diode D2 having a cathode terminal connected to the terminal P and an anode terminal connected to the ground plane of the integrated circuit ICI. The CRC circuit makes it possible to lower the equivalent parasitic capacitance of the integrated circuit, seen of terminal P. Diode D2 allows negative overvoltages appearing on terminal P to be evacuated to the ground plane of the integrated circuit ICI, when the amplitude of these overvoltages exceeds the threshold voltage of diode D2.

[0030] The VDT circuit provides a voltage level detection function and provides a control signal CS representative of the comparison of the signal received by the terminal P with a threshold voltage. The VDT circuit provides the control signal CS at an output of the VDT circuit connected to an input of the DVC circuit. The DVC circuit provides a control function of the BYC circuit from the control signal CS, and for this purpose comprises an output connected to an input of the BYC circuit. The BYC circuit provides a grounding function of the terminal P when the control signal CS indicates that the voltage of the terminal P is greater than the threshold voltage, i.e. in the event of detection of an electrostatic discharge.

[0031] It should be noted that the connections between terminal P (diode D1), and circuits VDT, DVC, BYC and INC, are isolated from the supply voltage source Vdd of the internal circuits INC of the integrated circuit ICI. Indeed, terminal P is either an "open drain" communication terminal, or a power supply terminal, or a power supply and communication terminal. If terminal P provides the function of power supply terminal of the integrated circuit, terminal P is connected to an internal power supply circuit producing the supply voltage Vdd. The supply voltage of the INC circuits is therefore not accessible from terminal P, otherwise the INC circuits would be powered directly by terminal P, even if the power supply circuit producing the voltage Vdd was not powered elsewhere (off).Furthermore, in the case where terminal P is a power supply and communication terminal, when the power supply circuit is inactive (zero supply voltage Vdd), the high level of the communication signal received by terminal P could be significantly reduced if the isolation between terminal P and the supply voltage of the INC circuits was not achieved, the power supply of the circuit then being generated from the signal received by terminal P.

[0032] According to other embodiments, the CRC circuit may be alternatively placed so that the input of the CRC circuit is connected to the P terminal and the input of the VDT circuit, and the output of the CRC circuit is connected to the inputs of the DVC and BYC circuits, or so that the input of the CRC circuit is connected to the P terminal and the respective inputs of the VDT and DVC circuits and the output of the CRC circuit is connected to the input of the BYC circuit. It is noted that the voltage detection range of the VDT circuit may be expanded by placing the CRC circuit so that the output of the CRC circuit is connected only to the BYC circuit.

[0033] According to other embodiments, the CRC circuit comprises a zener or Schottky diode, or a bipolar transistor, or a combination of these different components. It is simply important that the input terminal of the CRC circuit connected to the terminal P occupies a small substrate area in the ICI integrated circuit to present a sufficiently low capacitance likely to lower the equivalent capacitance of the circuit, seen from the P terminal. It is also important that the CRC circuit can conduct a large current, and thus transmit large electrostatic discharge currents to the BYC circuit.

[0034] Figure 3 shows an exemplary embodiment of the ESDC protection circuit connected to the interface terminal P to be protected. The ESDC circuit comprises the circuits VDT, DVC, BYC. The VDT circuit comprises an N-channel MOS transistor NI having a drain terminal connected to the terminal P via a resistor R3, a source terminal connected to ground, and a gate terminal connected to the terminal P via a resistor RI and connected to ground via a resistor R2. The substrate of the transistor NI is also connected to ground.

[0035] The DVC circuit comprises a P-channel MOS transistor PI and an N-channel MOS transistor N2. The PI and N2 transistors have a gate terminal connected to the drain terminal of the NI transistor. The PI transistor has a source terminal connected to the P terminal and a drain terminal connected to a drain terminal of the N2 transistor. The N2 transistor has a source terminal connected to ground.

[0036] The BYC circuit comprises an N-channel MOS transistor N3 having a gate terminal connected to the source terminals of the transistors PI, N2, a drain terminal connected to the P terminal and a source terminal connected to ground. The gate of the transistor N3 can be as wide as possible to allow the transistor N3 to conduct high currents, and thus evacuate high electrostatic discharge currents to ground. However, such a transistor with a wide gate has a necessarily high drain capacitance, to the point of making communication signals, in particular of the I2C or RF type, unusable. Indeed, this capacitance appears in the equivalent capacitance of the integrated circuit, seen from the P terminal. The provision of the low-capacitance CRC circuit introduces into the circuit downstream of the P terminal a low capacitance which makes it possible to lower the equivalent capacitance of the circuit seen from the P terminal.For example, the capacitance of the CRC circuit is between C / 30 and C / 100, C being the equivalent capacitance C of the rest of the circuit seen from terminal P without the CRC circuit, i.e. essentially the capacitance of transistor N3. It follows that the equivalent capacitance taking into account the presence of the CRC circuit is between C / 101 and C / 31, i.e. between C / 100 and C / 30 as a first approximation. The equivalent capacitance of the circuit seen from terminal P is therefore substantially equal to that of the CRC circuit in the case where the capacitance of the CRC circuit is low compared to the equivalent capacitance of the rest of the integrated circuit, seen from terminal P.

[0037] Here again, the CRC circuit can be arranged anywhere between the connection points to terminal P of the VDT, DVC and BYC circuits.

[0038] When the voltage on the input terminal of the VDT circuit is lower than a certain threshold value defined as a function of the values ​​of the resistors RI and R2 and a threshold voltage Vth of the transistor NI, the transistor NI is blocked. The voltage on the drain terminal of the transistor NI (control signal CS) corresponds to the positive values ​​of the voltage received by the terminal P, offset by the potential difference at the terminals of the CRC circuit if the latter is placed upstream of the VDT circuit. The DVC circuit ensures the function of inverting the voltage of the control signal CS coming from the drain terminal of the transistor NI. The voltage supplied by the DVC circuit on the gate terminal of the transistor N3 is therefore lower than the threshold voltage Vth of the latter. The transistor N3 is therefore blocked.

[0039] When the voltage on the gate terminal of transistor N1 exceeds the threshold voltage Vth, in the event of an electrostatic discharge on terminal P, transistor N1 turns on. The drain terminal of transistor N1 is then connected to ground via the source terminal of transistor N1. The control signal CS is therefore zero. The DVC circuit therefore supplies the gate terminal of transistor N3 with a positive voltage (corresponding to the positive values ​​of the voltage received by terminal P), greater than the threshold voltage Vth. Transistor N3 therefore turns on. As a result, terminal P is grounded, which allows an electrostatic discharge current to be discharged to ground. Grounding terminal P causes the voltage on terminal P to fall below the threshold voltage of the VDT circuit and therefore blocks transistor N1, then transistor N3.

[0040] Thus, the electrostatic discharge protection functions are provided by the ESDC circuit without using parasitic components such as parasitic bipolar transistors, apart from equivalent capacitances which can be modeled. The ESDC circuit can therefore be produced entirely with components whose behavior can be simulated in the event of an electrostatic discharge applied to the P terminal.

[0041] The voltage detection circuit VDT has the advantages of being insensitive to the presence of edges (rapid variations) in the communication signal received by terminal P. The adjustment of the trigger threshold voltage of the circuit VDT is carried out simply by choosing the values ​​of the resistors RI, R2. Thus, the threshold voltage VT of the circuit VDT coupled to the diode D1 can be calculated by the following equation: VT = VD1 + Vth*(Rl+R2) / R2, (1) where VD1 is the threshold voltage of the diode DL

[0042] The capacitance of the ESDC circuit seen from terminal P is determined as a function of the ratio between the anode terminal area of ​​diode D1, and the drain terminal area of ​​transistor N3. This capacitance can therefore be reduced easily, as much as possible, and is perfectly modelable.

[0043] Figures 4 to 7 represent the voltage detection circuit, according to various other embodiments. Figure 4 represents a voltage detection circuit VDT1 which differs from the VDT circuit in that it comprises a diode D3 interposed between the resistor RI and the junction point of the resistor RI connected to the terminal P or to the output of the CRC circuit. The VDT circuit (figure 3) has a power consumption which increases if the surface occupied by the resistors RI, R2 is reduced, and the trigger threshold voltage is limited by the threshold voltage Vth of the transistor NI. The diode D3 makes it possible to increase the voltage alone. Thus, the threshold voltage VT of the VDT1 circuit coupled to the diode D1 can be calculated by the following equation: VT = VD1 + VD3 + Vth*(Rl+R2) / R2, (2) where VD3 is the threshold voltage of diode D3.

[0044] Figure 5 shows a voltage detection circuit VDT2 which differs from the circuit VDT1 in that it includes a diode D4 interposed between the source terminal of the transistor NI and ground. It turns out that the threshold voltage Vth of the transistor NI decreases proportionally with the drain-source current leaks in the transistor. The diode D4 makes it possible to compensate for these leaks by adding its threshold voltage VD4 to that of the transistor NI, and therefore makes it possible to reduce the dependence between the trigger threshold voltage VT of the VDT circuit coupled to the diode D1, and the threshold voltage Vth of the transistor NI. The threshold voltage VT of the VDT2 circuit coupled to the diode D1, can be calculated by the following equation: VT = VD1 + VD3 + (Vth+VD4)*(R1+R2) / R2, (3).

[0045] Diode D4 can be implemented without diode D3. Thus, the threshold voltage VT of the circuit VDT2 coupled to diode D1, but without diode D3, can be calculated by the following equation: VT = VD1 + (Vth+VD4)*(R1+R2) / R2, (4)

[0046] Figure 6 shows a voltage detection circuit VDT3 which differs from the VDT circuit in that it includes a zener diode ZI which replaces the resistor RL. The implementation of the zener diode ZI makes it possible both to set more precisely the trigger threshold voltage of the VDT circuit, coupled to the diode D1, and to reduce the consumption and the substrate surface occupied by the VDT circuit. The threshold voltage VT of the VDT3 circuit coupled to the diode D1 can be calculated by the following equation: VT = VD1 + VZ + Vth, (5) where VZ is the threshold voltage of the zener diode ZI.

[0047] Figure 7 shows a voltage detection circuit VDT4 which differs from the circuit VDT3 in that it includes the diode D4 interposed between the drain terminal of the transistor NI and the ground. The circuit VDT4 combines the advantages of the circuits VDT2 and VDT3. The threshold voltage VT of the circuit VDT4 coupled to the diode D1 can be calculated by the following equation: VT = VD1 + VZ + Vth + VD4. (6)

[0048] It will be clear to those skilled in the art that the present invention is susceptible to various variant embodiments and various applications. In particular, the invention is not limited to the presence of the DVC circuit. Indeed, according to one embodiment, transistor N3 of the BYC circuit is replaced by a P-channel MOS transistor whose gate can be sized 2.5 times wider than that of transistor N3 to be able to pass currents at least as large as those of transistor N3. The gate of transistor N1 can also be widened to be able to supply a current capable of directly driving the P-channel MOS transistor of the BYC circuit. According to another embodiment, transistor N1 is replaced by a P-channel MOS transistor whose gate is sized sufficiently wide to be able to directly drive transistor N3 of the BYC circuit.

Claims

Claims

1. A method for protecting an input or input / output terminal (P) of an integrated circuit (IC, ICI) against electrostatic discharges, the method comprising steps consisting of: generating a control signal (CS) resulting from a comparison of a voltage on the terminal (P) with a threshold voltage, the terminal being isolated from a supply voltage of the integrated circuit, closing a switch (N3) between the terminal and ground if the control signal indicates that the voltage of the terminal is higher than the threshold voltage, and providing a component (CRC, Dl) connected between the terminal and the switch, to lower an equivalent capacitance of the integrated circuit, seen from the terminal.

2. Method according to claim 1, in which the control signal (CS) acts directly on a circuit (BYC) for grounding the terminal (P).

3. Method according to claim 1, in which the control signal (CS) acts on a circuit (BYC) for grounding the terminal (P) via a circuit (DVC) for inverting and shaping the control signal.

4. Method according to one of claims 1 to 3, in which the threshold voltage is set as a function of respective values ​​of resistances (RI, R2) of a resistance bridge connected to a gate terminal of a first transistor (NI) producing the control signal (CS).

5. Method according to claim 4, wherein the threshold voltage is set as a function of a threshold voltage of a diode (D3) connected upstream of the resistance bridge (RI, R2).

6. Method according to one of claims 1 to 3, in which the threshold voltage is set as a function of a threshold voltage of a zener diode (Zl) connected to a gate terminal of a first transistor (NI) producing the control signal (CS).

7. Method according to one of claims 4 to 6, wherein the threshold voltage is set as a function of a threshold voltage of a diode (D4) connected to a source terminal of the first transistor (NI).

8. Integrated circuit comprising: an input or input / output terminal (P), capable of being subjected to electrostatic discharges, the terminal being isolated from a voltage integrated circuit (IC, ICI) power supply, a circuit (VDT) for comparing a terminal voltage with a threshold voltage, providing a control signal (CS) capable of triggering the closing of a switch (N3) for grounding terminal P when the terminal voltage is higher than the threshold voltage, and a component (CRC, Dl) connected between the terminal and the switch, to lower an equivalent capacitance of the integrated circuit, seen from the terminal.

9. Integrated circuit according to claim 8, wherein the component (CRC, Dl) comprises an output connected only to the switch (N3).

10. Integrated circuit according to claim 9, comprising a circuit (DVC) for inverting and shaping the control signal (CS), arranged between the voltage comparison circuit (VDT) and a circuit (BYC) for grounding the terminal (P).

11. Integrated circuit according to one of claims 8 to 10, in which the voltage comparison circuit (VDT) comprises a first transistor (NI) producing the control signal (CS) and a resistance bridge (RI, R2) connected to a gate terminal of the first transistor, the threshold voltage being fixed as a function of respective values ​​of resistances forming the resistance bridge.

12. Integrated circuit according to claim 11, in which the voltage comparison circuit (VDT) comprises a diode (D3) connected upstream of the resistance bridge (RI, R2), the threshold voltage being fixed as a function of a threshold voltage of the diode.

13. Integrated circuit according to one of claims 8 to 10, in which the voltage comparison circuit (VDT) comprises a zener diode (Zl) connected to a gate terminal of a first transistor (NI) producing the control signal (CS), the threshold voltage being set as a function of a threshold voltage of the zener diode.

14. Integrated circuit according to one of claims 11 to 13, in which the voltage comparison circuit (VDT) comprises a diode (D4) connected to a source terminal of the first transistor (NI), the threshold voltage being set as a function of a threshold voltage of the diode connected to the source terminal of the first transistor.

15. Integrated circuit according to one of claims 8 to 14, in which the component (CRC) comprises a diode (Dl), a schottky type diode, a zener diode or a bipolar transistor.

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