Photodiode including a memory area

Abstract

Photodiode comprising a memory area. This description relates to a photodiode comprising at least one memory area (104), each memory area comprising at least two storage regions (106), the charge storage regions being connected by first (116) and second (281) apertures. Figure for the abbreviation: Fig. 9

Description

Title of the invention: Photodiode comprising a memory area Technical field

[0001] The present description relates generally to electronic components and more particularly to photodiodes comprising a memory zone. Prior art

[0002] Photodiodes are semiconductor components each comprising a PN junction. Photodiodes have the capacity to detect light radiation, for example from the optical domain, and to transform it into an electrical signal.

[0003] Image sensors are electronic devices each comprising a plurality of photodiodes. The photodiodes allow the device to obtain an image of a scene at a given instant. The image consists of a matrix of pixels, the information for each pixel being obtained by one or more photodiodes. For example, this information generally corresponds to a quantity of electrons obtained by a photodiode at a given instant, this quantity of electrons being converted by the image sensor into color levels (red, green or blue) or into gray levels.

[0004] During a first operating step in which a photodiode receives radiation from a scene, the photodiode may, for example, store the electrons obtained in memory areas, i.e. electron storage areas. During a second operating step, the quantity of electrons located in the memory areas is read. This value is then representative of the quantity of radiation received from the scene. Summary of the invention

[0005] One embodiment overcomes all or part of the drawbacks of photodiodes comprising a known memory zone.

[0006] One embodiment provides a photodiode comprising at least one memory area, each memory area comprising at least two storage regions, the charge storage regions being connected by first and second openings.

[0007] According to one embodiment, the first opening is at least partially covered by a connection pad.

[0008] According to one embodiment, the second opening is not covered by the connection pad.

[0009] According to one embodiment, the connection pad is a reading pad of a value representative of the quantity of charge in the memory area.

[0010] According to one embodiment, the second opening is located as close as possible to the pad without being located under the pad.

[0011] According to one embodiment, the main directions of the storage regions of the same memory area are parallel.

[0012] According to one embodiment, the storage regions are at least partially surrounded by first insulated conductive walls.

[0013] According to one embodiment, each insulated conductive wall comprises a conductive core configured to receive, during operation of the photodiode, a negative voltage, the insulating core at least partially surrounded by an insulating sheath.

[0014] According to one embodiment, the first and second openings are separated by a portion of second insulated conductive wall.

[0015] According to one embodiment, the first insulated conductive walls comprise portions located on either side of the second opening and extending towards the second opening.

[0016] Another embodiment provides a method of using a photodiode as described previously, comprising a first step during which electrons are generated and are stored in the memory area(s) and a second step of reading the quantity of electrons in the memory area(s).

[0017] According to one embodiment, the portion receives a negative voltage during the first step.

[0018] According to one embodiment, the voltage received by the portion reaches a positive value during the second step. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [fig. 1] figure 1 represents an embodiment of a photodiode;

[0021] [fig.2] figure 2 represents another embodiment of a photodiode;

[0022] [fig.3] figure 3 represents another embodiment of a photodiode;

[0023] [fig.4] figure 4 represents another embodiment of a photodiode;

[0024] [fig.5] figure 5 represents the electrostatic potential on the path of the electrons in the embodiment of Figure 1;

[0025] [fig.6] Figure 6 represents the electrostatic potential in a part of one of the embodiments of figures 1 to 4;

[0026] [fig.7] Figure 7 represents the electrostatic potential in a part of one of the embodiments of figures 1 to 4;

[0027] [fig.8] Figure 8 represents the electrostatic potential in a part of one of the embodiments of figures 1 to 4;

[0028] [fig.9] figure 9 represents another embodiment of a photodiode;

[0029] [fig.10] figure 10 represents another embodiment of a photodiode;

[0030] [fig.l 1] figure 11 represents the electrostatic potential in a part of the mode of realization of figure 10 during three stages of operation;

[0031] [fig. 12] figure 12 represents another embodiment of a photodiode. Description of the embodiments

[0032] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the electronic devices comprising the pixels, for example the image sensors, will not be detailed.

[0034] Unless otherwise specified, when referring to two elements connected between them, it means directly connected without intermediate elements other than conductors, and when referring to two elements connected or coupled together, it means that these two elements can be connected or be connected or coupled through one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "approximately", "approximately", "sen "possibly", and "of the order of" mean within 10%, preferably within 5%.

[0037] Figure 1 shows an embodiment of a photodiode 100. More specifically, Figure 1 is a top view of the photodiode 100.

[0038] The photodiode 100 comprises an active area 102, located in a semiconductor substrate, for example made of silicon. The active area 102 is the semiconductor area receiving radiation and generating electrical charges, for example electrons. The active area 102 comprises, for example, a PN junction, for example a PN junction comprising horizontal semiconductor layers.

[0039] The photodiode 100 comprises memory areas 104 in the substrate. Each memory area 104 is an area in which charges are stored, for example in electron storage areas. Each memory area 104 is for example an area of ​​the semiconductor substrate in which the photodiode 100 is formed.

[0040] In the example of FIG. 1, the photodiode 100 comprises two memory areas 104. The memory areas 104 are located on either side of the active area 102.

[0041] Each memory area 104 comprises at least two electron storage regions 106. In the example of FIG. 1, each memory area 104 comprises two electron storage regions 106. Each electron storage region 106 has, for example, substantially the shape of a parallelogram.

[0042] The main direction of an electron storage region 106 is considered to be the direction of the highest dimension in the plane of FIG. 1. In the example of FIG. 1, the main directions of the storage regions 106 of the same memory area 104 are parallel. In the example of FIG. 1, the main directions of the storage regions 106 of the different memory areas 104 are parallel.

[0043] In the example of Figure 1, the storage regions 106 of the same memory area 104 have identical dimensions. However, the regions may have different dimensions. For example, the two regions 106 may have a substantially equal width. For example, one of the two regions may have a length greater than that of the other region 106. For example, the storage region 106 furthest from the active area 106 may have a length greater than the length of the active area 106 closest to the active area 102.

[0044] The width of one of the storage regions 106 is called the dimension in the direction perpendicular to the main direction of this region in the plane of FIG. 1. The length of one of the storage regions 106 is called the dimension in the main direction of the storage region 106.

[0045] Each memory area 104 is surrounded by insulated conductive walls 108, with the exception of an input region of the memory area. The insulated conductive walls 108 receive, during operation of the photodiode 102, a negative voltage.

[0046] Each insulated conductive wall 108 comprises a conductive core and an insulating sheath not shown in FIG. 1. The conductive core is for example made of metal. The sheath is for example made of silicon oxide. The conductive core is for example connected to a node for applying a voltage. The insulating sheath surrounds the conductive core, with the exception for example of the connections with the voltage source. In particular, the insulating sheath separates the conductive core from the active zone 102 of the photodiode 100 and the electron storage regions 106. The insulating sheath for example completely covers the side walls and the bottom of the conductive core. The insulating sheath for example partially covers the upper face of the conductive core.

[0047] In the example of Figure 1, each memory area 104 comprises three insulated conductive walls 108a, 108b and 108c extending in the main direction of the storage regions 106. The walls 108a and 108b constitute the side walls of the memory area 104. The wall 108c forms the separation between the two storage regions 106. Each memory area 104 further comprises one or more walls 108 connecting some the three walls 108a, 108b and 108c on one side of the memory area 104. In the example of Figure 1, the photodiode 100 comprises a single wall 108d connecting the walls 108a and 108c on one side of the memory area. The other side of the memory area 104, for example, is separated from a strip 110 extending along the photodiode 100 by an insulated conductive wall 112. The wall 112 connects the walls 108a and 108b. The insulated conductive wall 112 comprises, like the walls 108, a conductive core and an insulating sheath similar to the core and the sheath of the walls 108. The wall 112 extends, in the example of FIG. 1, along the part of the strip 110 extending along the photodiode 100. The wall 112 is therefore common to the two memory areas of the photodiode 100. The wall 112 further separates the active area 102 from the strip 110.

[0048] The strip 110 is for example a conductive strip. The strip 110 is for example a reading strip allowing the reading of the photodiode, that is to say the obtaining of a voltage representative of the quantity of charges in the memory zones 104.

[0049] For each memory area 104, the wall 108a extends from the wall 112 to the wall 108d. The walls 108b and 108c extend partially from the wall 112 to the wall 108d. The wall 108b comprises an opening 114 constituting the entrance to the memory area 104. The opening 114 is, in the example of FIG. 1, located between the wall 108b and the wall 108d. The opening 114 allows the electrons generated in the active area 102 to pass into the memory area 104.

[0050] Similarly, wall 108c includes an opening 116. Opening 116 constitutes the connection between the two electron storage regions 106. Opening 116 allows electrons to pass from one region to the other. Opening 116 is, in the example of Figure 1, between wall 108c and wall 112.

[0051] The openings 114 and 116 are preferably located at opposite ends of the memory area 104, in the main direction of the regions 106.

[0052] A conductive pad 118 is located above each opening 114, that is to say above each entrance of the memory zones 104. In FIG. 1, there are therefore two conductive pads 118 each covering a portion of the semiconductor substrate in which the active zone 102 and the memory zones 104 are formed.

[0053] A conductive pad 120 is located above each opening 116. Each conductive pad 120 preferably completely covers the opening 116. In the example of FIG. 1, the conductive pad 120 partially covers the strip 110, the wall 112 and the parts of the memory area 104 in contact with the wall 112. For example, the conductive pad 120 partially covers the walls 108a, 108b and 108c extending in the main direction of the storage regions 106.

[0054] In the example of Figure 1, the photodiode 100 further comprises a region 122 of semiconductor material partially surrounded by insulated conductive walls 124. In the example of Figure 1, the region 122 is surrounded by two walls 124 having each a U shape in the plane of the figure.

[0055] The region 122 is for example connected to a voltage application node.

[0056] As a variant, the elements 122 and 124 may be absent.

[0057] During a first step of operation, electrons are generated in the active area 102. The region 122 and the pads 116 receive negative voltages. The conductive pads 118 receive a positive voltage, so as to attract the electrons towards the memory areas 104. The electrons fill the electron storage region 106 closest to the opening 114 and then, the electrons passing through the opening 116, fill the storage region furthest from the opening 114.

[0058] During a second step of operation, region 122 receives a positive voltage so as to attract the newly generated electrons. This ensures that the quantity of electrons read from the memory areas is representative of the scene at a given time. Pads 118 receive a negative voltage and pads 116 receive a positive voltage.

[0059] Throughout the operation of the photodiode, the insulated conductive walls 108 and 112 receive a negative voltage, for example approximately equal to -2 V or -2.5 V.

[0060] The operation of the photodiode will be described in more detail in relation to Figures 5, 6, 7, and 8.

[0061] Figure 2 shows another embodiment of photodiodes 125. Figure 2 shows two photodiodes 125.

[0062] Each of the two photodiodes 125 comprises the same elements as the photodiode 100 of FIG. 1, referenced in the same way, with the exception of the strip 110 and the walls 112. The identical elements will not be detailed again. The strip 110 is replaced by a strip 127. The strip 127 is, like the strip 110, a conductive strip. The strip 127 is common to the two photodiodes 125. The two photodiodes 125 are symmetrical to each other with respect to the strip 127. Each memory area 104 is therefore located opposite another memory area 104, separated by the strip 127.

[0063] Unlike Figure 1, in which the strip 110 was a continuous strip along the entire length of the photodiode, the strip 127 common to the two photodiodes 125 comprises openings 129. Similarly, the strip 112 comprises openings 131 at the openings 129.

[0064] In the example of Figure 2, the strip 127 comprises two openings 129. Each strip 112 therefore comprises two openings 131. Each memory zone 104 of one of the two photodiodes is connected to a memory zone 104 of the other of the two photodiodes 125 by two openings 131 and one opening 129.

[0065] The opening 129 and the two openings 131 are for example located between the two openings 116. The two openings 116 of the two memory zones 104 are therefore connected by opening 129 and the two openings 131.

[0066] The operation of the photodiodes 125 is identical to the operation of the photodiode 100. The different elements of the photodiodes 125 are for example controlled in an identical manner, and at the same times.

[0067] Figure 3 shows another embodiment of a photodiode 150.

[0068] Photodiode 150 is identical to photodiode 100 except for the number of electron storage regions 106. Common elements between photodiode 150 and photodiode 100 are referenced in the same manner and are not detailed again.

[0069] The photodiode 150 comprises, in each memory area 104, three electron storage regions 106. The three storage regions, as in FIG. 1 and in FIG. 2, have for example a substantially parallelogram shape. In addition, the regions 106 have a main direction substantially parallel to each other, preferably parallel to the main direction of all the regions 106 of the photodiode. The regions 106 are separated from each other by insulated conductive walls 108c' and 108c". The walls 108c' and 108c" are identical to the walls 108c of FIG. 1.

[0070] Each of the walls 108c' and 108c" respectively forms an opening 116' and 116". Preferably, the openings 116' and 116" are located on the same side of the memory area 104, for example on the side opposite the opening 114 in the main direction of the regions 106.

[0071] The pad 120 of each memory zone 104 is identical to the pads 120 described in relation to FIG. 1 and covers at least the two openings 116' and 116". Preferably, each pad 120 extends from the wall 108a to the wall 108b.

[0072] The operation of the photodiode 150 is the same as the operation of the photodiode 100 of FIG. 1.

[0073] Two photodiodes 150 may be arranged in the same way as the photodiodes 125 are arranged in FIG. 2, i.e. symmetrically to each other with respect to a strip 127 replacing the strip 110. The openings 129 and 131 are for example located in the strip 110 between the two openings 116' and 116".

[0074] Figure 4 shows another embodiment of a photodiode 155. The photodiode 155 includes elements identical to the elements of Figure 1, referenced in the same way. These elements are not detailed again.

[0075] The photodiode 155 of FIG. 4 differs from the photodiode 100 of FIG. 1 in that the storage regions 106 of a memory area 104 do not extend in directions parallel to each other, but in directions that are preferably substantially perpendicular. The storage regions therefore have, for each memory area 104, substantially an L shape.

[0076] Each memory area 104 comprises a region 106a extending along the wall 108a and a region 106b extending along wall 112. Regions 106a and 106b join at a region 157 located at the level where walls 108a and 112 join.

[0077] Region 106a is separated from active area 102 by a wall 159. Region 106b is separated from active area 102 by a wall 161. Regions 106b of the two memory areas 104 are separated by a wall 163. Walls 159, 161 and 163 are insulated conductive walls, similar to walls 108.

[0078] The pad 120 covers the region 157. For example, the pad 120 partially covers the wall 112, the wall 108a, the wall 159 and the wall 161. The conductive pads 120 do not cover the active zone 102. The conductive pads 120 do not cover the strip 110.

[0079] In the example of Figure 4, the active area 102 is separated from the wall 112 along the entire length of the active area 102 by the regions 106b, the wall 163, and the walls 161. The dimensions of the regions 106b and the dimensions of the wall 163 ensure that the active area 102 is not in contact with the wall 112.

[0080] As a variant, a part (not shown) of the active zone 102 could be located between the two regions 106b. Each of the regions 106b would thus be separated from this part of the active zone by an insulated conductive wall similar to the wall 163. The dimensions of the regions 106b in their main direction, that is to say the direction in which the wall 112 extends, would then be less than the dimension of the regions 106b in their main direction in the case of FIG. 4. The active zone 102 would therefore be in contact with the wall 112.

[0081] Like the photodiode 150 of Figure 3, two photodiodes 155 can be arranged in the same way as the photodiodes 125 are arranged in Figure 2, i.e. symmetrically to each other with respect to a strip 127 replacing the strip 110. The openings 129 and 131 are for example located at the region 157.

[0082] The operation of the photodiode 155 is substantially identical to the operation of the photodiodes 100, 125 and 150 of the preceding figures.

[0083] Figure 5 shows the electrostatic potential on an electron path in the embodiment of Figure 1.

[0084] The origin of the electron path, corresponding to the origin of the abscissa (Distance), is located in the active zone 102. The path of the electrons considered then extends into one of the openings 114, into the region 106 closest to the active zone 102, into the opening 116 and into the other region 106.

[0085] The ordinate corresponds to the electrostatic potential (Electrostatic Potential) along the path of the electrons. The ordinate is represented in such a way that positive values ​​are directed downwards and negative values ​​are directed upwards on the ordinate axis.

[0086] Figure 5 includes a first curve 175 in solid lines and a second curve 177 in dotted lines. Curve 175 corresponds to the maximum electrostatic potential over a thickness ranging from 0.1 pm to 2 pm in the semiconductor material on the path. The thickness is measured from the upper face of the substrate, i.e. the face shown in Figure 1. Curve 177 corresponds to the maximum electrostatic potential in a thickness ranging from 0.3 pm to 2 pm in the semiconductor material on the path. Thus, curve 175 includes a portion of the substrate located above the portion considered for curve 177.

[0087] In the example of Figure 5, it is considered that the pads 118 receive a positive voltage, for example 1.1V. It is further considered that the pad 120 receives a negative voltage, for example -IV. The values ​​of the curves 175 and 177 correspond to an instant during the electron generation step, before the reading step.

[0088] The opening 114 of the memory area 104 corresponds to a distance dl, for example approximately 1.5 pm, on the path of the electrons.

[0089] At the distance dl, the curves 175 and 177 both have an extrema. This extrema represents a first barrier to be crossed by the electrons. Thus, when the quantity of electrons is sufficient in the active zone 102, that is to say at a distance less than dl, the electrons enter the first region 106. The first region 106 therefore corresponds to a distance between the distance dl and a distance d2. The distance d2 is for example substantially equal to 5.25 pm. Between dl and d2, the electrostatic potential is much lower than at the distances dl and d2. The distance d2 corresponds to the opening 116. At the distance d2, the curves 175 and 177 have an extrema. This is a second barrier. Thus, when the number of electrons is sufficient in the first region 106, the electrons pass into the second region 106.For distances greater than distance d2, curves 175 and 177 represent the electrostatic potential in the second region 106.

[0090] Thus for a memory area 104, the region 106 closest to the active area 102 is first filled then when this region is filled, the electrons are transferred to the region 106 furthest from the active area 102.

[0091] Memory areas such as those described in relation to FIG. 1 therefore make it possible to obtain an electron storage capacity greater than the storage capacity of a memory comprising only one electron storage region.

[0092] It would have been possible to choose to enlarge the dimensions of a storage region without adding a second region 106 separated by an opening 116. However, the single storage region would then include, particularly in the deep regions, regions in which the electrons would be difficult to read.

[0093] Figures 6 and 7 each represent two views along section AA of Figure 2. The first views, 6A and 7A, represent the doping levels in the part concerned. The second views 6B and 7B represent the electrostatic potential in this same part, respectively in the part represented in views 6A and 7A, during the reading step, that is to say when the connection pad 120 receives a voltage of positive value.

[0094] Although Figures 6 and 7 are described in relation to Figure 2, the observations made are also valid for embodiments comprising two photodiodes 100, 150 or 155 symmetrical to each other with respect to a strip 127 as well as for the embodiments of the other figures.

[0095] Views 6A, 6B, 7A and 7B represent an insulated conductive wall 200 comprising a conductive core 202 and an insulating sheath 204. The wall 200 corresponds for example to the wall 108c of FIG. 2. The views also represent the conductive pad 120. The views also represent the semiconductor material of the electron storage regions and more particularly the semiconductor material of the opening 116, of the opening 131 and of the opening 129.

[0096] In Figure 6A, the doping of the semiconductor material located in the opening 129 but not located under the connection pad 120, is greater than approximately 10A18 dopants / cmA3 (the symbol A representing the power function), over a thickness substantially equal to 0.2 μm. This corresponds substantially to a region 206 of view 6A.

[0097] The doping of the semiconductor material located in the opening 116, more precisely along the wall 200, is between approximately 10A10 dopants / cmA3 and 10A18 dopants / cmA3, for a depth of up to 1.5 pm. This corresponds substantially to a region 208 of view 6A. The concentration is for example decreasing in the region 208 from the surface of the opening 116.

[0098] Regions 206 and 208 are connected by a region 210. The doping of region 210 is for example between approximately 10A15 and 10A18 dopants / cmA3. Region 210 is located on the surface of the semiconductor material. Region 210 is located in contact with pad 120. The thickness of region 210 is for example substantially equal to 0.1 μm. The thickness of region 210 is for example less than the thickness of region 206.

[0099] A region 212 located below regions 206 and 210 has a doping of less than -10A16 dopants / cmA3. Region 212 is located just below regions 206 and 210. Region 212 extends, for example, from regions 206 and 210 to a depth of about 0.5 pm.

[0100] The remainder of the semiconductor material considered has, for example, a doping between -10A13 and -10A16 dopants / cmA3.

[0101] Region 208 extends partially under region 212. Negative dopant concentrations correspond to doping of the opposite type to positive concentration doping. Thus, a doping lower than a negative doping corresponds to a number higher dopants of the type whose concentration corresponds to a negative value.

[0102] The dimensions of regions 210 and 212 are chosen such that the path for electrons heading towards region 206 is relatively narrow. Thus, there is little risk of leakage.

[0103] In Figure 6B, it is observed that the electrostatic potential is highest in region 210 and in the part of region 208 closest to region 210. A pocket 214 is also observed, within region 208, having an electrostatic potential value higher than the potential values ​​of the parts of region 108 which surround it. This pocket 214 constitutes an electron storage pocket, that is to say that during reading, electrons will remain stored in this pocket and will not move towards region 206 to be read. The read value is therefore not entirely representative of the number of electrons which were present in the memory, and therefore of the number of electrons having been generated by the photodiode.

[0104] View 7A is similar to View 6A. View 7A differs from View 6A in that the region 212 extends deeper. Thus, the 212 region extends to about 0.7 pm. In addition, the 212 region is more lightly doped, i.e., much of the 212 region has doping below -10AI8 dopants / cmA3.

[0105] In view 7B, the absence of pocket 214 is observed. The electrostatic potential gradually decreases from region 210.

[0106] During the reading step, there will therefore be no electrons which remain stored in the pocket 214 and therefore cannot be read.

[0107] Thus, the presence of a region 212 extending more deeply ensures the absence of the pocket 214.

[0108] Figure 8 represents the electrostatic potential on a path going from the first electron storage region to the second electron storage region of the same memory area in two different cases. Curve 215 corresponds to the case of Figure 6 and curve 217 corresponds to the case of Figure 7.

[0109] It is observed that each curve includes an extrema located at the same distance D. This distance D corresponds to the opening 116, that is to say to the place where one passes from the first region to the second region. This maximum therefore corresponds to the barrier which must be crossed by the electrons to pass to the second electron storage region.

[0110] It is observed that by moving from the case of Figure 6 to the case of Figure 7, that is to say by increasing the thickness of the region 212, the barrier to be crossed by the electrons is increased.

[0111] The inventors have determined that by increasing the thickness of region 212, it is possible to remove the presence of electron storage pockets, however this increases the barrier to be crossed between the two electron regions. This can pose problems, particularly in the case where the barrier between the active zone and the first electron storage region is lower than the barrier between the two storage regions. Indeed, some electrons could then return to the active zone rather than crossing the barrier to the second region.

[0112] The inventors have further determined that increasing the distance between wall 108c and region 212 results in a decrease in the barrier between regions 106. However, this increases the dimensions of region 208 in depth. There is therefore a risk that certain electrons, located in depth, will not be read.

[0113] Figure 9 shows another embodiment of a photodiode 275. The photodiode 275 includes elements identical to the elements of Figure 1, referenced in the same way. These elements are not detailed again.

[0114] The photodiode 275 of Figure 9 differs from the photodiode 100 of Figure 1 in that each wall 108c comprises two distinct portions. Each wall 108c comprises a first portion 277 extending from the wall 108d in the main direction of the electron storage regions 106. Each wall 108c further comprises a second portion 279. The second portion 279 is located in the extension of the first portion 277. The second portion is therefore located between the first portion and the wall 112. The first portion 277 and the second portion 279 are separated by an opening 281.

[0115] The conductive pad 120 does not cover the opening 281. The conductive pad 120 for example partially covers the second part 279.

[0116] The voltage received by the conductive core of the second part 279 of the wall 108c is independent of the voltage received by the conductive cores of the other insulated conductive walls 108 and 112. In particular, the voltage received by the conductive core of the second part is independent of the voltage received by the conductive core of the first part 277 of the wall 108c.

[0117] Preferably, the opening 281 is as close to the pad 120 as current technologies allow without being located under the pad 120. For example, the dimension of the second portion 279 in the main direction of the electron storage regions 106 is for example substantially equal to 0.4 μm. The dimension of the opening 281 in the main direction of the electron storage regions 106 is for example substantially equal to 0.2 μm. Preferably, the dimension of the first portion 277 in the main direction of the regions 106 is at least five times greater than the dimension in the same direction of the second portion 279, preferably at least ten times greater.

[0118] The operating steps of this embodiment are identical to that of the embodiment of FIG. 1. However, during the step of generating electrons in the active zone 102 and storing the electrons, the electrons move from the storage area closest to the active area to the other storage region via opening 281. This is because the electrostatic potential barrier is lower in opening 281 than in opening 116. Preferably, the electrostatic potential barrier of opening 281 is lower than the barrier of opening 114.

[0119] As a variant, the conductive pads 120 may have a U shape. For example, each conductive pad 120 comprises a main portion identical to the conductive pads 120 of FIG. 9, and two secondary portions not shown each extending above one of the storage regions 106. The secondary portions do not extend above the opening 281.

[0120] Figure 10 shows another embodiment of a photodiode. The photodiode 300 includes elements identical to the elements of Figure 9, referenced in the same way. These elements are not detailed again.

[0121] The photodiode 300 differs from the photodiode 275 in that the walls 108a and 108b comprise projecting portions 302. The walls 108a and 108b therefore comprise a main portion and a projecting portion 302. The main parts of the walls 108a and 108b are identical to the walls 108a and 108b of FIG. 9. The portions 302 extend from the main portions towards the storage regions 106. The portions 302 are preferably located on either side of the opening 281. Preferably, the portions 302 are therefore not covered, even partially, by the conductive pad 120.

[0122] The presence of the portions 302 makes it possible to reduce the electrostatic potential barrier of the opening 281.

[0123] Figure 11 shows the electrostatic potential in a portion of the embodiment of Figure 10 during three stages of operation. Figure 11 includes Y and Z axes representing distances in micrometers. The Y axis is in the main direction of the regions 106 and the Z axis is in the direction perpendicular to the Y axis in the plane of Figure 11.

[0124] Although the observations made in relation to the embodiment of Figure 10 in a structure comprising two symmetrical photodiodes similar to Figure 2, similar observations can be made in relation to the embodiment of Figure 9 and with the embodiment of Figure 13 which will be described subsequently.

[0125] Figure 11 only represents a part of one of the memory areas 104, in particular the part comprising the conductive pad 120, the portions 277 and 279 of the wall 108c, the opening 281, a part of the strip 127 and the opening 129.

[0126] The three steps described in relation to FIG. 1 are steps in reading one of the memory areas 104.

[0127] During a first step, illustrated by view 1 1A, the pad 120 receives a positive voltage. In addition, the portion 279 of the wall 108c receives a negative voltage, for example the same voltage as the voltage received by other insulated conductive walls, for example a voltage substantially equal to -2 V.

[0128] The electrostatic potential under the conductive pad 120 is between approximately 2 and 3 V. The value of the potential decreases away from the strip 127, according to potential curves similar to curves 303 and 304. The potential in the storage regions 106 is between approximately 0.8 V and 2.5 V.

[0129] The electrons move towards the conductive pad 120.

[0130] During a second step, illustrated by view 11B, the value of the voltage received by the portion 279 increases, for example until reaching a value substantially equal to 0 V.

[0131] The electrons still flow toward the conductive pad 120. However, electron storage pockets 305 begin to form on either side of the portion 279. The electron storage pockets are locations at which there is an extrema of the electrostatic potential.

[0132] During a third step, illustrated by view 1 IC, the value of the voltage received by the portion 279 increases, for example until reaching the value of the voltage received by the conductive pad 120, for example until reaching a value substantially equal to 2.5 V.

[0133] The electrons move towards the conductive pad 120. The dimensions of the storage pockets 305 increase. For example, the storage pockets 305 extend along the portion 279, for example over the entire length of the portion 279.

[0134] During a following step not illustrated, the voltage received by portion 279 is again negative.

[0135] The electrostatic potentials then become similar to those of view 1 IA. The electrons stored in the pockets 305 are then attracted by the pad 120. The pockets 305 are located for example at the level of the upper face of the regions 106. Thus, the electrons are easily attracted from the pockets towards the pad 120, and do not remain stored in depth.

[0136] The voltage of the pad 120 then becomes negative again so as to stop the reading step.

[0137] Figure 12 shows another embodiment of a photodiode 375.

[0138] Photodiode 375 is identical to photodiode 275 except for the number of electron storage regions 106. Common elements between photodiode 275 and photodiode 375 are referenced in the same manner and are not detailed again.

[0139] The photodiode 375 comprises, in each memory area 104, three electron storage regions 106. The three storage regions, as in FIG. 3, have for example a substantially parallelogram shape. In addition, the regions 106 have a main direction substantially parallel to each other, preferably parallel to the main direction of all regions 106 of the photodiode. The regions 106 are separated from each other by insulated conductive walls 108c' and 108c". The walls 108c' and 108c" are identical to the walls 108b of Figure 1.

[0140] Each of the walls 108c' and 108c" respectively comprises an opening 116' and 116". Preferably, the openings 116' and 116" are located on the same side of the memory area 104, for example on the side opposite the opening 114.

[0141] The pad 120 of this memory zone 104 is identical to the pads 120 described in relation to FIG. 9 and covers at least the two openings 116' and 116".

[0142] Each wall 108c' or 108c" comprises two distinct parts. Each wall 108c', respectively 108c", comprises a first part 277', respectively 277", extending from the wall 108d in the main direction of the electron storage regions 106. Each wall 108c', respectively 108c", further comprises a second part 279', respectively 279". The second part 279', respectively 279", is located in the extension of the first part 277', respectively 277". Each second part is therefore located between the corresponding first part and the wall 112. Each first part 277' or 277" and the corresponding second part 279' or 279" are separated by an opening 281' or 281".

[0143] The conductive pad 120 does not cover the openings 281' and 281". The conductive pad 120 for example partially covers the second parts 279' and 279".

[0144] The voltage received by the conductive core of the second parts 279' and 279" of the walls 108c' and 108c” is independent of the voltage received by the conductive cores of the other insulated conductive walls 108 and 112. In particular, the voltage received by the conductive core of each second part 279' or 279" is independent of the voltage received by the conductive core of the first part 277' or 277" of the corresponding wall 108c' or 108".

[0145] Preferably, each opening 281' or 281" is as close to the pad 120 as current technologies allow without being located under the pad 120. For example, the dimension of each second portion 279' or 279" in the main direction of the electron storage regions 106 is for example substantially equal to 0.4 μm. The dimension of each opening 281' or 281" in the main direction of the electron storage regions 106 is for example substantially equal to 0.2 μm. Preferably, the dimension of each first portion 277' or 277" in the main direction of the regions 106 is at least five times greater than the dimension in the same direction of the corresponding second portion 279' or 279", preferably at least ten times greater.

[0146] The operation of photodiode 375 is the same as the operation of photodiode 300.

[0147] Two photodiodes 375 may be arranged in the same way as the photodiodes 125 are arranged in FIG. 2, i.e. symmetrically to each other with respect to a strip 127 replacing the strip 110. The openings 129 and 131 are for example located in the strip 110 between the two openings 116' and 116".

[0148] An advantage of the embodiments of Figures 9, 10 and 12 is that the openings 281 allow less difficult passage between the different storage regions of the memory areas, by lowering the electrostatic potential barrier between the regions.

[0149] Another advantage of the embodiments of Figures 9, 10 and 12 is that the voltage received by the second part 279 of the walls 108c makes it possible to better attract the charges, in particular the charges which could have been located deep in the memory area and could then not be read.

[0150] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0151] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A photodiode comprising at least one memory area (104), each memory area comprising: at least two storage regions (106), the charge storage regions being connected by first (116) and second (281) openings; first (108a), second (108c) and third (108b) insulated conductive walls, the second wall (108c) forming the separation between two storage regions (106); a fourth insulated conductive wall (108d), connecting the first and second walls (108a, 108c); and a fifth insulated conductive wall (112), connecting the first and third walls (108a, 108b), the second wall comprising a first portion (277) extending from the fourth wall (108d) and a second portion (279) located between the first portion (277) and the fifth wall (112), the second opening (281) being between the first and second portions and the second opening (116) being between the second portion and the fifth wall.

2. The photodiode of claim 1, wherein the first opening (116) is at least partially covered by a connection pad (120).

3. A photodiode according to claim 2, wherein the second opening (281) is not covered by the connection pad (120).

4. Photodiode according to claim 2 or 3, in which the connection pad is a reading pad of a value representative of the quantity of charge in the memory area (104).

5. Photodiode according to any one of claims 2 to 4, in which the second opening (281) is located as close as possible to the connection pad (120) without being located under the pad (120).

6. Photodiode according to any one of claims 1 to 5, in which the main directions of the storage regions (106) of the same memory area (104) are parallel.

7. A photodiode according to any one of claims 1 to 6, wherein each insulated conductive wall (108, 112) comprises a conductive core configured to receive, during operation of the photodiode, a negative voltage, the insulating core at least par- partially surrounded by an insulating sheath.

8. A photodiode according to any one of claims 1 to 7, wherein the first (116) and second (281) openings are separated by the second portion (279) of the second insulated conductive wall (108c).

9. A method of using a photodiode according to any one of claims 1 to 8, comprising a first step during which electrons are generated and stored in the memory area(s) and a second step of reading the quantity of electrons in the memory area(s).

10. A method according to claim 9 as appended to claim 10, wherein the second portion (279) receives a negative voltage during the first step.

11. The method of claim 10, wherein the voltage received by the second portion (279) reaches a positive value during the second step.

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