Phase-change memory

Abstract

Phase-Change Memory This description relates to a process for manufacturing phase-change memory comprising: a) a step of forming a phase-change memory cell array, each cell being separated from neighboring cells in the same row of the array and from neighboring cells in the same column of the array by the same first distance (L1), and b) a step of etching, in each row or each column, one memory cell out of N, N being at least equal to 2. Figure for the abstract: Fig. 3

Description

Title of the invention: Phase change memory Technical field

[0001] The present description relates generally to electronic devices, and more particularly to phase change memories. Prior art

[0002] Phase change materials are materials that can switch, under the effect of heat, between a crystalline phase and an amorphous phase. Since the electrical resistance of an amorphous material is significantly higher than the electrical resistance of a crystalline material, this phenomenon can be useful for defining two memory states, for example 0 and 1, differentiated by the resistance measured across the phase change material. Summary of the invention

[0003] One embodiment overcomes all or part of the drawbacks of known phase change memories.

[0004] One embodiment provides a method for manufacturing a phase-change memory comprising: a) a step of forming a matrix of phase-change memory cells, each cell being separated from neighboring cells of the same row of the matrix and from neighboring cells of the same column of the matrix by a first distance, and b) a step of etching, in each row or each column, one memory cell out of N, N being at least equal to 2.

[0005] According to one embodiment, N is equal to 5.

[0006] According to one embodiment, the method comprises, before step a), the formation of a matrix of conductive vias, each via being separated from neighboring vias in the same row and from neighboring vias in the same column of the matrix by a second distance.

[0007] According to one embodiment, step a) comprises the formation, on the matrix of vias, of a stack comprising a layer of a resistive material, a layer of a phase change material and a conductive layer.

[0008] According to one embodiment, step a) comprises etching the stack so as to delimit the cells of the matrix, each cell comprising a portion of the layer made of a resistive material, a portion of the layer made of a phase change material and a portion of the conductive layer.

[0009] According to one embodiment, step b) comprises the formation of a cavity uncovering the via on which each etched cell was formed.

[0010] According to one embodiment, step b) comprises the etching of lines of cells, the etched lines being separated from each other by N1 lines of unetched cells.

[0011] According to one embodiment, step b) comprises etching a cell on N on each row and on each column.

[0012] According to one embodiment, the cells formed during step a) are identical.

[0013] Another embodiment provides a phase change memory comprising a plurality of phase change memory cells arranged in rows and columns, in which each row, or column, comprises groups of memory cells, the cells of the same group being separated two by two by the same first distance, the groups being separated two by two by a third distance.

[0014] According to one embodiment, the third distance is equal to the sum of twice the first distance and the dimension of the memory cell in the direction of the row, or of the column.

[0015] Another embodiment provides a memory as described above, obtained by the method described above. Brief description of the drawings

[0016] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0017] [Fig.l] represents a device resulting from a step of an embodiment of a method of manufacturing a phase change memory;

[0018] [Fig.2] represents a device resulting from another step of an embodiment of a method for manufacturing a phase change memory;

[0019] [Fig.3] represents a device resulting from another step of an embodiment of a method of manufacturing a phase change memory;

[0020] [Fig.4] schematically represents several arrangements of the cavities of the embodiment of [Fig.3];

[0021] [Fig.5] represents a device resulting from another step of an embodiment of a method of manufacturing a phase change memory; and

[0022] [Fig.6] represents a device resulting from an alternative step of the step of [Fig.3]. Description of the embodiments

[0023] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0025] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0027] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0028] Figures 1 to 5 represent steps, preferably successive, of an embodiment of a method for manufacturing a phase change memory. The phase change memory comprises a plurality of memory cells, each memory cell being for example configured to store data, for example binary data. The memory cells are placed in a matrix of cells, comprising rows and columns. Figures 1 to 3 and 5 are for example in the plane of a row of the matrix.

[0029] [Fig. 1] represents a device resulting from a step of an embodiment of a method for manufacturing a phase change memory.

[0030] During this step, an insulating layer 10 is formed on a substrate 12. The substrate 12 is for example a semiconductor substrate, for example made of silicon, or a semiconductor on insulator (SOI) type substrate. The insulating, or dielectric, layer 10 is for example a single insulating layer, or corresponds to a stack of insulating layers. The insulating layer(s) of the layer 10 are made of one or more dielectric materials, for example silicon oxide or silicon nitride. In the following description, it is considered for example that the layer 10 comprises a single insulating layer.

[0031] Conductive vias 14 are formed through the layer 10. The vias 14 pass through the layer 10. In other words, the vias 14 extend from an upper face of the layer 10 to a lower face of the layer 10. The lower end of the vias is for example in contact with the substrate 12. The upper end of the vias is preferably flush with the upper face of the layer 10.

[0032] The vias 14 are located regularly, that is to say periodically, in the layer 10. The vias 14 are located at the locations of the memory cells. The vias 14 therefore form a matrix and form rows and columns. [Fig.l] represents for example a row of the matrix. Each via 14 is separated from the vias neighbors belonging to the same row or column, by the same distance. Thus, each row or column of the matrix includes 14 vias separated two by two by this same distance.

[0033] Selection elements 13 are for example formed between the vias. The selection elements are for example covered by an insulating layer 17. In the example of [Fig.l], the selection elements are transistors, formed in and on the substrate 12. The transistors are represented by their gate 15. The neighboring transistors of the same row have for example a common drain or source region. The transistors of the same row are for example thus connected in series by their drain and source regions.

[0034] The lower end of each via 14 is for example in contact with a drain or source region of a transistor 13.

[0035] A layer 16 of a resistive material is formed on the layer 10 and on the upper ends of the vias 14. The layer 16 is for example made of a conductive material, for example metal. For example, a layer 16 is formed on each row of the matrix. Each layer 16 is preferably separated from the layers 16 of the other rows by an insulating material not shown. The assembly comprising the layers 16 and the insulating material separating them preferably forms a flat layer. Each layer 16 is in contact with the upper end of each via of the row. Each layer 16 has for example an L shape in a plane, for example a plane orthogonal to the plane of [Fig.l].

[0036] A layer 18 of a phase change material is formed on the layer 16, for example on the assembly comprising the layers 16 and the insulating material separating them. The layer 18 is for example made of an alloy of germanium, antimony and tellurium (GeSbTe or GST). The material of the layer 18 is for example doped. As a variant, the material of the layer 18 is not doped. The layer 18 preferably extends over all the layers 16. The layer 18 preferably extends continuously over the entire matrix.

[0037] A conductive layer 20, for example made of a metal, is formed on the layer 18. The conductive layer 20 covers, for example, the entire layer 18.

[0038] [Fig.2] represents a device resulting from another step of an embodiment of a method of manufacturing a phase change memory.

[0039] The step of [Fig. 2] comprises an etching step for delimiting memory cells 22. During this step, cavities 24 are formed through layers 16, 18 and 20 and, for example, in layer 10. The cavities 24 are located between the cells 22. The cavities 24 extend, for example, in the direction of the rows of the memory cell matrix, between the cells of different rows, and in the direction of the columns of the memory cell matrix, between the cells of columns different. The cavities 24 thus form a grid or grid shape. The cavities are for example located opposite portions of the layer 10 not comprising a via 14.

[0040] Each memory cell delimited by the cavities 24 is located opposite a via 14. In other words, the cavities 24 delimit portions of the layers 16, 18 and 20. Each memory cell 22 therefore comprises, from a via 14, a stack comprising a portion of the layer 16, forming a resistive element, a portion of the layer 18, and a portion of the layer 20 forming an upper electrode.

[0041] A matrix of memory cells 22 is thus formed. In other words, cells arranged in rows and columns are formed. The cells 22 are substantially identical, that is to say the dimensions of the cells are substantially equal two by two. More precisely, the memory cells are intended to be identical apart from manufacturing dispersions. The cells 22 are located regularly, that is to say periodically, in each row or column of the matrix of memory cells. [Fig. 2] represents for example a row of the matrix. Each cell 22 is separated from each neighboring cell belonging to the same row or the same column, by the same distance. In other words, the distances separating the neighboring cells of the same row or the same column are substantially equal. Thus, each row or column of the matrix comprises cells 22 separated two by two by this same distance.

[0042] The structure obtained is covered in a conformal manner by a protective layer 26, for example made of an insulating material, for example silicon nitride. The layer 26 covers in particular the walls and the bottom of the cavities 24 and the upper face of the memory cells. In other words, the layer 26 covers the layer 10, the lateral faces of the portions of the layers 16, 18 and 20 and the upper face of the portions of the layer 20.

[0043] The structure is for example covered with a protective layer 28, for example an insulating layer, for example made of silicon oxide.

[0044] [Fig. 3] represents a device resulting from another step of an embodiment of a method of manufacturing a phase change memory.

[0045] This step includes a step of etching certain memory cells. In other words, the vias 14 corresponding to the memory cells etched during this step are discovered by the etching step.

[0046] More precisely, cavities 30 are formed at certain memory cells of the matrix. Each cavity 30 opens at the upper face of layer 28 and extends to via 14. In particular, the portions of layers 16, 18 and 20 of the cells etched during this step are removed entirely. The etching is preference stopped in layer 10. Layer 26 of each cell is therefore separated from layer 26 of the other cells by one of the cavities 30.

[0047] For example, the vias 14 are not etched. In other words, the cavity uncovers the vias 14 without etching them. For example, the layer 10 surrounding the vias is not etched. For example, the vias 14 are still surrounded, after the etching step, by a portion of material from the layer 10.

[0048] For example, the cavity 30 does not extend over the entire height of the vias 14. In other words, the cavity 30 extends, for example, partially over the height of the layer 10. The selection elements are, for example, not etched. The cavity 30 does not reach the substrate 12.

[0049] In the example of [Fig. 3], one cell out of N is etched. The value N is, in the example of [Fig. 3], equal to 5. Thus, in the example of [Fig. 3], one memory cell out of five is etched and replaced by a cavity 30. In other words, each row, or column, preferably comprises groups of Nl cells, here four cells. Thus, each row comprises a succession of Nl cells, a cavity 30, Nl cells, a cavity 30, etc.

[0050] The cells of the same group are separated two by two by the same distance LL. In other words, the distances between two neighboring cells of the same group, located on the same row or the same column, are substantially equal. The groups are separated from each other by the cavities 30. The dimensions of the cavities 30 are less than the sum of twice the distance between two cells and the dimension of the cell in the same direction. Two neighboring groups of cells are separated by the same distance L2. In other words, the cells closest to each other of two neighboring groups of cells are separated by the distance L2. The distances separating the cells closest to each other of two neighboring groups of cells are all substantially equal to each other, and substantially equal to the value L2.The distance L2 between two cells separated only by a cavity 30 is equal to the sum of twice the distance between two cells and the dimension of the cell in the same direction.

[0051] [Fig. 4] schematically represents several examples of arrangements of the cavities of the embodiment of [Fig. 3]. [Fig. 4] comprises views A and B, each corresponding to a possible arrangement of the memory cells 22 and the cavities 30.

[0052] Each of views A and B schematically represents a matrix of memory cells. In each of views A and B, the horizontal lines correspond to rows of the memory matrix and the vertical lines correspond to columns of the memory matrix. A memory cell is formed at each intersection of a row and a column. The memory cells etched during the step of [Fig. 3] are represented by crosses at the corresponding intersections.

[0053] In the embodiment shown in view A, one cell out of N cells is etched in each column. The etched cells are part of the same rows. Thus, rows of cells are etched. In other words, the cell matrix comprises rows 37, in which all the memory cells have been etched during the step of [Fig. 3]. The rows 37 are separated by N1 rows in which no cells have been etched during the step of [Fig. 3].

[0054] The embodiment of view B differs from the embodiment of view A in that the etched cells are not part of the same rows. In other words, one cell out of N cells is etched in each column, the etched cells of each column being for example on a different row from the etched cells of at least one of the neighboring columns. For example, the etched cells of each column are offset by one row, preferably in the same direction, relative to the etched cells of the neighboring column.

[0055] According to one embodiment, a memory cell array may comprise several regions, at least some regions having different arrangements.

[0056] [Fig.5] represents a device resulting from another step of an embodiment of a method of manufacturing a phase change memory.

[0057] During this step, the cavities 30 are filled with an insulating material 40, for example the same material as the material of the layer 28.

[0058] This step further comprises the formation of vias. Vias 42 are formed so as to reach the portions of layers 20 of each memory cell. In other words, a via is formed opposite each cell. Each cell is thus in contact, through layer 20, with a via 42. Each via 42 extends from the upper face of layer 28, passes through layers 28 and 26 and reaches layer 20.

[0059] Vias 44 are formed so as to reach the vias 14 opposite the cavities 30. In other words, a via 44 is formed in each cavity 30. The via 44 reaches, and is in contact with, the via 14 uncovered by the cavity 30. Each via 44 extends from the upper face of the material 40 to the via 14.

[0060] Vias 42 and 44 are made of conductive materials, for example metal, for example copper or tungsten.

[0061] When programming or reading a memory cell, a current is formed between via 14 and via 42 of the cell. The current flows, for example, through via 44 closest to the cell and the selection elements between the cell and said via 44 so as to reach via 14.

[0062] [Fig.6] represents a device resulting from an alternative step of the step of [Fig.3],

[0063] This step includes, like the step of [Fig.3], the etching of certain memory cells. The step of [Fig.6] differs from [Fig.3] in that the cells are etched in groups of at least two cells, for example X cells, X being an integer at least equal to 2. In other words, the memory cells form groups of NX cells, the groups being separated by a cavity 50 resulting from the etching of X memory cells.

[0064] The next step, not shown, corresponding to [Fig.5], differs in that the via 44 is for example in contact with the two uncovered vias. The two vias are thus short-circuited.

[0065] It would have been possible to choose to form only the cells that one wishes to keep and therefore to form the cavities separating the groups of cells during the formation of the memory cells. However, this would lead to differences in dimensions between the cells of the same group, in particular between the cells located at the edges of the group and the cells located inside the group.

[0066] An advantage of the described embodiments is the reduction of variations between the different memory cells.

[0067] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0068] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Method for manufacturing a phase change memory comprising: a) a step of forming a matrix of phase change memory cells (22), each cell (22) being separated from the neighboring cells (22) of the same row of the matrix and from the neighboring cells (22) of the same column of the matrix by a first distance (L1), and b) a step of etching, in each row or each column, one memory cell out of N, comprising the formation of a cavity (30) revealing a via (14) on which each etched cell is formed, N being at least equal to 2.

2.

3. Method according to claim 1, in which N is equal to 5. Method according to claim 1 or 2, comprising, before step a), the formation of a matrix of conductive vias (14), each via (14) being separated from the neighboring vias (14) of the same row and from the neighboring vias (14) of the same column of the matrix by a second distance.

4. The method of claim 3, wherein step a) comprises forming, on the via array (14), a stack comprising a layer of resistive material (16), a layer of phase change material (18) and a conductive layer (20).

5. Method according to claim 4, in which step a) comprises etching the stack so as to delimit the cells (22) of the matrix, each cell comprising a portion of the layer (16) of a resistive material, a portion of the layer (18) of a phase change material and a portion of the conductive layer (20).

6. A method according to any one of claims 1 to 5, wherein step b) comprises etching lines (37) of cells, the etched lines being separated from each other by N1 lines of unetched cells.

7. A method according to any one of claims 1 to 5, wherein step b) comprises etching one cell out of N on each row and on each column.

8. A method according to any one of claims 1 to 7, wherein the cells (22) formed during step a) are identical.

9. A phase change memory comprising a plurality of phase change memory cells (22) arranged in rows

10. and in columns, in which each row, or column, comprises groups of memory cells, the cells of the same group being separated two by two by the same first distance (L1), the groups being separated two by two by a third distance (L2), the memory being obtained by the method according to any one of claims 1 to 8. Memory according to claim 9, wherein the third distance (L2) is equal to the sum of twice the first distance (L1) and the dimension of the memory cell in the direction of the row, or of the column.

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