QUANTUM DEVICE INTEGRATING A BURIED METALLIC ELECTRODE

Abstract

Realization of a spin-qubit quantum device, comprising: - a first semiconductor portion (141) and a second semiconductor portion (142) juxtaposed to the first semiconductor portion, said semiconductor portions being formed in a surface layer of a semiconductor-on-insulator substrate and arranged on an insulating layer (12) of said semiconductor-on-insulator substrate, the substrate being provided with a semiconductor support layer (11) such that said insulating layer (12) is arranged between said support layer and said surface layer, - several pairs (221, 222) of front control grids,Each pair being formed respectively of a first front control grid (221) covering a region of the first semiconductor portion (141) to form a first quantum island and of a second front control grid (222) covering a region of the second semiconductor portion (142) forming a second quantum island, an insulating region (160) being provided between the first quantum island and the second quantum island so as to allow electrostatic coupling between the first quantum island and the second quantum island, the quantum device being provided with a rear conducting electrode (150) disposed above the insulating coupling region (57a-57b-61), said rear conducting electrode (150) being formed of a region of alloy of metallic and semiconductor materials arranged in said semiconductor support layer (11) of the semiconductor-on-insulator substrate. Figure for the abstract: 17,

Description

Description Title of the invention: INTEGRATING QUANTUM DEVICE A BURIED METAL ELECTRODE technical field

[0001] …— This application relates to the field of quantum electronic devices and in particular that of the realization of a quantum device with quantum bits (also called quantum bits or qubits) made up of semiconductor islands and using, in addition to front grid electrodes located above the islands, an electrode rear control arranged below the level in which the islands are located. PREVIOUS STATE OF THE ART

[0002] — Quantum islands (sometimes also called quantum boxes or quantum dots) form the basic elements of a quantum electronic device. The islands quantum particles are typically formed in a layer of semiconductor material. in which potential wells are implemented to confine carriers, electrons or holes, in the three dimensions of space. Quantum information is then encoded via the spin of the carrier. These are then called spin qubits.

[0003] — According to one approach, electrons are confined by field effect under electrodes using grids similar to those of transistor structures, and the information is encoded in the spin of these electrons. These so-called "front" grids are arranged above the set of quantum islands.

[0004] — For certain applications, a back electrostatic control is used in order to to better modulate the electrostatic environment of quantum islands. Such control is typically achieved by means of an additional electrode thus located at- below the set of quantum islands.

[0005] = This type of quantum device generally operates at very low temperatures. which implies that if we wish to make the rear grille out of semiconductor material, This must be very heavily doped so that the grid can remain conductive and functional. tional.

[0006] — However, heavily doping a substrate by ion implantation poses the risk of inducing residual dopants in the semiconductor layer in which the islands are intended. This is not compatible with the proper functioning of a device quantum.

[0007] — Another method that would include a plate transfer step with an area already doping to create the rear grille would, however, present the disadvantage of being complex to implement and to induce significant process variability.

[0008] The same applies to a method that would consist of making the rear grid by structuring the back face of a substrate, for example by forming a conductive via through the back face of this substrate on which the islands are planned. Furthermore, for certain applications, quantum devices incorporate an additional conductive line through which an RF signal is passed to manipulate electron spin. Ideally, such a conductive line should be located as close as possible to the semiconductor islands. It is therefore known to place this line alongside the semiconductor islands, or to position such a line above the islands, for example, in a first layer of metal. However, such arrangements present a problem of space constraints. Description of the invention In one aspect, the present invention relates to a spin-qubit quantum device comprising: -a first semiconductor portion and a second semiconductor portion juxtaposed to the first semiconductor portion, said semiconductor portions being formed in a surface layer of a semiconductor-on-insulator substrate and arranged on an insulating layer of said semiconductor-on-insulator substrate, the substrate being provided with a semiconductor support layer such that said insulating layer is arranged between said support layer and said surface layer, several pairs of front control grids, each pair being formed respectively of a first front control grid covering a region of the first semiconductor portion to form a first quantum island and a second front control grid covering a region of the second semiconductor portion forming a second quantum island, an insulating region being provided, in particular in terms of size and composition, between the first quantum island and the second quantum island so as to allow electrostatic coupling between the first quantum island and the second quantum island, the quantum device being equipped with a back-conducting electrode disposed vertically above the insulating region, said back-conducting electrode being formed of a region based on metallic material arranged in said semiconducting support layer of the semiconductor-on-insulator substrate. Such an arrangement of the rear electrode makes it possible to free up space above all the quantum islands in order in particular to be able to integrate possible additional control grids. Such an arrangement of the rear control electrode is placed here as close as possible to the active area in order to obtain optimized ESR coupling. Advantageously, the region based on metallic material can be formed from an alloy. of metallic and semiconductor materials Advantageously, the metallic region can also be capable of adopting superconducting properties. Operation at very low temperatures, in particular on the order of several millikelvins, can thus be expected. The region based on metallic material can be based on one of the following materials: Ta, Pt, Nb, TiN, Co, V. According to one possible implementation, the rear conductive electrode is configured to carry an RF signal. According to a particular implementation of the device, the rear conducting electrode can extend under and opposite the insulating region without extending opposite either of the said first control grid and second control grid. According to another aspect, the present invention relates to a method for making a device as described above. In another respect, the present invention relates to a method for manufacturing a quantum device, the method comprising, in this order, steps consisting of: -to form, on a so-called "active zone" of a surface layer of a semiconductor-on-insulator substrate equipped with a semiconductor support layer and an insulating layer arranged between the support layer and said surface layer, a plurality of grid blocks, - to form a separation trench through said grid blocks so as to divide each grid block into a pair of front control grids, said separation trench being made extending through the active zone so as to divide the active zone into a first semiconductor portion and a second semiconductor portion, said trench also extending through the insulating layer of the substrate and having a bottom exposing an area of ​​the support layer, -form a rear conductive electrode at the bottom of the trench. Such a process: - allows for very precise positioning of the rear control electrode, - is less invasive than a back-face process, particularly one in which the back face of a substrate is structured; - avoids the need for excessive doping of the substrate to fabricate the back electrode, - remains compatible with the additional integration of exchange grids arranged above the semiconductor islands. The rear conducting electrode can be formed in particular through the following steps: - metal deposit on said area of ​​the exposed support layer at the bottom of the trench, - heat treatment so as to form an alloy between said metal and semiconductor material of the support layer area. Advantageously, the process may further include, after the formation of the grid blocks and prior to the fabrication of the back control electrode: - the formation of an etching stop layer on said grid blocks, the trench being made through said etching stop layer formed on the grid blocks. According to one possible implementation, the process may further include, after grid formation and prior to the formation of the etching stop layer, the following steps: - growth of doped semiconductor material on regions of the active area arranged on either side of the gate blocks, so as to form dopant reservoirs, - silicification of an upper face of said tanks and grid blocks. According to one possible implementation of the process in which, prior to the metal deposition to create the alloy region of metallic and semiconductor materials, the process comprises the following steps: - formation of dielectric protection zones on lateral sides of the trench, the dielectric protection zones being arranged so as to extend between the first semiconducting portion and the second semiconducting portion and to reveal the area of ​​the support layer at the bottom of the trench. According to one possible embodiment, after formation of the back conductive electrode, the process may include filling the trench by depositing at least one dielectric layer, the dielectric layer and the dielectric protection zones having a composition and arrangement designed to allow electrostatic coupling between the first semiconductor portion and the second semiconductor portion. According to one possible implementation of the process in which said trench extends into a given part of the substrate located on the periphery of the active zone, and in which, after the deposition of said at least one dielectric filling layer, the process comprises: the creation of contact pads, at least one of which is a contact pad for said back control electrode, by: - formation of at least one hole through the dielectric layer, said hole opening into said given part exposing the support layer, - filling the hole with a conductive material. Brief description of the drawings The present invention will be better understood upon reading the description of the given exemplary embodiments, provided for illustrative purposes only and in no way limiting the application, with reference to the accompanying drawings in which: [Fig.1] [Fig.2] [Fig.3] [Fig.4A] [Fig.4B] [Fig.4C] [Fig.4D] [Fig.5A] [Fig.5B] [Fig.5C] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10A] [Fig.10B] [Fig.10C] [Fig.11] [Fig.12] [Fig.13] [Fig.14] [Fig.15A] [Fig.15B] [Fig.16A] [Fig.16B] [Fig.16C] serve to illustrate an example of a manufacturing process for a quantum device implemented according to the invention. [Fig.17] [Fig.18] serve to illustrate an example of a quantum device implemented according to the invention. Identical, similar or equivalent parts of the different figures carry the same numerical references in order to facilitate the transition from one figure to another. The different parts represented on the ligurian figures are not necessarily on a uniform scale, in order to make the figures more legible. In addition, in the description below, terms that depend on the orientation of the structure such as "above", "below", "rear", "front", "peripheral" apply assuming that the structure is oriented as illustrated in the figures. DETAILED DESCRIPTION OF SPECIFIC METHODS OF IMPLEMENTATION We refer first to [Fig.1] which represents a possible starting material for the realization of a spin qubit quantum device and which is in the form of a 10-type semiconductor-on-insulator substrate. The substrate thus comprises a support layer 11 made of semiconductor material, a buried insulating layer 12 disposed on the support layer 11 and a superficial semiconductor layer 13 disposed on the insulating layer. The substrate is typically a silicon-on-isothiazolinone (SOI) substrate with a surface layer 13 made of silicon, specifically silicon (Si) when this layer is intended to host electron spin qubits. Other semiconductor materials can be considered for the surface semiconductor layer 13. In particular, when this layer is intended to host hole spin qubits, the surface layer can be made of silicon (Si, Ge), with x preferably ranging from 0% to 70%. In this case, the insulating layer 12 and the support layer 11 are typically, respectively, a silicon oxide layer commonly called "BOX" (for "Buried Oxide") and a silicon-based layer. The thickness of the surface layer 13, for example, is between approximately 5 nm and 50 nm, typically around 10 nm. The thickness of the buried insulating layer 12, for example, is between 15 nm and 150 nm. Within this range, a thickness close to 15 nm, typically around 25 nm, is preferred, as this layer may need to be etched later. The thickness of the support layer 11 (thicknesses being dimensions measured along the z-axis of the orthogonal coordinate system [O; x; y; z] shown in [Fig. 1]) can, for example, be around 775 µm when using a 300 mm wafer. Next ([Fig.2]), we can define in the surface layer 13 at least one active zone pattern 14. This can be achieved by photolithography and etching of the surface layer 13, in particular a plasma etching with stop on the insulating layer 12. Then, a grid stack covering the active area 14 is made. This stack is typically formed ([Fig.3]) of a grid dielectric layer 17 and one or more layers 18, 20 of semiconductor grid material(s) such as doped poly-silicon and / or metallic material(s) such as TiN, Al, or W. The gate dielectric 17 can be an oxide, in particular a silicon oxide obtained by deposition or oxidation of a surface thickness of the active region 14. For example, the thickness of the gate dielectric layer 17 can be on the order of 2 nm. In this case, according to a particular embodiment, the gate stack can itself be formed of a TiN metal layer, for example, on the order of 6 nm thick, and a polysilicon layer, for example, on the order of 30 nm thick. The grid stack can be coated with at least one masking layer, in particular one or more hard mask layers 21, 21' typically formed from insulating layers, for example in SiN and / or SiO. In the illustrated embodiment, a stack is made to form this masking, in particular a bi-layer stack, with a SiN layer 21 of thickness for example between 20 nm and 30 nm coated with a silicon oxide layer 21' of thickness for example between 20 nm and 30 nm. Next, a plurality of masking blocks 24a, 24c, 24d, 24e are defined by etching in order to create a plurality of distinct grid blocks 22a, 22b, 22c, 22d, 22e. Anisotropic etching, particularly using plasma, is performed to create the masking blocks 24a, 24b, 24c, 24d, 24e, and then the distinct grid blocks 22a, ..., 22e beneath them, reproducing the patterns of the latter. A structure obtained at the end of this step is illustrated in Figs 4A, 4B, 4C, 4D giving respectively a perspective view, a top view, a cross-sectional view along a longitudinal axis A which extends along the length of the active area (dimension measured parallel to the x-axis of the orthogonal coordinate system [O; X; y; Z] on [Fig. 4C]), and another cross-sectional view along a longitudinal axis B which extends along the width of the active area (dimension measured parallel to the y-axis of the orthogonal coordinate system [O; x; y; z] on [Fig. 4D]). The grid blocks 22a, …, 22e in this example have a parallelepiped bar shape. These bars typically extend in a direction orthogonal to that in which the active zone 14 extends, in other words, in the direction of the width of the active zone 14. The grid blocks 22a, …, 22e are preferably regularly spaced with a dense distribution, for example such that the distribution step is on the order of 100 nm. Insulating spacers 23, 25 can then be formed on either side of each of the grid blocks. The spacers 25, 25' can be produced by depositing a dielectric layer 24, positioned to fill inter-grid gaps. The insulating material for the spacers is typically chosen from one of the following materials: SiN, SiCO, SiBCN. The deposition process is preferably conformal, and in particular of the ALD (Atomic Layer Deposition) type, in order to fill the inter-grid cavities without creating filling defects. In one particular embodiment, the deposited dielectric layer 24 has a thickness of approximately 30 nm. In the embodiment illustrated in figures 5A, 5B, 5C, (giving respectively a perspective view, a top view, a cross-sectional view along a longitudinal axis A) this dielectric layer 27 is then etched so as to remove this layer from regions 14a, 14b of the active zone. To complete the formation of dopant reservoirs 33a, 33b on these regions 14a, 14b and increase their thickness, one or more layers of semiconductor material(s) 33 can then be grown on the exposed regions 14a, 14b of the active zone ([Fig. 6]). This can be achieved by epitaxial growth of silicon or by CVD (chemical vapor deposition), for example, of germanium. Doping can then be carried out by ion implantation or by in-situ doping performed concurrently with the growth of the semiconductor material layer(s) 33, for example, to form Si:P (phosphorus-doped silicon) or SiGe:B (boron-doped silicon germanium). In order to reduce the contact resistance of the dopant reservoirs 33a, 33b and / or the grid blocks 22a, … 22e when at least part of these blocks is made of doped semiconductor material, areas based on metallic material can then be formed on these reservoirs and / or grid blocks. To do this, we remove the 24a, …, 24e masking blocks arranged on the grid blocks so as to reveal the top face of the latter. Such removal can be achieved using a selective chemical etching process. For example, etching with H₂PO₄ at a temperature of approximately 100°C for one hour can be performed when the removed masking material is SiN. The etching time can be around 30 minutes for a SiN layer approximately 20 nm thick deposited by PECVD. We can then form regions of metal and semiconductor alloy. Thus, in the embodiment example illustrated in [Fig.7], such regions 45, 46 are formed respectively on a top face of the gate blocks and on a top face of the dopant reservoirs 33a, 33b. To achieve this, a silicification process can be carried out, including a step of depositing at least one layer of metal, such as Ni, Pt, W, Co, Ti, or V. The metal layer can optionally be covered with an encapsulation layer, which can be metallic. An example of encapsulation is formed by depositing TiN, with a thickness, for example, on the order of 10 nm. A heat treatment is carried out to achieve silicification. Such a treatment can be implemented at a temperature between 200°C and 900°C and for a duration adapted according to the treatment temperature. The unreacted metal can then be removed, for example by wet etching using a hot SPM (Sulfuric Peroxide Mix) solution. A second silicification anneal can also be performed. In the embodiment illustrated in [Fig. 7], regions 45, 46 of metal alloy and semiconductor, in particular silicide, are thus formed respec- tively on the grid blocks and dopant reservoirs. For example, the thickness of the 45, 46 silicidated regions can be on the order of 15 nm. This process is particularly distinctive in that it involves a step of cutting the active area 14 into separate and disjoint portions after the grid blocks have been formed. Such cutting is typically performed by engraving through an opening made in at least one masking element. Thus, in the example illustrated in [Fig.8], a 51 etching stop layer is first formed. This stop layer 51 can be of the CESL type (CESL stands for "Contact Etch-Stop Layer"), typically made of silicon nitride or a derivative material. The etch stop layer 51 can be produced here with a thickness, for example, on the order of 30 nm. A PECVD (Plasma-Assisted Chemical Vapor Deposition) deposition process can, for example, be used to deposit such a stop layer 51. A mask 52 is then formed, having a slot 53 that extends primarily along the length of the active zone (dimension measured parallel to the x-axis of the coordinate system [O; x; y; z] shown in [Fig. 9] and parallel to the axis A of the section plane). The slot 53 extends opposite the active zone 14 and also opposite a region of the substrate beyond the active zone 14, in which the surface semiconductor layer has been removed. The mask 52 can be formed from several stacked layers. In the particular embodiment illustrated in [Fig. 9], the mask 52 comprises three layers, with a first layer 52a forming a hard organic mask, for example a spin-on-carbon (SOC) layer of carbon, surmounted by a second anti-reflective layer 52b, for example a silicon anti-reflective coating (SIARC), and a third layer 52c which may be, in particular, a photosensitive resin layer. As an example, a slit 53 in the mask 52 with critical dimension Dc (the smallest dimension of a pattern other than its thickness, measured parallel to the plane [O; x; y]) of the order of 50 nm. Then, extending from slot 53, a trench 55 is formed to create a two-part cut in the grid blocks (figures 10A, 10B, 10C showing respectively a perspective view, a top view, and a cross-sectional view parallel to axis B). Trench 55 typically reproduces the pattern of slot 53. Dividing the grid blocks into two parts allows for the creation of a first set of grids 221 covering the first semiconductor portion 141 and a second set of grids 222 covering the second semiconductor portion 142, each of the grids from the first set being arranged opposite and forming a pair with a grid from the second set. This trench 55 is extended into the active zone 14 in order to divide this active zone 14 into two portions 141, 142. The trench 55 is constructed so as to have a bottom exposing the support layer 11 of the semiconductor-on-insulator substrate. The trench 55 extends alongside the active zone 14 and includes a portion that extends beyond the active zone 14 such that this part of the trench 55 is formed through a region of the substrate in which the surface semiconductor layer 13 is removed. The trench 55 can be created using anisotropic etching, typically with a plasma. The arrest layer 51, all the materials forming the grid stack, the active area 14 located in a portion of the surface layer 13 of the substrate, and the insulating layer 12 of the substrate, typically of the BOX type, are thus etched sequentially. The etching stops at the support layer 11 of the semiconductor-on-insulator substrate, for example, at the top face of this semiconductor support layer 11. Such a trench 55 allows access to the support layer 11 in order to create a back-control electrode at the level of the latter, and in particular at least partially within this support layer 11. As mentioned above, such a trench 55 also allows the active area 14 to be separated into two distinct portions 141, 142, the first portion 141 of the active area 14 serving as a region in which the qubits are located, while the second portion 142 of the active area 14 forming a charge detection region. The trench can extend into a part of the substrate located at the periphery of the active area 14 in order, for the purpose of subsequently creating a contact, to be able to access the support layer 10 in a part located outside the active area 14. According to a particular embodiment, prior to the formation of a back-control electrode by depositing at least one metallic layer in trench 153, protective zones 57a, 57b can be created against the lateral sides of trench 153 ([Fig. 11]). The protective zones 57a, 57b are thus arranged to cover regions of portions 141, 142 of the active zone 104 exposed by the construction of trench 55. The protective zones 57a, 57b are advantageously made of a dielectric material such as, for example, SiN, SiIBCN, SiO-, HfO-, Al-O-, or SiCO. In particular, the dielectric material of these zones 57a, 57b, as well as their thickness, can be chosen according to the desired level of electrostatic cutting between the two portions 141, 142 separated from each other by the trench 55. For example, the deposited dielectric material can have a thickness between 5 and 15nm. A deposit of typically dielectric protective material is thus made so as to conform to the sides of trench 55. This protective material is then removed by anisotropic etching ([Fig.12]), typically by means of a plasma, in order to remove it from the bottom of trench 55. This reveals again a zone 111 of the semiconducting support layer 11, at the bottom of trench 55. The back control electrode is then formed by first depositing a metallic material. Preferably, the back control electrode is made by forming a semiconductor alloy or compound and metal at the bottom of trench 55. This is typically achieved by silicification, with a process that may be similar to that described previously in relation to [Fig. 7] in order to form contact areas on the grid blocks and dopant reservoirs. Thus, a first step involves deposition of at least one layer of metal, such as Ni, Pt, W, Co, Ti, or V. A heat treatment is then performed. This treatment can be carried out at a temperature between 200°C and 900°C, with the duration adjusted according to the treatment temperature. For example, at a temperature of around 250°C, a duration of approximately 30 seconds can be expected. A selective silicification process can be used, so that the silicide forms only where the semiconductor material of the support layer 11 is exposed. The thickness of the silicide layer can be, for example, on the order of 15 nm or greater. This silicide layer 59 allows the formation of a back grid that is metallic and therefore not based on a doped semiconductor material. ([Fig.13]). Next, trench 55 ([Fig. 14]) is filled with one or more dielectric materials. This is done by depositing one or more successive layers of dielectric material(s) followed by CMP planarization (Chemical Mechanical Polishing). Here again, the dielectric filling material(s) can be chosen for their permittivity, depending on the desired level of electrostatic coupling between the two portions 141, 142 of the active zone 14, which are disjoint and separated from each other by trench 55. For example, the filling is carried out with a PMD (pre-metal dielectric) type dielectric 61, such as silicon dioxide. A conformal filling of trench 55 can be implemented for example by carrying out an FCVD deposition (for "Furace Chemical Vapor Deposition", i.e. CVD deposition in a furnace) and an HDP (for "High Density Plasma") deposition of TEOS type silicon oxide. Then (figures 15A and 15B respectively showing a perspective view and a cross-section parallel to axis B), contact pads are formed, with in part- particulars of the contact pads 7la, 72a, 73a, 74a, 75a on first grid blocks which are located on one side of the trench and cover the first part 141 of the active zone 14 and of the contact pads 71b, 72b, 73b, 74b, 75b on second grid blocks which are located on the other side of the trench 55, cover the second part 142 of the active zone 103a and are disjoint from the first grid blocks. Contact pads 78, 79 are also provided on the portions of the doping tanks. Similarly, at least one contact pad 77 is typically provided on the rear control electrode. The contact pads can be made by forming holes through the dielectric layer 61 and the etching stop layer 53, for example by photolithography and then plasma etching. The holes are then filled with a metal such as, for example, W. To make [Fig. 15A] more legible, the dielectric material 61 used to fill the trench and which covers the structure is not shown. Among these holes, one is typically planned to pass through trench 55 and open into a specific area exposing the support layer. Once this hole is filled with conductive material, a contact pad is formed for making contact with the rear electrode 150. According to one possible implementation (Figures 16A, 16B, 16C), this structure can be further constructed by forming additional electrodes 81, 82, 83, 84, called exchange grids, which extend above the semiconducting portions 141, 142, in a direction parallel to that of the blocks. These electrodes allow for modulation of the potential barriers between two successive quantum islands. They therefore modulate the coupling between the islands and thus enable control of the exchange energy of the quantum islands. To make Figure 16A more legible, the dielectric material 161, which fills the trench and covers the structure, is again not shown. Figure 17 shows a cross-sectional view of a spin qubit quantum device, which may have been made using a process as described above. The device comprises a first semiconductor portion 141 in which a row of quantum islands is provided, and a second semiconductor portion 142, juxtaposed to the first semiconductor portion, in which another row of quantum islands is implemented. The semiconductor portions 141 and 142 have oblong blocks, for example, parallelepiped-shaped blocks in which quantum islands are arranged and separated in pairs by a tunnel barrier. Dopant reservoirs are typically provided at the ends of these blocks. In the cross-sectional view of [Fig. 17], only the blocks extending in a direction orthogonal to the plane of the figure are shown. The islands of the first portion 141 are intended to form a first row of data qubits, while the islands of the second portion 142 form a second row of sensing elements for reading coded value from the data qubits of the first row. Above each island in the first row, a 221 front control grid is arranged, and opposite this 221 grid, above each island in the second row of detection islands, a 222 control grid is provided. The semiconductor portions 141, 142 are separated from each other by means of an insulating region 160. The dielectric constant of this region 160, which depends on its composition in dielectric material(s) and its dimensions, in particular the width W (dimension measured parallel to the y-axis of the orthogonal frame [O; x; y; z]) between the portions 141, 142, is provided between the first quantum island 141 and the second quantum island 142 so as to allow electrostatic coupling between these islands 141, 142. The coupling is such that the current in the charge detector is likely to vary typically by a factor of 10 depending on the occupancy rate of the quantum island. In the illustrated embodiment, the insulating region 160 is composed of dielectric zones 57a, 57b arranged respectively against the first semiconductor portion 141 and against the second semiconductor portion 142, and based on a dielectric material with dielectric constant ks, for example, silicon nitride, and a dielectric layer 60 between these zones 57a, 57b. The dielectric layer 60 is composed of a material different from that of the zones 57a, 57b, for example, silicon oxide, and has a dielectric constant ks such that ks = 1 / ks. Alternatively, the insulating region 160 may be made of a single dielectric material or composed of more than two distinct dielectric materials. In order to limit potential non-uniformity within the semiconductor portions 141, 142, it is advantageous to use one or more materials with low permittivity to form the insulating region 160.The dielectric materials used to form the insulating region 160 are chosen for their respective dielectric constants according to the desired level of coupling. Below and opposite the insulating region 160, in other words directly above this region 160, the device is equipped with an additional conductive electrode 150 made of a metallic material, in particular a metal-semiconductor alloy such as CoSi or VSi. This metallic electrode 150 is thus advantageously made of a material capable of forming a superconductor and operating at very low temperatures, in particular on the order of several millikelvins. For a distance separating the semiconductor portions 141, 142, for example, of between 40 and 50 nm, one can consider an effective relative permittivity of the material(s) separating these two semiconductor regions to be typically higher to 3. Electrode 150 typically extends in a direction orthogonal to the principal direction of the grid pairs 221, 222, that is, along the length of the semiconductor portions 141, 142. Such electrode 150, also called the "back gate," participates in controlling the respective spin states of the islands forming qubits by EPR coupling (for "Electron Spin Resonance," also called ESR in Anglo-Saxon terminology). This electrode 150 is adapted, by its composition and dimensions, to carry an RF signal, for example, on the order of several GHz, in order to generate an oscillating magnetic field. Since electrode 150 in this example is made under the insulating layer 12 of a semiconductor-on-insulator substrate, it is arranged as close as possible to the semiconductor portions 141, 142. This contributes to obtaining better coupling. An insulating layer 12, typically a thick buried oxide layer, is advantageously used to reduce the risk of potential non-uniformity in the semiconductor portions. The insulating layer 12 can be, for example, a BOX layer 25 nm thick. In the example illustrated in [Fig.17], the buried electrode 150 has a width D1 (dimension measured parallel to the y-axis of the orthogonal frame [O;x;y;z]) which corresponds approximately to that of the insulating region 160 between the semiconducting portions 141, 142. Thus, in the embodiment illustrated in [Fig.17], the buried electrode 150 is located directly above the region 160 located in a space between pairs 221, 222 of grids without extending in relation to either of these pairs of grids. As an alternative, as in the arrangement of [Fig.18], a wider rear electrode 150 can be provided so as to extend at least partially under the semiconducting portions 141, 142 without this significantly impacting the functionality of the device or the rear grid.

Claims

Demands

1. A spin-qubit quantum device comprising: --a first semiconductor portion (141) and a second portion semiconductor (142) juxtaposed to the first semiconductor portion conductive, said semiconductor portions being formed in a surface layer (13) of a semiconductor-type substrate on insulating and arranged on an insulating layer (12) of said substrate of type semiconductor on insulator, the substrate being provided with a layer (11) of semiconductor support such as said insulating layer (12) is arranged between said support layer and said surface layer, --several pairs (221, 222) of front control grids, each pair being formed respectively of a first control grid (221) before covering a region of the first semiconductor portion (141) to form a first quantum island and a second grid (222) control before covering a region of the second portion semiconductor (142) forming a second quantum island, a region insulating (160, 57a-57b-61) being present between the first quantum island and the second quantum island and so as to allow an electro- coupling static between the first quantum island and the second quantum island, the quantum device being equipped with a rear conductive electrode (150) arranged directly above the insulating region (160, 57a-57b-61), said rear conducting electrode (150) being formed of a region (59) with a base of metallic material arranged in said support layer (11) semi- conductive of the semiconductor substrate on insulator.

2. Device according to claim 1, wherein the region based on metallic material is formed from an alloy of metallic materials and semiconductor.

3. A device according to either claim 1 or 2, wherein the region at metallic material base is based on one of the following materials: Ta, Pt, Nb, TiN, Co, V.

4. Device according to any one of claims 1 to 3, in the electrode The rear conductor (150) is configured to carry an RF signal.

5. A device according to any one of claims 1 to 4, wherein the region insulating (160) is composed of different dielectric materials.

6. Device according to any one of claims 1 to 5, wherein the electrode rear conductive (150) extends below and opposite the insulating region (160) without elaborating with regard to either of the said first control grid (221) and second control grid (222).

7. Method for manufacturing a quantum device, the method comprising, In this order, the steps consist of: -to form on an area (14) called the "active zone" of a surface layer (13) of a semiconductor-on-insulator substrate equipped with a a semiconductor support layer (11) and an insulating layer (12) arranged between the support layer (11) and said surface layer (13), a plurality of blocks (22a,…,22e) of grids, -to form a separation trench (55) through said grid blocks so as to divide each grid block into a pair (221, 222) of front control grids, said separation trench (55) extending to through the active zone (14) so ​​as to divide the active zone (14) into one first semiconductor portion (141) and a second semiconductor portion conducting (142), said trench (55) also extending through the insulating layer (12) of the substrate and having a bottom exposing an area (111) of the support layer (11), -form at the bottom of the trench (55) a conductive electrode (150) back.

8. Method according to claim 7, wherein the conducting electrode rear (150) is formed through the following steps: - metal deposition on said area (111) of the exposed support layer at the bottom of the trench (55), - heat treatment to form an alloy between said metal between the semiconductor material of the zone (111) of the layer (11) of support.

9. A method according to any one of claims 7 or 8, further comprising, after the formation of the grid blocks (22a, ..., 22e) and prior to the fabrication of the rear control electrode (150): - the formation of an etching stop layer (51) on said blocks (22a,...,22e) of grid, the trench (55) being made through said etching stop layer (51) formed on the grid blocks.

10. | Method according to claim 9, further comprising, after formation grids and prior to the formation of the arrest layer of engraving, the steps of which are: - growth of doped semiconductor material (33) on regions (14a, 14b) of the active zone (14) arranged on either side of the blocks of grids (22a,...,22e), so as to form reservoirs of doping agents, - silicification of the upper surface of said reservoirs and blocks (22a,..,22e) of grid.

11. A method according to any one of claims 7 to 9, wherein previously In the metal depot, the process includes the following steps: - formation of dielectric protection zones (57a, 57b) on flanks lateral to the trench (55), the di- protection zones (57a, 57b) electrical being arranged so as to extend between the first portion semiconductor (141) and the second semiconductor portion (142) and to reveal zone (111) of the support layer at the bottom of the trench {55).

12. A method according to claim 11, wherein, after formation of the rear conducting electrode (150), the process includes the rem- folding of the trench (55) by depositing at least one layer di- electrical (61), the dielectric layer (61) and the zones (57a, 57b) of dielectric protection having a specified composition and arrangement in order to allow for the establishment of an electrostatic coupling between the first semiconductor portion (141) and second semiconductor portion driver (142).

13. Method according to claim 12, wherein said trench (55) carried out extends into a given part of the substrate located at the periphery of the active zone (14), and in which after the filing of said at least a dielectric filling layer (61), the process comprising in in addition: the production of contact pads (77, 78, 79, 71a, 72a, 73a, 74a, 'I5a, 71b, 72b, 73b, 74b, 75b) of which at least one contact pad (77) of said rear control electrode (150), by: - formation of at least one hole through the dielectric layer (61), said hole opening into said given part revealing the layer of support, - filling the hole with a conductive material.