REAR GRILLE FOR QUANTUM DEVICE

Abstract

Realization of a spin-qubit quantum device comprising a semiconductor-on-insulator substrate, the substrate having a surface semiconductor layer, the surface semiconductor layer being disposed on an insulating layer, the insulating layer being arranged on a top face of a semiconductor support layer, the device having at least one component formed of one or more quantum islands extending into the surface semiconductor layer (12) and one or more gate electrodes for the electrostatic control of the quantum islands, said front gate electrodes being disposed on the surface semiconductor layer, the component further having a rear electrostatic control gate,said rear control grid being formed of a conductive layer (119) lining the side walls and bottom of an opening (517) passing through said semiconducting support layer from a lower face of said support layer opposite said upper face to said insulating layer (11) of the substrate, said conductive layer (119) being disposed, at the bottom of the opening (517), against and advantageously in contact with said insulating layer of the substrate, said conductive layer (119) being disposed against and in contact with said semiconducting support layer at the level of said side walls of said opening. Figure for the abbreviation: 6,

Description

Title of the invention: BACK GRID FOR QUANTUM DEVICE Technical field

[0001] The present application relates to the field of electronic devices and in particular that of quantum devices formed from semiconductor islands and using, in addition to front gate electrodes located above the islands, at least one rear control electrode arranged below the level in which the islands are located. STATE OF THE PRIOR ART

[0002] Quantum islands (sometimes also called quantum dots or quantum boxes) form the basic elements of a quantum electronic device. Quantum islands are typically formed in a layer of semiconductor material in which potential wells are implemented to confine carriers, electrons or holes, in the three dimensions of space. Quantum information is then encoded via the spin of the carrier. These are called spin Qbits (or qubits).

[0003] According to one approach, electrons are confined by field effect under gate electrodes similar to those of transistor structures and the information is encoded in the spin of these electrons. These so-called "front" gates are arranged above the set of quantum islands.

[0004] The possibility of applying a potential under an insulation layer, or a buried oxide (BOX), or rather a rear gate called "Back gate" makes it possible to adjust the depth of the potential well and thus to better control the potential profile and therefore the manipulation of the electrons and their spins.

[0005] The rear gate is an additional electrode located below the set of quantum islands.

[0006] This type of quantum device generally operates at very low temperatures, which means that if we want to make the rear gate from a semiconductor material, it must be very heavily doped so that the gate can be conductive and functional.

[0007] However, doping a substrate very heavily by ion implantation risks inducing residual dopants or generating crystal defects in a semiconductor layer in which the islands are provided. This is not compatible with correct operation of a quantum device.

[0008] Another method which would include a plate transfer step with an already doped area to produce the rear gate would have the disadvantage of being complex to implement and of inducing significant process variability.

[0009] Another method which would consist of producing the rear grid by structuring the rear face then forming a conductive via poses a problem in terms of mechanical constraints exerted on the structure.

[0010] The problem arises of finding a quantum device provided with at least one component equipped with a rear control electrode as well as a method for producing such a device and which are improved with respect to the drawbacks stated above. Statement of the invention

[0011] It is therefore an object of the present invention to provide a quantum device with spin Qbits comprising a substrate of the semiconductor-on-insulator type, the substrate being provided with a surface semiconductor layer, the surface semiconductor layer being arranged on an insulating layer, the insulating layer being arranged on an upper face of a semiconductor support layer, the device being provided with at least one component formed of one or more quantum islands extending in the surface semiconductor layer and one or more so-called "front" gate electrodes for the electrostatic control of the quantum islands, said front gate electrodes being arranged on the surface semiconductor layer, the component C being further provided with a so-called "rear" electrostatic control gate,said rear control gate being formed of a conductive layer covering side walls and a bottom of an opening passing through said semiconductor support layer from a lower face of said support layer opposite said upper face to said insulating layer of the substrate, said conductive layer being arranged, at the bottom of the opening against and advantageously in contact with said insulating layer of the substrate, said conductive layer being arranged against and in contact with said semiconductor support layer at said side walls of said opening.

[0012] Such a rear grid arrangement allows for close control of the islands while maintaining good mechanical strength and in particular protecting the device from excessive mechanical stress.

[0013] Advantageously, said opening comprises an empty volume, that is to say unfilled or filled with air, and which extends from the conductive layer to a mouth of said opening.

[0014] According to one possible implementation, the conductive layer further extends beyond said opening on said lower face of the support layer.

[0015] The conductive layer may extend over a given region of said lower face of the support layer and may be structured so as to comprise patterns on this given region.

[0016] According to a particular embodiment, said opening may have a flared shape. of said bottom to a mouth of said opening and provided so that said side walls of the opening are inclined relative to a normal to a principal plane of said support layer. In this case, the opening may have a flared shape from said bottom to a mouth of said opening.

[0017] According to one possible implementation, the conductive layer can be formed from a stack comprising a conductive bonding layer, and a metal layer made of a material having superconducting properties.

[0018] According to another aspect, the present invention provides a method of manufacturing a device as defined above.

[0019] The present invention relates in particular to a method for manufacturing a quantum device with spin Qbits as defined above and comprising, in this order, steps consisting of:

[0020] a) providing or producing a structure comprising, said substrate provided with said one or more quantum islands extending in the superficial semiconductor layer and one or more electrostatic control gates in front of the quantum islands arranged on the superficial semiconductor layer,

[0021] b) forming, through the lower face of the support layer, the opening then,

[0022] c) depositing the conductive layer in the opening so as to form the grid of rear electrostatic control.

[0023] Advantageously, the method may further comprise: making one or more cutting holes or trenches in the support layer so as to make a cutting path in the support layer.

[0024] According to one implementation possibility, the one or more cutting holes or trenches can create an outline around the opening.

[0025] Advantageously, the production of the one or more cutting holes or cutting trenches in the support layer and the formation of the opening can be carried out by etching and concomitantly.

[0026] According to one possible implementation, the deposition of the conductive layer can also be carried out in the one or more cutting holes or trench(es).

[0027] The method can then further comprise steps of:

[0028] - formation of a masking covering said opening,

[0029] - removal by etching of the conductive layer opposite the hole(s) or trench(es) cutting while protecting the opening through masking.

[0030] Advantageously, the method may further comprise, after step c), the steps of:

[0031] - bonding an adhesive strip against the underside or a layer or an em pile arranged on the underside of the support layer,

[0032] - stretching the adhesive strip so as to create a division of the substrate at the level of the cutting path(s).

[0033] According to one possible implementation, the opening can be made by deep etching through a mask.

[0034] Typically, a preliminary reversal of the substrate is carried out before carrying out such etching.

[0035] According to one possible embodiment for which the front electrostatic control grids are coated with a stack of layers and for which between step a) and step b) a temporary handle support is glued to said stack, the method may further comprise after step c): a step of removing the temporary support. Brief description of the drawings

[0036] The present invention will be better understood on the basis of the following description and the attached drawings in which:

[0037] The present invention will be better understood on reading the description of exemplary embodiments given, for purely indicative and non-limiting purposes, with reference to the appended drawings in which:

[0038] [Fig. 1] serves to illustrate an example of a quantum component on which a back gate is intended to be formed and which is capable of being integrated into a quantum device as implemented according to the present invention;

[0039] [Fig.2A]

[0040] [Fig.2B]

[0041] [Fig.2C]

[0042] [Fig.2D]

[0043] [Fig.2E]

[0044] [Fig.2F]

[0045] [Fig.2G]

[0046] [Fig.2H]

[0047] [Fig.2I]

[0048] [Fig.2J] are used to illustrate an exemplary method, according to an embodiment of the present invention, of manufacturing a quantum device and a back gate for a quantum component;

[0049] [Fig.3A]

[0050] [Fig.3B] are used to illustrate a division of a substrate in order to obtain several elementary chips by stretching an adhesive strip stuck on a substrate in which one or more cutting paths have been previously formed;

[0051] [Fig.4A]

[0052] [Fig.4B]

[0053] [Fig.4C] are used to illustrate the implementation of holes or trenches around grids back in order to create a continuous or discontinuous cutting path;

[0054] [Fig.5] serves to illustrate the implementation of a flared receiving opening for a quantum device rear gate;

[0055] [Fig.6] serves to illustrate a quantum device having a back gate formed in a flared receiving opening in the semiconductor support layer of a semiconductor-on-insulator support;

[0056] [Fig.7] is used to illustrate patterns made in a conductive layer on the back face of a quantum device and connected to one or more back gates;

[0057] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0058] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0059] Furthermore, in the following description, terms that depend on the orientation of the structure such as "front", "rear", "upper", "lower", "side", apply considering that the structure is oriented as illustrated in Figures 1, 2A, or 6.

[0060] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0061] We first refer to [Fig.l] which gives a sectional view of an example of a quantum component C, in particular with spin Qbits, during manufacture, and which is capable of being integrated into a quantum circuit chip implemented according to the invention.

[0062] The component is formed on a substrate which may be of the semiconductor-on-insulator type and which comprises a support layer 10 made of semiconductor material, a buried insulating layer 11 arranged on the support layer 10 and a semiconductor surface layer 12 arranged on the insulating layer. The substrate is typically an SOI (“Silicon On Insulator” substrate, i.e. Silicon on insulator) whose surface layer 12 is made of silicon, in particular 28Si when this layer is to accommodate electron spin qubits. Other semiconductor materials may be envisaged for the surface semiconductor layer 12, in particular, when this layer is to accommodate hole spin qubits.

[0063] The insulating layer 11 and the support layer 10 are typically, respectively, a silicon oxide layer commonly called “BOX” (for “Burried Oxide” or “buried oxide”) and a silicon-based layer. The thickness of the surface layer 12 is, for example, between approximately 5 nm and 50 nm, typically of the order of 10 nm. The thickness of the buried insulating layer 11 is, for example, between 10 nm and 200 nm, for example of the order of 145 nm.

[0064] The support layer 10 can be provided for example with a thickness eocomprised between 30 pm and 725 pm, typically 725 pm or 775 pm.

[0065] In the embodiment described here, the component C comprises at least two confinement regions 12A, 12B located in a portion of the superficial semiconductor layer 12, these regions 12A, 12B being coupled and juxtaposed, a first of these regions forming a Qbit, while the other region forms a detection element. Each qubit and detection element is provided with a front gate, referenced 20a and 20b, each of the gates resting on a gate dielectric 19a, 19b. The two confinement regions 12A, 12B are here connected via a coupling region 12C between the confinement regions 12A, 12B.

[0066] The quantum coupling between the confinement regions 12A, 12B or more particularly the potential level of the tunnel barrier formed by the region 12C can be modulated by the addition of a rear gate intended to be formed subsequently in the support layer 10.

[0067] To enable precise positioning of the component C relative to a back gate location, alignment marks (not shown) may be provided on the underside 10B of the support layer 10. Such marks may be detected by an optical system using an infrared beam passing through the support layer 10.

[0068] After having typically produced a plurality of quantum components of the type described above, contacts and connection elements of one or more interconnection levels are formed by carrying out one or more step(s) of depositing insulating layer(s), for example SiO2, of producing opening(s) in this or these layer(s), of depositing metallic material(s).

[0069] In the particular embodiment illustrated in [Fig.2A], the component C is thus covered with a stack of insulating layers comprising a layer 32 of dielectric material called “pre-metallic” (PMD), for example an oxide layer which may be of the order of 400 nm thick. This layer or this stack is planarized by CMP (“Chemical Mechanical Polishing”, i.e. chemical-mechanical polishing) and holes are made to form connection elements 34 made of metallic material.

[0070] The layer 32 of dielectric material called “pre-metallic” (PMD) is here covered with other insulating layers 42, 52, in which a first metallic level M1 and a second metallic level M2 of interconnection are in this example formed with vertical connection elements V1 (commonly called “vias”) between the levels M1, M2. The metallic levels are here surmounted by conductive access pads 64, for example made of aluminum flush with the stack of insulating layers.

[0071] It is then desired to form in the support layer 10 one or more rear gate electrodes and in particular at least one rear gate electrode for the component C described previously.

[0072] In the embodiment illustrated in [Fig.2B], prior to structuring the support layer 10, a temporary support 202 is attached to the stack of insulating layers. The temporary support 202 is thus arranged on the side of the upper face of the substrate and makes it possible to provide protection and mechanical strength for the assembly during subsequent structuring(s) of the support layer 10.

[0073] The temporary support 202 may for example be made of semiconductor material, in particular silicon, and may have a thickness of between 400 μm and 800 μm, for example of the order of 725 μm. The temporary support 202 may be assembled with the substrate by means of an adhesive 201, which is previously spread on the stack in which the connection elements 64, M1, M2, VI, 34 are formed. A step of cleaning the lateral edges of the substrate is typically carried out after the temporary bonding of the support 202.

[0074] The glue 201 used may be a glue made liquid at high temperature, in particular above 200°C. For example, a liquid glue of type BSIO1A developed by Brewer Science, Inc. (BSI) is chosen.

[0075] In [Fig.2C] (the substrate being turned over in this figure), an optional step of reducing the thickness of the support layer 10, now noted e'o and such that e'0< e0 is carried out in order to facilitate subsequent structuring of the latter.

[0076] This reduction in thickness can be achieved in successive thinning sub-steps.

[0077] A first thinning of a thickness for example of the order of 200 μm can be carried out. This first thinning can be followed by a second thinning of a thickness for example of the order of 120 μm.

[0078] Between the thinnings, steps of trimming and measurement of residual thickness can be provided.

[0079] Each thinning may comprise a deep reactive ion etching (DRIE) process. For a silicon support 10, this process is carried out, for example, by alternating a silicon etching phase using a fluorine-based plasma (Sulfur Hexafluoride SF6) and a phase based on fluorocarbon chemistry.

[0080] For example, a thickness of the support layer 10 of between 30 and 200 μm, advantageously between 120 μm and 180 μm, is maintained.

[0081] One or more openings are then made in the support layer 10, in particular in order to form one or more rear grid locations.

[0082] In the embodiment illustrated in [Fig.2D], a mask 108 is first produced for this purpose, for example in photosensitive resin, on the layer of support 10 and the patterns of the mask are reproduced in the support layer 10. The reproduction of the patterns can be carried out by deep reactive ion etching (DRIE), for example by a process commonly called "Bosch". An etching process similar to that for forming connection elements through silicon commonly called TSV (for "Through Silicon Vias") can be implemented. The mask 108 is then removed.

[0083] According to one possible implementation, it is advantageous to provide for the production, at the same time as the rear grid receiving opening(s): of one or more cutting trenches in the support layer 10.

[0084] Thus, in the embodiment illustrated in [Fig.2E], in addition to an opening 117 for receiving a rear gate for the component C, a trench 111 forming a cutting path is produced. The trench 111 and the rear gate opening 117 have here been produced simultaneously by etching the support layer 10 of the substrate through the same mask.

[0085] The opening 117 for receiving the rear grid here has a bottom 117a located at the level of the insulating layer 11 of the substrate and in this particular example the bottom 117a is formed by this insulating layer 11. The opening 117 is provided with side walls 117b formed by the semi-conducting support layer 10 of the substrate. An opening 117 of diameter D (dimension measured parallel to the plane [O; x; y] of the orthogonal reference [O; x; y; z] given in [Fig. 2E]) can be provided at its mouth which can be between 500 and 10 μm, for example 20 μm. The opening 117 is made with a depth H (dimension measured parallel to the z axis of the orthogonal reference frame [O; x; y; z] given in [Fig.2E]) from the bottom 117a to its mouth 117e which can be of the order of the thickness of the support layer 10, for example of the order of 120 μm.

[0086] At least one conductive material is then deposited in the opening 117 for receiving the gate ([Fig.2F]). In the illustrated embodiment, this is done by a process of conformal deposition of at least one conductive layer 119. A layer or stack of material having superconducting properties is preferably chosen, in particular at a temperature T below 2K.

[0087] The conductive layer 119 may be formed from a stack comprising a bonding layer, for example made of Ti, and a metal layer, for example made of Cu or a material having superconducting properties and preferably capable of being easily deposited in a conformal manner, for example a material chosen from one of the following materials: TiN, Ru, Nb. This stack covers the bottom 117a and the side walls 117b of the opening 117. It is possible to provide a bonding layer with a thickness between 5 nm and 500 nm, for example of the order of 50 nm, and a metal layer in material having superconducting properties with a thickness between 5 nm and 500 nm, for example of the order of 50 nm, the thickness of these layers being provided according to the dimensions of the opening 117 and preferably so as to line the latter without filling it.

[0088] In this embodiment, the conductive layer 119 is thus in contact with a semiconductor material at the side walls 117b and with an insulating material at the bottom 117a, and in particular the insulating material of the insulating layer 11 of the substrate. The conductive layer 119 can be produced by physical vapor deposition (PVD) or advantageously by CVD (Chemical vapor deposition). A particular method provides for producing a bonding layer by iPVD (ionized PVD) and the superconductor layer by CVD.

[0089] Metallization is thus carried out without the need to provide electrical insulation at the side walls 117b since the semiconductor material of the support layer 10, typically silicon, is insulating at the operating temperature of the quantum device. This quantum device can operate at low temperatures, in particular at temperatures below several Kelvin, advantageously below 2 K and for example equal to 1 K.

[0090] An optional step of removing the conductive layer 119 at the cutting trench 111 can then be carried out. In the particular embodiment illustrated in [Fig.2G], a masking 121 is arranged on the side of the lower face 10B of the support layer 10 and above the opening 117, without coating the side walls 117b or the bottom 117a of the latter. According to a particular embodiment, the masking 121 can be a dry layer of photosensitive resin produced by lamination, such as for example an MX5015™ resin developed by the company Dupont™.

[0091] Portions 119p of the conductive layer 119 which are not covered by the masking 121 and which are thus revealed are then etched. In particular, these portions 119p are removed at the level of the trench(es) 111 formed in the support layer 10 ([Fig.2H]). The removal of portions 119p of the conductive layer 119 outside areas where it is desired to form the rear gate(s) and any contact points for this or these gates, makes it possible to release the stresses exerted by the layer 119 on the structure.

[0092] This step may also be an opportunity to produce patterns 122 in the conductive layer 119 at the lower face 10B of the support layer 10. This may make it possible to define contact pads on the rear face as well as distinct polarization zones of the rear gate. This may also make it possible to release the stress exerted by the conductive layer 119 on the rest of the structure. compared to a continuous plane production, this can also make it possible to reduce parasitic capacitances. A particular embodiment example is illustrated in [Fig.7], the patterns 122 being here in the form of crossings of metal strips at the level of which the rear grids 120 are arranged.

[0093] The masking 121 can then be removed.

[0094] Then, the substrate is divided into several parts in order to separate integrated circuits formed on this substrate from each other. The division is carried out by following the cutting path(s) carried out previously. Such a division can be carried out by a cutting process implementing steps of scoring and breaking, mechanical sawing, or laser cutting.

[0095] Prior to this division, the temporary support 202 and the glue 201 used to assemble this support 202 with the stack of layers formed on the substrate can be removed, and a flexible adhesive strip 133 is formed or glued on the side of the lower face 10B of the support layer 10 ([Fig.2I]). The adhesive strip 133 is advantageously a stretchable strip having a thickness and a composition intended to allow it to be stretchable. For example, the adhesive strip can be based on a polyolefin, acrylic, PET (poly(ethylene terephthalate)), or according to a particular embodiment, be an adhesive strip of the brand "Furukawa Electric" commercially available under the reference SP-537T.

[0096] When the substrate is cut, for example by a sawing or cutting process, the strip 133 makes it possible to hold the assembly together temporarily. Alternatively or in combination, the division can be carried out by stretching the adhesive strip 133. Thus, in the exemplary embodiment illustrated in FIGS. 3A-3B, the adhesive strip 133 is stretched to allow parts of the substrate corresponding to different elementary chips p to be separated; and the division is carried out without further cutting. The prior creation of cutting trenches 111 in combination with an expansion of the adhesive strip 133 may be sufficient.

[0097] Once the division is carried out, the complete separation ([Fig.2J]) of the elementary circuit chips pi from each other can then be carried out, by removing the strip 133 from the surface of the latter.

[0098] In the embodiment described above, at least one cutting trench 111 is advantageously formed concomitantly with the opening 117 for receiving the rear grille. Alternatively, two separate steps may be provided for producing the opening and the cutting path.

[0099] According to one possible arrangement and in order to facilitate cutting, the trench 111 can be formed so as to produce a closed contour, for example rectangular or square in shape. Thus, in the exemplary embodiment illustrated in [Fig.4A] giving a schematic bottom view, the separation trench 111 between a chip integrated circuit and other adjacent circuit chips achieves a closed contour around back gates 120.

[0100] To produce the cutting path(s), instead of a continuous trench producing a closed contour, it is possible to engrave a succession of distinct trenches 151 around the rear grid(s) 120. In the embodiment illustrated in [Fig.4B], the trenches 151 formed are separate from one another and produce a discontinuous contour around a set of rear grids 120.

[0101] The cutting path is not necessarily limited to a topography of trench(es). This path may be made in the form of a plurality of holes 161. In the particular embodiment illustrated in [Fig.4C], the holes 161 are arranged against each other so as to produce a contour which may be continuous around the grids 120.

[0102] As a variant of one or other of the method examples described previously, and in particular of a step such as presented in connection with [Fig.2E], it is possible to provide, as in [Fig.5], to produce an opening 517 for receiving the rear grille having a flared shape.

[0103] The dimensions of such an opening 517 thus increase from the bottom 17a located at the level of the insulating layer 11 of the substrate to its mouth 517e of the opening 517 and which can be located at the level of the lower face 10B of the support layer 10. The opening is in the example illustrated provided with side walls 517b inclined relative to a normal n to a main plane of said support layer 10 (i.e. a plane passing through the support layer and parallel to the plane [O; x; y; z] given in [Fig. 5].

[0104] Such an opening shape can make it easier to produce the rear gate electrode in that it makes the conformal deposition of the conductive layer 119 easier. To form such an opening 517, etching of the support layer 10 using a “tapered via” type method can be carried out. In particular, for example, DRIE-ICP (“Deep Reactive Ion Etching” - “Inductively coupled plasma”) type etching is used, i.e. deep reactive ion etching using an inductively coupled plasma. Such a shape also makes it easier to produce the opening by etching and can also avoid a possible prior step of thinning the support layer 10 of the substrate or reducing the thickness of the substrate 10 to be removed.

[0105] A rear grid arrangement 520 formed in such a receiving opening 517 is illustrated in [Fig. 6]. The rear grid 520 is formed of the conductive layer 119 lining the bottom as well as the inclined side walls 517b without however filling the opening 517. Such a shape of opening 517 also makes it possible to limit the mechanical stress at the level of the insulating layer 11 of the support 10 and to obtain thus better retention of the conductive layer 119 at the bottom of the opening.

[0106] A quantum island or quantum box device as described above may be integrated, for example, into a logic circuit suitable for implementing quantum information processing or a spintronics circuit, or even into a circuit used in a quantum computer. Such a circuit may also be associated with or comprise one or more transistors, in particular transistors produced using CMOS technology, more particularly transistors produced on thin film.

Claims

Claims

1. A quantum device with spin Qbits comprising a substrate (10) of the semiconductor-on-insulator type, the substrate being provided with a surface semiconductor layer (12), the surface semiconductor layer being arranged on an insulating layer (11), the insulating layer being arranged on an upper face (10A) of a semiconductor support layer (10), the device being provided with at least one component (C) formed of one or more quantum islands (12A) extending in the surface semiconductor layer (12) and one or more gates (20A, 20B) called "front" for the electrostatic control of the quantum islands, said front gate(s) (20A, 20B) being arranged on the surface semiconductor layer (12), the component (C) being further provided with an electrostatic control gate (120) called "rear",said rear control gate being formed of a conductive layer (119) covering side walls (117b) and a bottom (117a) of an opening (117, 517), said opening passing through said semiconductor support layer (10) from a lower face (10B) of said support layer opposite said upper face (10A) to said insulating layer (11) of the substrate, said conductive layer (119, 519) being arranged, at the bottom of the opening (117, 517), against and advantageously in contact with said insulating layer of the substrate, said conductive layer (119, 519) being arranged against and in contact with said semiconductor support layer (10) at said side walls of said opening, said opening (517) having side walls (517b) inclined relative to a normal (n) to a principal plane of said layer (10) of support.,

2. A spin Qbit quantum device according to claim 1, wherein said opening (117) comprises a void volume extending from the conductive layer (119) to a mouth of said opening (117).

3. A spin Qbit quantum device according to one of claims 1 or 2, wherein the conductive layer (119) further extends beyond said opening (117) on said lower face (10B) of the support layer.

4. Spin Qbit quantum device according to one of claims 1 to 3, wherein the conductive layer (119) extends over a given region (1 OBI) of said lower face (10B) of the support layer (10) and is structured so as to comprise patterns (122) on this given region.

5. Quantum device with spin Qbits according to one of claims 1 to 4, in which the conductive layer (119) is formed from a stack comprising a conductive attachment layer, and a metallic layer made of a material having superconducting properties.

6. A method of manufacturing a quantum device with spin Qbits according to one of claims 1 to 5, comprising, in this order, the following steps: a) providing or producing a structure comprising, said substrate provided with said one or more quantum islands (12A, 12B) extending into the superficial semiconductor layer (12) and said one or more electrostatic control gates (20A, 20B) in front of the quantum islands arranged on the superficial semiconductor layer, b) forming, through the lower face of said support layer (10), said opening (117), said opening (517) having side walls (517b) inclined with respect to a normal (n) to a principal plane of said support layer (10) and producing one or more cutting holes (161) or trenches (111, 151), in the support layer (10) so as to produce a path of cutting into said support layer,the production of said one or more cutting holes (161) or cutting trenches (111, 151) in the support layer (10) and the formation of said opening (117) being carried out by etching and concomitantly, then, c) depositing said conductive layer in said opening so as to form the rear electrostatic control grid.,

7. A method according to claim 6, wherein said one or more cutting holes (161) or trench(es) (111, 151) provide a contour around said opening.

8. Method according to one of claims 6 or 7, in which the deposition of said conductive layer (119) is also carried out in said one or more cutting holes (161) or trench(es) (111, 151), the method further comprising steps of: - forming a masking (121) covering said opening (117), - removing by etching said conductive layer (119) opposite the cutting hole(s) or trench(es) while protecting said opening (117) by means of said masking (121).

9. Method according to one of claims 6 to 8, further comprising, after step c) of the steps of: - gluing an adhesive strip (133) against the lower face or a layer or stack arranged on the lower face of the support layer, - stretching the adhesive strip (133) so as to divide the substrate at the cutting path(s).

10. Method according to one of claims 6 to 9, in which the opening (117) is produced by deep etching through a mask (108).

11. Method according to one of claims 6 to 10, in which said one or more front electrostatic control grids are coated with a stack of layers and in which between step a) and step b) a temporary handle support is glued to said stack, the method further comprising after step c) a step of removing said temporary support.

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