Manufacturing process for an integrated circuit and corresponding integrated circuit

Abstract

The manufacturing process of an integrated circuit includes the fabrication of a transistor (GP) comprising: - steps (300, 400) of forming a first gate region (GPG); - steps (500, 800, 900, 1100) of depositing dielectric layers (ONO, HVSP, NVSP, LVSP) accumulating on the flanks of the first gate region (GPG) so as to form spacer regions having a width (w2); - an etching step (510) removing part of the dielectric layers (ONO) accumulated on the flanks of the gate region so as to reduce the width (w1) of the spacer regions; - a first dopant implantation step (1100) aligned with the spacer regions, forming first lightly doped conduction regions (LDD0 / 1) of the transistor (GP); - a second dopant implantation step (1200) forming the first conduction regions (SD) of the transistor (GP) with higher doping levels. Figure for the abbreviation: Fig 12

Description

Title of the invention: Method for manufacturing an integrated circuit and corresponding integrated circuit

[0001] Implementation methods and embodiments relate to integrated circuits, in particular the manufacture of a transistor adapted for a first voltage range in cointegration with manufacturing steps of at least one other transistor adapted for another voltage range.

[0002] Cointegration makes it possible to reuse manufacturing steps planned for elements typically present in a type of integrated circuit, in order to manufacture a particular element without additional steps or additional cost.

[0003] For example, in an integrated circuit comprising non-volatile memory, floating gate transistors are typically intended for storing data in memory, transistors adapted for a so-called high voltage range are typically intended for memory write operations, and transistors adapted for a so-called low voltage range are typically intended for scheduling the operation of the memory, in a logic circuit of the state machine type.

[0004] Typically, in an inexpensive circuit of this type incorporating non-volatile memory, no specific transistor architecture suitable for a first voltage range, referred to as the medium voltage range, is offered, for cost reasons, and only low-voltage or high-voltage transistor architectures exist. The medium voltage range, for example, is higher than the low-voltage range and lower than the high-voltage range, and is intended for general-purpose signal communication such as input / output signals of the integrated circuit.

[0005] Conventionally, to manufacture a transistor suitable for the medium voltage range at a lower cost and without introducing additional steps, a high-voltage transistor is reproduced, as it is capable of withstanding medium voltages and operating within the medium voltage range. Typically, the operation of high-voltage transistors is not optimized for the medium voltage range, and furthermore, the size of high-voltage transistors is excessive for the medium voltage range and cannot be reduced. Indeed, to withstand high voltages, high-voltage transistors typically have extended conduction regions under their gates, and the minimum gate length of high-voltage transistors cannot be reduced without introducing short-channel parasitic effects.

[0006] Thus, there is a need to provide transistor manufacturing techniques adapted for a particular voltage range, optimized in their function- functional, compact and at a lower cost.

[0007] According to one aspect, a method for manufacturing an integrated circuit is proposed in this regard, including the manufacture of a first transistor for a first voltage range, comprising: - steps for forming a first grid region on a front face of a semiconductor substrate and having flanks perpendicular to the front face; - stages of deposition of dielectric layers accumulating on the flanks of the first grid region so as to form spacer regions having a width in a direction perpendicular to the flanks of the first grid region; - an etching step removing part of the dielectric layers accumulated on the sides of the first grid region in order to reduce the width of the spacer regions; - a first dopant implantation step aligned with the spacer regions, forming the first lightly doped conduction regions of the first transistor; - a second stage of implanting dopants forming the first conduction regions of the first transistor, more heavily doped than the lightly doped conduction regions.

[0008] Indeed, typically in the manufacture of an integrated circuit comprising several transistors for several respective voltage ranges, the steps of depositing dielectric layers in order to form spacer regions accumulate on the sides of all the gate regions which are already formed on the front face.

[0009] In the method according to this aspect, it is proposed to specifically remove a portion of the dielectric layers accumulated on the sides of the first gate region, so as to reduce the width of the spacer regions. By reducing the width of the spacer regions of the first transistor, the implantation zones of the first lightly doped conduction regions are brought closer to the channel region of the first transistor. The channel region of the transistor is considered to be located in the semiconductor substrate, opposite the first gate region.And, by bringing the aforementioned first lightly doped conduction regions closer to the channel region, on the one hand, we reduce the impact ionization phenomena generating "hot carriers" that degrade the transistor; and on the other hand, we parameterize the threshold voltage of the transistor in conjunction with the conditions of the first dopant implantation stage, for optimized performance in the first voltage range.

[0010] Furthermore, the term "lightly doped conduction regions," commonly used in its English form "Lightly Doped Drain / Source," is well known to those skilled in the art and designates a region typically implanted less deeply than the conduction region, with a typically lower dopant concentration. The source and drain regions of the transistor include the regions weakly doped conduction regions and more strongly doped conduction regions.

[0011] For example, the first weakly doped regions according to this aspect may have a concentration of doping species between 1016 cm3 (ten to the power of sixteen atoms per cubic centimeter) and 1018 cm3 (ten to the power of eighteen), and a depth between 100 nm (nanometers) and 500 nm, while the first more strongly doped conduction regions may have a concentration of doping species between 1018 cm3 (ten to the power of eighteen) and 1020 cm3 (ten to the power of twenty), and a depth between 100 nm and 500 nm.

[0012] According to one implementation method: - said dielectric layer deposition steps include a dielectric layer(s) deposition step prior to said etching step and at least one other dielectric layer(s) deposition step subsequent to said etching step; - said etching step is adapted to remove the dielectric layer(s) deposited during the previous step.

[0013] Alternatively, the etching step could also be carried out after the deposition of all the dielectric layers, so as to reduce the width of the spacer regions from the outside. That being said, the implementation method defined above has the advantage of having better alignment tolerance than its alternative, and even of not being constrained at all with regard to alignment.

[0014] According to one embodiment, the dielectric layer deposition step prior to the etching step comprises a deposition of a superposition of conformal layers of silicon oxide, silicon nitride, and silicon oxide.

[0015] According to one embodiment, the process includes manufacturing a second transistor for a second voltage range comprising: - steps for forming a second grid region on the front face of the semiconductor substrate and having flanks perpendicular to the front face; - the same steps of depositing dielectric layers to form spacer regions on the flanks of the second gate region; and - a masking step adapted to prevent said removal, during the etching step, of part of the accumulations of dielectric layers deposited on the sides of the second grid region.

[0016] Thus, the accumulations of dielectric layers in the spacer regions of the first transistor and the second transistor have the same constitutions and the same thicknesses, and the second transistor further comprises at least one dielectric layer (the said part whose removal is prevented by the masking step) in said accumulation which is not in the spacer regions of the first transistor.

[0017] According to one embodiment, the process includes the manufacture of a third floating-gate transistor comprising: - the same steps for forming the first gate region to form the floating gate of the third floating-gate transistor, including: — the formation of a tunnel dielectric layer on the front face; — the formation of an electrically conductive layer on the tunnel dielectric layer.

[0018] This makes it possible in particular to benefit from a first gate region having a dielectric layer and a conductive layer well adapted for the first voltage range, while being free due to the cointegration with the manufacture of the third transistor.

[0019] According to one embodiment, the process includes manufacturing a fourth transistor for a fourth voltage range comprising: - the same first step of dopant implantation, forming fourth, weakly doped conduction regions of the fourth transistor.

[0020] This allows in particular to benefit from first low-doped conduction regions, having the same constitution and the same depth as the fourth low-doped conduction regions, well suited for the first voltage range, while being free due to the cointegration with the manufacture of the fourth transistor.

[0021] According to one embodiment, the process includes manufacturing a fourth transistor for a fourth voltage range comprising: - the same etching step removing some of the dielectric layers accumulated on the front face of the semiconductor substrate.

[0022] Here again, since the manufacture of the fourth transistors involves an etching step to remove deposited dielectric layers, the cointegrated implementation of the etching step reducing the width of the spacer regions of the first transistor is free.

[0023] According to another aspect, an integrated circuit is proposed comprising a first transistor adapted for a first voltage range, and a second transistor adapted for a second voltage range, - the first transistor comprising a first gate region and the second transistor comprising a second gate region, the gate regions being located on a front face of a semiconductor substrate and having flanks perpendicular to the front face, and each comprising a conductive layer having the same constitution and thickness, typically taken in a direction perpendicular to the front face, - the first transistor and the second transistor comprising an accumulation of dielectric layers having the same composition and thickness on the flanks of their gate regions so as to form spacer regions having, respectively, a first width and a second width in a direction perpendicular to the sides of the grid regions, - the first transistor comprising, in the semiconductor substrate, first lightly doped conduction regions aligned with the spacer regions, and first more heavily doped conduction regions, wherein the second transistor further comprises at least one additional dielectric layer in said accumulation so as to form spacer regions having a second width greater than the first width of the spacer regions of the first transistor.

[0024] According to one embodiment, the integrated circuit further comprises a third floating gate transistor having a floating gate region comprising a tunnel dielectric layer on the front face and, on the tunnel dielectric layer, a conductive layer having the same constitution and the same thickness as the conductive layer of the first gate region and the second gate region, in which the first gate region has a dielectric layer on the front face having the same constitution and the same thickness as the tunnel dielectric layer.

[0025] According to one embodiment, the integrated circuit further comprises a fourth transistor adapted for a fourth voltage range comprising, in the semiconductor substrate, fourth lightly doped conduction regions having the same constitution and the same depth as the first lightly doped conduction regions.

[0026] Other advantages and features of the invention will become apparent upon examination of the detailed description of implementations and embodiments, which are by no means limiting, and the accompanying drawings, in which:

[0027] [Fig.l] ;

[0028] [Fig.2] ;

[0029] [Fig.3] ;

[0030] [Fig.4] ;

[0031] [Fig.5] ;

[0032] [Fig.6] ;

[0033] [Fig.7] ;

[0034] [Fig.8] ;

[0035] [Fig.9] ;

[0036] [Fig. 10];

[0037] [Fig. 11];

[0038] [Fig. 12];

[0039] [Fig. 13];

[0040] [Fig. 14] illustrate methods of implementation and realization of the invention.

[0041] Figures 1 to 12 illustrate results of steps of an example of a manufacturing process for an integrated circuit comprising a first GP transistor adapted to a first voltage range, a second HV transistor adapted to a second voltage range, a third NVM floating gate transistor typically adapted for a non-volatile memory cell, a fourth SRAM transistor, GO1 adapted to a fourth voltage range.

[0042] By "a transistor" we mean "at least one transistor".

[0043] The first GP transistor is manufactured in a completely cointegrated manner, with the manufacturing steps of the second HV transistor, the third NVM transistor and the fourth SRAM transistor, GO1, i.e. without any manufacturing step dedicated to the first GP transistor.

[0044] For example, the first voltage range, called "medium voltage", includes voltages below 5.7 V (volts), so the first GP transistor will be called "medium voltage transistor"; the second voltage range, called "high voltage", includes voltages below 10 V, so the second HV transistor will be called "high voltage transistor"; the fourth voltage range, called "low voltage", includes voltages below 1.4 V, so the fourth SRAM transistor, GO1, will be called "low voltage transistor".

[0045] The fourth SRAM transistor, GO1, is illustrated in two possible cases: one corresponding to an SRAM transistor manufactured for static random access memory, and the other to a GO1 transistor manufactured for a logic circuit such as a state machine or a processor. In some technologies, the SRAM transistors for static random access memory and the logic GO1 transistors are identical; in other technologies, the SRAM transistors for static random access memory and the logic GO1 transistors exhibit slight differences, particularly with regard to the lightly doped conduction region LDD0, LDD1 (see below in relation to Figures 10 and 11). In both cases, for the purposes of cointegrating the first transistor GP, the fourth transistor will be considered to be one of the SRAM transistors, GO1.

[0046] Finally, although the manufacturing of the GP medium voltage transistor is described in a framework fully cointegrated with the manufacturing steps of the second HV, third NVM and fourth SRAM transistors, GO1, implementation modes partially cointegrated with, for example, only one or two of the second HV, third NVM and fourth SRAM transistors, GO1 are included in the present description by considering the corresponding steps as being implemented in a dedicated manner for the manufacturing of the GP medium voltage transistor.

[0047] Figure 1 illustrates the result of step 100 in which lateral STI isolation regions, for example shallow isolation trenches, were formed in a PSUB semiconductor substrate, in order to define active regions within the PSUB substrate, in a conventional and well-known manner. The PSUB substrate is typically made of P-type doped crystalline silicon. Alternatively, the PSUB substrate can be N-type doped, in which case those skilled in the art will know how to adapt the doping type of the cells and the respective conduction regions in the fabrication process described below. The face of the PSUB substrate on which the fabrication steps are performed is called the front face (FA).

[0048] Figure 2 illustrates the result of step 200 of forming so-called high-voltage (HVW) cells by implanting dopants in the active region housing the high-voltage (HV) transistor and in the active region housing the medium-voltage (GP) transistor. Step 200 further includes the formation of a non-volatile memory (NVW) cell specific to the non-volatile memory in the active region housing the floating-gate (NVM) transistor. The NVW non-volatile memory cell notably includes a buried isolation cell and contact wells (not shown) to form a "triple cell" type isolation structure (well known to those skilled in the art) and a surface counter-implant region at the front face (FA) to adjust the threshold voltage of the floating-gate (NVM) transistor.

[0049] Figure 3 illustrates the result of steps 300, comprising the fabrication of a vertical-gate buried access transistor TR in the active region hosting the floating-gate transistor NVM, including a buried source region BS joining the buried isolation box (not shown). Steps 300 further comprise the formation of a thick HVOX oxide layer on the front face FA in the active regions hosting the high-voltage transistor HV, the floating-gate transistor NVM, and the medium-voltage transistor GP; followed by partial etching of the thick HVOX oxide layer in the active regions hosting the floating-gate transistor NVM and the medium-voltage transistor GP, so as to reduce its thickness to a so-called tunnel thickness TNOX.The TNOX tunnel thickness is particularly suited to injections of electrical charges through it by the Fowler-Nordheim effect, also known as the "tunnel effect", intended for writing data into non-volatile memory.

[0050] Figure 4 illustrates the result of 400 steps comprising the deposition of a conductive PI layer, typically comprising polycrystalline silicon, over the entire front face FA of the PSUB semiconductor substrate. Etching is then carried out, typically by photolithography, of the conductive PI layer and the HVOX and TNOX oxide layers in order to define the HVG gate region of the high-voltage transistor and the GPG gate region of the medium-voltage transistor. The definition of the HVG and GPG gate regions includes delineating the edges of the gate regions in a vertical plane, i.e., perpendicular to the front face FA.

[0051] The etching process also allows the PI conductive layer to be removed from the active regions hosting the low-voltage SRAM transistors, GO1. The etching process is further configured to leave the active region hosting the floating-gate NVM transistor entirely covered by the tunnel oxide layer TNOX and the conductive layer PL.

[0052] In addition, steps 400 include the formation of so-called low-voltage LVW boxes, by dopant implantation, in the active regions hosting the low-voltage SRAM transistor, GOL. For example, the LVW boxes of the low-voltage SRAM transistors, GO1 are formed by the same dopant implantation step.

[0053] Figure 5 illustrates the result of initial deposition stages of ONO dielectric layers accumulating on the flanks of the GPG gate region of the GP medium-voltage transistor and on the flanks of the HVG gate region of the HV high-voltage transistor. The dielectric layers thus accumulated are intended to form spacer regions having a second width w2 (for the HV high-voltage transistor, see Figure 12) in a direction perpendicular to the flanks of the GPG and HVG gate regions.

[0054] These initial deposition steps 500 involve depositing a superposition of ONO layers of conformal silicon dioxide (O), silicon nitride (N), and silicon dioxide (O) over the entire structure obtained from the preceding steps 400. The layers are conformal in that they adhere to the horizontal surfaces (e.g., the front face FA) and the vertical surfaces (e.g., the sides of the gates GPG, HVG) with a constant (isotropic) thickness. An etching step 510 is adapted to remove the superposition of ONO dielectric layers deposited on the front face FA in the regions hosting the low-voltage transistors SRAM, GO1, and in the region hosting the medium-voltage transistor GP. Thus, the etching step 510 removes some of the ONO dielectric layers accumulated on the sides of the first gate region so as to reduce the width wl of the spacer regions (for the medium-voltage transistor GP, see [Fig. 12]).

[0055] The ONO dielectric layer superposition is not removed in the regions hosting the high voltage HV transistor and the floating gate NVM transistor, for example by means of a masking step 505 covering and protecting from etching the high voltage HV region, and the NVM memory region.

[0056] Figure 6 illustrates the result of 600 steps comprising, on the one hand, the formation of a GO1OX gate oxide layer on the front face of the FA in the active regions of the low-voltage SRAM and GOL transistors.

[0057] On the other hand, steps 600 include depositing a second conductive layer P2 over the entire structure obtained at the end of the preceding steps 500, GO1OX, and a directional etching adapted to remove the second conductive layer P2 in the region of the high-voltage transistor HV, and in the region of the GP medium voltage transistor.

[0058] The directional etching is further adapted to remove, in the region of the high voltage transistor HV, the superposition of dielectric layers ONO deposited on horizontal surfaces (parallel to the front face FA) and to not remove, or to remove only a minority of, the superposition of dielectric layers ONO deposited on vertical surfaces (perpendicular to the front face FA).

[0059] Figure 7 illustrates the result of step 700 in which lightly doped LDDHV conduction regions are implanted in the HVW housing of the high-voltage HV transistor only. The implantation of the lightly doped LDDHV conduction regions is, for example, self-aligned with the widthwise superposition of ONO dielectric layers on the flanks of the HVG gate region of the high-voltage HV transistor.

[0060] In particular, the lightly doped conduction regions LDDHV are not implanted in the HWV box of the medium voltage transistor GP, for example by means of a mask blocking implantation in the active region of the medium voltage transistor GP.

[0061] Fig. 8 illustrates the result of a step 800 of deposition of one or more dielectric layer(s) HVSP accumulating on the sides of the gate regions HVG, GPG of the high voltage transistor HV and the medium voltage transistor GP, so as to form, in the end, the spacer regions of these transistors.

[0062] Figure 9 illustrates the result of steps 900 comprising etching in the region of the NVM floating-gate transistor, typically by photolithography, so as to define the FGCG gate region of the NVM floating-gate transistor. The etching is adapted to etch the stack of the second conductive layer P2, the dielectric layer superposition ONO, the first conductive layer PI, and the tunnel oxide layer TNOX. The FGCG gate region of the NVM floating-gate transistor thus comprises a floating gate PI situated between the tunnel oxide layer TNOX and a control gate P2, the floating gate PI and the control gate P2 being electrically isolated by the dielectric layer superposition ONO. Implantation of lightly doped conduction regions LDDNV is implanted in the NVW box of the NVM floating-gate transistor only.The implantation of the lightly doped LDDNV conduction regions is, for example, self-aligned with the FGCG gate region of the NVM floating-gate transistor.

[0063] In addition, steps 900 include the deposition of one or more NVSP dielectric layer(s) accumulating additionally on the flanks of the FGCG, HVG, GPG gate regions of the NVM floating gate transistor, the HV high voltage transistor, and the GP medium voltage transistor, so as to form, in the end, the spacer regions of these transistors.

[0064] Fig. 10 illustrates the result of 1000 steps comprising etching in the region of the low-voltage SRAM transistor, GO1, typically by photolithography, so as to define the gate region G0, G1 of the low-voltage SRAM transistor, GO1. The etching is adapted to etch the stack of the second conductive layer P2 and the gate oxide layer GO1OX.

[0065] A distinction is now made between the low voltage SRAM transistor of static random access memory cell, and the low voltage GO1 transistor of logic circuit.

[0066] In a first case, the implantation of the low-doped conduction regions LDD1 of the low-voltage transistor GO1 of the logic circuit, and the implantation of the low-doped conduction regions LDD0 of the low-voltage transistor SRAM of the static random-access memory cell, are carried out in separate steps 1000 and 1100.

[0067] In a second case, the implantation of the low-doped conduction regions LDD1 of the low-voltage transistor GO1 of the logic circuit, and the implantation of the low-doped conduction regions LDD0 of the low-voltage transistor SRAM of the static random-access memory cell, are done in a single step 1000 or 1100.

[0068] In the first case, the lightly doped conduction regions LDD1 of the low voltage transistor GO1 of the logic circuit are implemented in the 1000 steps, for example in a self-aligned manner on the gate region G1 of the low voltage transistor GO1 of the logic circuit.

[0069] In a first alternative of the second case, the low-doped conduction regions LDD0 of the low-voltage SRAM transistor of the static random-access memory cell, and the low-doped conduction regions LDD0 / 1 of the medium-voltage GP transistor are implemented at the same time and in the same way as the low-doped conduction regions LDD1 of the low-voltage GO1 transistor of the logic circuit in steps 1000.

[0070] Fig. 11 illustrates the result of steps 1100 comprising the deposition of one or more LVSP dielectric layer(s) on the sides of the gate regions G0, G1 of the low voltage transistors SRAM, GO1, and also accumulating on the sides of the gate regions of the high voltage transistor HV, the floating gate transistor NVM, and the medium voltage transistor GP, so as to finalize the formation of the spacer regions of these transistors.

[0071] In the first case mentioned above, steps 1100 include an implantation of the lightly doped conduction regions LDD0 of the low voltage SRAM transistor of static random access memory cell, for example in a self-aligned manner on the spacer region LVSP on the sides of the gate G0 of the low voltage SRAM transistor.

[0072] According to a preferred embodiment, the lightly doped conduction regions LDD0 / 1 of the medium-voltage transistor GP are implanted simultaneously and in the same way as the lightly doped LDDO conduction regions of the low voltage SRAM static random-access memory transistor in steps 1100 of the first case, specifically self-aligned to the LVSP, NVSP, HVSP spacer region on the sides of the GPG gate of the medium voltage GP transistor.

[0073] In a second alternative of the second case, the lightly doped conduction regions LDD1 of the low voltage transistor GO1 of the logic circuit, and the lightly doped conduction regions LDD0 / 1 of the medium voltage transistor GP are implemented at the same time and in the same way as the lightly doped conduction regions LDDO of the low voltage transistor SRAM of static random access memory in steps 1100.

[0074] Figure 12 illustrates the result of steps 1200 comprising an implantation of dopants forming SD conduction regions of all the SRAM, GO1, HV, NVM, and GP transistors in the circuit. The 1200 implantation is, for example, self-aligned with the spacer regions of each SRAM, GO1, HV, NVM, and GP transistor, comprising respective accumulations of ONO, HVSP, NVSP, and LVSP dielectric layers on the flanks of the corresponding G0, Gl, HVG, FGCG, and GPG gate regions. The SD conduction regions are implanted deeper into the PSUB substrate and with a higher dopant concentration than the lightly doped LDDO, LDD1, LDDHV, LDDNV, and LDDO / L conduction regions.

[0075] In particular, the accumulations of dielectric layers, HVSP, NVSP, LVSP on the flanks of the first gate region GPG of the first transistor GP, form the spacer regions having a first width wl in the direction perpendicular to the flanks of the first gate region GPG; and the accumulations of dielectric layers, ONO, HVSP, NVSP, LVSP on the flanks of the gate region HVG of the high voltage transistor HV, form the spacer regions having a second width w2 in the direction perpendicular to the flanks of the first gate region GPG.

[0076] Reference is made in this regard to figures 13 and 14.

[0077] Fig. 13 schematically illustrates an enlargement of a spacer region of an embodiment of a high voltage HV transistor as described above in relation to Figures 1 to 12.

[0078] Fig. 14 schematically illustrates an enlargement of a spacer region of an embodiment of a GP medium voltage transistor as described above in relation to Figures 1 to 12.

[0079] In these embodiments, within the same integrated circuit, the medium-voltage transistor GP and the high-voltage transistor HV have respective gate regions GPG and HVG, comprising a conductive layer PI having the same composition and thickness, given that the conductive layers PI have been formed during the same 400 steps.

[0080] On the other hand, the medium voltage transistor GP and the high voltage transistor HV have, in their respective spacer regions on the flanks of their gate regions PI, an accumulation of dielectric layers HVSP, NVSP, LVSP having the same constitutions and the same thicknesses, forming the entire spacer regions of the medium voltage transistor GP having a first width wl.

[0081] Since in the joint manufacturing process of the medium voltage transistor GP and the high voltage transistor HV at least one dielectric layer (ONO) of the accumulation was removed (step 510) for the medium voltage transistor, the high voltage transistor HV has said at least one additional dielectric layer ONO in the accumulation on the flanks of its gate PI, so as to form entire spacer regions having a second width w2 greater than the first width wl.

[0082] In the example described in relation to Figures 1 to 12, said at least one "additional" dielectric layer - present in the accumulation of dielectric layers forming the spacer region of the high voltage transistor HV, and absent from the accumulation of dielectric layers forming the spacer region of the medium voltage transistor GP - is the ONO superposition of oxide, nitride and silicon oxide layers.

[0083] That being said, in other examples, said at least one "additional" dielectric layer could be at least one of the other dielectric layers in the accumulation of dielectric layers forming the spacer region of the high voltage HV transistor, such as the HVSP, NVSP, LVSP dielectric layers, or other dielectric layers which have not been mentioned or shown in relation to Figures 1 to 12.

[0084] Furthermore, the GP medium-voltage transistor and the HV high-voltage transistor include lightly doped conduction regions LDD0 / 1, LDDHV implanted in the HVW housings, and more heavily doped conduction regions SD. The source and drain regions of the GP and HV transistors each incorporate a lightly doped conduction region LDD0 / 1, LDDHV, and a more heavily doped conduction region SD.

[0085] The lightly doped conduction regions LDDHV of the high voltage transistor HV extend into the channel region of the HV transistor, i.e. under the gate region HVG opposite the conductive layer PL. This ensures the voltage withstand of the high voltage transistor HV but requires a large gate length.

[0086] The lightly doped conduction regions LDD0 / 1 of the medium voltage transistor GP do not extend to the channel region of the GP transistor, and are located below the spacer regions.

[0087] Now, since some of the dielectric layers (ONO) accumulated on the sides of the GPG gate region of the GP medium-voltage transistor have been removed, the lightly doped conduction regions LDD0 / 1 have been brought closer to the channel region of the GP medium-voltage transistor. The channel region of the transistor is considered to be located in the HVW box, opposite the PI gate region. This makes it possible, on the one hand, to reduce impact ionization phenomena that generate "hot carriers" which degrade the transistor; and on the other hand, to have a suitable threshold voltage for optimized performance in the medium-voltage range, i.e., for example, below 5.7 V.

Claims

Demands

1. A method for manufacturing an integrated circuit including the fabrication of a first transistor (GP) for a first voltage range comprising: - steps (300, 400) of forming a first gate region (GPG) on a front face (FA) of a semiconductor substrate (PSUB) and having flanks perpendicular to the front face; - steps (500, 800, 900, 1100) of depositing dielectric layers (ONO, HVSP, NVSP, LVSP) accumulating on the flanks of the first gate region (GPG) so as to form spacer regions having a width (w2) in a direction perpendicular to the flanks of the first gate region; - an etching step (510) removing a portion of the dielectric layers (ONO) accumulated on the flanks of the first gate region so as to reduce the width (wl) of the spacer regions;- a first dopant implantation step (1100) aligned with the spacer regions, forming first lightly doped conduction regions (LDD0 / 1) of the first transistor (GP); - a second dopant implantation step (1200) forming first conduction regions (SD) of the first transistor (GP), more heavily doped than the lightly doped conduction regions (LDD0 / 1).

2. A method according to claim 1, wherein: - said dielectric layer deposition steps comprise a dielectric layer(s) (ONO) deposition step (500) prior to said etching step (510) and at least one other dielectric layer(s) (HVSP, NVSP, LVSP) deposition step (800, 900, 1100) subsequent to said etching step (510); - said etching step (510) is adapted to remove the dielectric layer(s) (ONO) deposited during the prior step (500).

3. A method according to claim 2, wherein the dielectric layer deposition step (500) prior to the etching step (510) comprises a deposition of a superposition of conformal layers of silicon oxide (O), silicon nitride (N), and silicon oxide (O).

4. A method according to any one of the preceding claims, including the manufacture of a second transistor (HV) for a second range of voltages comprising: - steps (300, 400) of forming a second gate region (HVG) on the front face (FA) of the semiconductor substrate (PSUB) and having flanks perpendicular to the front face; - the same steps (500, 800, 900, 1100) of depositing dielectric layers (ONO, HVSP, NVSP, LVSP) to form spacer regions on the flanks of the second gate region (HVG); and - a masking step (505) adapted to prevent said removal, during the etching step (510), of a part of the accumulations of dielectric layers (ONO) deposited on the flanks of the second gate region (HVG).

5. A method according to any one of the preceding claims, including the manufacture of a third floating gate transistor (NVM) comprising: - the same steps (300, 400) of forming the first gate region to form the floating gate of the third floating gate transistor (NVM), comprising: - a formation (300) of a tunnel dielectric layer (TNOX) on the front face (FA); - a formation (400) of an electrically conductive layer (PI) on the tunnel dielectric layer (TNOX).

6. A method according to any one of the preceding claims, including the manufacture of a fourth transistor (SRAM, GO1) for a fourth voltage range comprising: - the same first dopant implantation step (1100), forming fourth lightly doped conduction regions (LDD0, LDD1) of the fourth transistor (SRAM, GO1).

7. A method according to any one of the preceding claims, including the manufacture of a fourth transistor (SRAM, GO1) for a fourth voltage range comprising: - the same etching step (510) removing a portion of the dielectric layers (ONO) accumulated on the front face (FA) of the semiconductor substrate (PSUB).

8. An integrated circuit comprising a first transistor (GP) adapted for a first voltage range, and a second transistor (HV) adapted for a second voltage range, the first transistor (GP) comprising a first gate region (GPG) and the second transistor (HV) comprising a second gate region (HVG), the gate regions (GPG, HVG) being located on a front face (FA) of a semiconductor substrate (PSUB) and having flanks perpendicular to the front face, and each comprising a conductive layer (PI) having the same constitution and the same thickness, - the first transistor (GP) and the second transistor (HV) comprising an accumulation of dielectric layers (HVSP, NVSP, LVSP) having the same constitutions and the same thicknesses on the flanks of their gate regions (PI) so as to form spacer regions having, respectively, a first width (wl) and a second width (w2) in a direction perpendicular to the flanks of the gate regions, - the first transistor comprising, in the semiconductor substrate (PSUB), first lightly doped conduction regions (LDD0 / 1) aligned with the spacer regions, and first more heavily doped conduction regions (SD),wherein the second transistor (HV) further comprises at least one additional dielectric layer (ONO) in said accumulation so as to form spacer regions having a second width (w2) greater than the first width (wl) of the spacer regions of the first transistor (GP).

9. Integrated circuit according to claim 8, further comprising a third floating gate transistor (NVM) having a floating gate region (FG) comprising a tunnel dielectric layer (TNOX) on the front face (FA) and, on the tunnel dielectric layer (TNOX), a conductive layer (PI) having the same constitution and thickness as the conductive layer (PI) of the first gate region (GPG) and the second gate region (HVG), wherein the first gate region (GPG) has a dielectric layer (TNOX) on the front face (FA) having the same constitution and thickness as the tunnel dielectric layer (TNOX).

10. Integrated circuit according to any one of claims 8 or 9, further comprising a fourth transistor (SRAM, GO1) adapted for a fourth voltage range comprising, in the semiconductor substrate (PSUB), fourth lightly doped conduction regions (LDDO, LDD1) having the same constitution and depth as the first lightly doped conduction regions (LDD0 / 1).

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