METHOD FOR MANUFACTURING A HIGHLY RESISTIVE SEMICONDUCTOR STACK AND ASSOCIATED STACK

Abstract

METHOD FOR MANUFACTURING A HIGHLY RESISTIVE SEMICONDUCTOR STACK AND ASSOCIATED STACK One aspect of the invention relates to a method for manufacturing a semiconductor stack (10), comprising, from a first silicon layer (11), called the support layer: forming a silicon carbide layer (12), extending over the support layer (11); andannealing the layers until cavities (13) are formed, each cavity (13) extending into the support layer (11), from the silicon carbide layer (12). Figure to be published with the abstract: Figure 1

Description

Title of the invention: METHOD FOR MANUFACTURING A HIGHLY RESISTIVE SEMICONDUCTOR STACK AND ASSOCIATED STACK TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of semiconductor stacks intended to form silicon-on-insulator substrates, also called "SOI" substrates for "Silicon On Insulator" in English, and more particularly SOI substrates used in the field of radio frequencies. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Highly resistive semiconductor stacks, such as silicon-on-insulator, or SOI, substrates, are widely used for radio frequency applications because they promote the integrity of signals circulating in devices made on their surface.

[0003] An SOI substrate comprises a first semiconductor layer, made of silicon, called the "support layer" or "base", a second semiconductor layer, made of silicon, called the "active layer". The active layer is intended to accommodate microelectronic components, manufactured in or on the active layer. In this case, we speak of "initial" or "front end" components, also "FEOL" for "Front End Of Line" in English. The active layer is separated from the support layer by an insulating layer, for example made of silicon oxide, arranged between the support layer and the active layer, and more particularly under the active layer. The insulating layer is then called "buried" or "BOX" for "Burried OXide". The insulating layer makes it possible to confine the majority charge carriers in the active layer, which makes it possible to envisage a high operating frequency of the front end components, for example up to several tens of gigahertz.

[0004] However, charge carriers can accumulate in the support layer, in the vicinity of the insulating layer, creating a conductive sub-layer which strongly penalizes conduction in the active layer. There is therefore a need to reduce the circulation of charge carriers in the support layer, in the vicinity of the insulating layer.

[0005] The article [“RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate”, Dimitri Lederer and Jean-Pierre Raskin, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 7, JULY 2008] provides a solution to this problem by forming a trapping layer, arranged between the support layer and the insulating layer, the role of which is to trap the carriers of charges. The trapping layer comprises polycrystalline silicon. The trapping of charge carriers then takes place at the grain boundaries, where the dangling bonds of the silicon are located. The trapping layer is deposited in low-pressure vapor phase (also called "LPCVD" for "Low Pressure Chemical Vapor Deposition" in English), followed by rapid annealing at a temperature of 1000 °C, in order to form the silicon grains.

[0006] The effectiveness of the trapping layer is based on the density of dangling bonds in the silicon and therefore on the density of grain boundaries. However, the heat treatments implemented during the manufacture of microelectronic components at the level of the active layer tend to reduce the number of grains and therefore reduce the number of grain boundaries. The polycrystalline silicon trapping layer therefore imposes a restricted thermal budget.

[0007] Another approach to trapping charge carriers is to form bubbles in the support layer, near the interface between the support layer and the insulating layer. The dangling bonds at the free surface of each bubble then allow the trapping of charge carriers. The article [“Chemical and electrical properties of cavities in Silicon and germanium”, SM Myers, DM Follstaedt, GA Petersen, CH Seager, HJ Stein & WR Wampler, Nuclear instruments and Methods in Physics Research B 106 (1995) 379-385] describes a method of forming bubbles in a silicon layer by implanting helium ions. However, the bubbles formed are about 200 nm away from the interface between the support layer and the insulating layer. Furthermore, the maximum bubble density is located at a distance from the interface between 1000 nm and 1500 nm. The trapping capacity at the interface is therefore limited.Furthermore, modulating the implantation energy to bring the bubbles closer to the interface could cause exfoliation of the insulating layer. In addition, the implantation time can be long (of the order of 20 min to implant ions into a 300 mm diameter substrate, under an implantation current of 10 mA and a dose of 1017 cm2).

[0008] Another known solution is described in document FR3091011 A1 which discloses an SOI substrate comprising a layer of polycrystalline silicon carbide extending on the surface of the support layer. The carbide layer is preferably polycrystalline and thus makes it possible to trap the charge carriers, in the same way as a polycrystalline silicon trapping layer. The growth of the carbide layer is carried out by growth from the support layer using a carbon precursor or by CVD. However, the thickness of the disclosed carbide layer is limited to 5 nm. However, at low thickness, the carbide layer is chemically fragile and can be contaminated by species introduced during additional manufacturing steps (such as the manufacturing of the insulating layer and / or the active layer) and having migrated to the carbide layer.

[0009] There is therefore a need to provide a semiconductor stack that can effectively trap charge carriers in the support layer and that is also robust with respect to additional manufacturing steps (such as the manufacturing of the insulating layer, the active layer or even the “front end” components). Summary of the invention

[0010] The invention relates to a method for manufacturing a semiconductor stack, comprising, from a first silicon layer, called the support layer: • the formation of a silicon carbide layer, extending over the support layer, having a thickness, measured from the support layer, greater than 5 nm, a fraction of carbon atoms in the silicon carbide layer, less than 20 nm from the support layer, being strictly greater than 50%; and • annealing the support layer and the silicon carbide layer until cavities are formed, each cavity extending into the support layer, from the silicon carbide layer, an oxygen concentration in contact with the silicon carbide layer, during the annealing step, being less than 10 ppm and preferably less than 5 ppm, or even zero.

[0011] During annealing, the silicon atoms of the support layer migrate towards the carbide layer, thus forming, from the carbide layer, cavities, i.e. hollow zones located in the support layer.

[0012] The cavities formed in the support layer provide dangling silicon bonds and thus allow charge carriers to be trapped in the support layer. The arrangement of the cavities allows charge carriers to be effectively trapped as close as possible to the interface between the support layer and the carbide layer.

[0013] In addition, the silicon carbide present is a semiconductor having an indirect band gap whose deviation is greater than 2 eV, or even 3 eV. The carbide layer thus prevents the circulation of charge carriers in the vicinity of the insulating layer.

[0014] Since the trapping does not rely on the presence of grain boundaries, which are sensitive to temperature, the stack then has improved morphological stability. In addition, during a heat treatment, the temperature involving the coalescence of the cavities is significantly higher than the temperature involving the coalescence of the grains in a polycrystalline structure. The temperature involving the coalescence of the cavities is also higher than the temperatures used during additional manufacturing steps. Moreover, while the coalescence of the grains is accompanied by a disappearance of traps, the possible coalescence of the cavities occurs at a constant surface.

[0015] The silicon carbide layer being richer in carbon, it makes it possible to activate the migration of silicon atoms from the support layer during annealing and effectively form the cavities.

[0016] The thickness of the silicon carbide layer greater than 5 nm improves its robustness, particularly chemical, with respect to additional manufacturing steps (such as the manufacture of “front end” components). Indeed, it is less affected by contaminants that can migrate.

[0017] The silicon carbide layer may undergo pitting oxidation when annealed in an environment containing oxygen. Pitting damages the silicon carbide layer and can slow down the migration of silicon atoms and therefore the formation of cavities. Annealing carried out in an oxygen-poor atmosphere limits the occurrence of pitting and therefore improves the reproducibility of the process.

[0018] Finally, the method does not rely on ion implantation to form the cavities, simplifying its implementation.

[0019] Annealing can be carried out for a period of between 15 min and 2 h at a temperature of between 900°C and 1100°C.

[0020] The silicon carbide layer resulting from the formation step is advantageously amorphous and the annealing of the layers is advantageously carried out so as to crystallize the silicon carbide layer in a polycrystalline arrangement.

[0021] The support layer is advantageously oriented in a plane.

[0022] A fraction of carbon atoms of the silicon carbide layer, less than 20 nm from the support layer, measured perpendicular to the plane, is advantageously less than or equal to 70%.

[0023] The thickness of the silicon carbide layer is preferably less than 500 nm.

[0024] Each cavity may have facets, each facet being preferentially oriented parallel to a crystallographic plane forming, for example, part of the {111} family of crystallographic planes or part of the {113} family of crystallographic planes.

[0025] The cavities extend over a distance, measured perpendicular to the plane and from the silicon carbide layer, preferably between 5 nm and 100 nm.

[0026] The method preferably comprises the formation of an insulating layer extending over the silicon carbide layer. The insulating layer is advantageously intended to form a “buried” layer called “BOX” for “Burried OXide” in English.

[0027] According to a first embodiment, the formation of the insulating layer is carried out by deposition, before said annealing.

[0028] The annealing of the support layer, the silicon carbide layer and the insulating layer can be carried out under an atmosphere comprising an oxygen concentration of less than 1%.

[0029] According to a second embodiment, the formation of the insulating layer is carried out by transfer from a donor substrate, after annealing the layers.

[0030] In a manner common to both aforementioned embodiments, the method may comprise the formation of a second crystalline layer, extending over the insulating layer. The insulating layer then forms a “BOX” layer.

[0031] Another aspect of the invention relates to a semiconductor stack comprising: • a first silicon layer, called the support layer; • a layer of silicon carbide, extending over the support layer, having a thickness, measured from the support layer, greater than 5 nm; and • cavities, each cavity extending into the support layer from the silicon carbide layer.

[0032] The silicon carbide layer is advantageously polycrystalline.

[0033] Advantageously, each cavity has a free surface surrounding an interior volume, at least a portion of the free surface separating said interior volume from the support layer and at least another portion of the free surface separating the interior volume from the silicon carbide layer.

[0034] Advantageously, each portion of the free surface separating the interior volume of the cavity from the support layer comprises silicon atoms of which at least a part has a dangling bond.

[0035] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0036] The figures are presented for information purposes only and in no way limit the invention. Unless otherwise specified, the same element appearing in different figures has a single reference.

[0037] [Fig. 1] schematically represents a first embodiment of a stack semiconductor according to the invention.

[0038] [Fig.2] schematically represents a first mode of implementation of a method manufacturing process according to the invention.

[0039] [Fig.3a] schematically represents a first example of a first stage of the manufacturing method according to the invention.

[0040] [Fig.3b] schematically represents a second example of the first stage of the manufacturing method according to the invention.

[0041] [Fig.4] schematically represents a second stage of the manufacturing process according to the invention.

[0042] [Fig.5] schematically represents a third stage of the manufacturing process according to the invention.

[0043] [Fig.6] schematically represents a fourth step of the manufacturing process according to the invention.

[0044] [Fig.7] schematically represents a second mode of implementation of a manufacturing method according to the invention.

[0045] [Fig.8] schematically represents a fifth step of the manufacturing process according to the invention. DETAILED DESCRIPTION

[0046] The invention proposes to improve the semiconductor stacks intended to form an SOI substrate and in particular a substrate intended for radiofrequency applications.

[0047] [Fig. 1] schematically represents a first embodiment of a semiconductor stack 10 according to the invention. The stack 10 comprises • a first silicon layer 11, called the support layer; • a layer of silicon carbide 12; and • cavities 13.

[0048] The support layer 11 extends for example along a given plane P. This is for example the plane of a silicon wafer from which a substrate SOL will be formed. The support layer 11 is advantageously a resistive support, that is to say having a resistivity greater than 1 kΩ-cm.

[0049] The silicon carbide layer 12 (also called the SiC layer) extends over the support layer 11 along the given plane P. The SiC layer 12 is directly in contact with the support layer 11, thus forming an interface 112 between the two layers.

[0050] The stack 10 is remarkable in that it comprises a plurality of cavities 13 extending into the support layer 11. Each cavity 13 is hollow, i.e. empty of any solid or liquid material. They may comprise a species in gaseous form having a low partial pressure. However, they are preferably completely empty. Each cavity 13 extends into the support layer 11, from the SiC layer 12. That is to say that each cavity 13 extends into the support layer 11 from the interface 112. Each cavity 13 then has a free surface 131, 132 surrounding an interior volume 130 of the cavity 13. At least one portion 131 of the free surface separates said interior volume 130 from the support layer 11 and at least one another portion 132 of the free surface separates the interior volume 130 of the cavity from the SiC layer 12.

[0051] The portion(s) 131 of the free surface separating the interior volume 130 of the cavity from the support layer 11 are formed of silicon atoms, at least a portion of which has a dangling bond. By dangling bond, we mean an atomic orbital not involved in a chemical bond with other elements. The dangling bonds make it possible to trap the charge carriers circulating in the support layer 11 and in the vicinity of the SiC layer 12.

[0052] The dangling bonds and the cavities also make it possible to trap impurities, such as hydrogen ions or atoms, helium atoms or metals such as lithium or copper, having migrated into the support layer 11 during, for example, additional manufacturing steps (such as the manufacturing of “front end” components). The resistivity of the support layer 11 is therefore not degraded during additional manufacturing steps.

[0053] The thermodynamic stability of the cavities 13 and their formation by diffusion tend to favor faceting of the cavities. Portions 131 of the free surface 131, 132 of each cavity 13 then preferentially align according to crystallographic planes of the support layer 11. For example, when the support layer 11 has a (001) plane, at the interface 112 with the SiC layer 12 (i.e. the (001) plane and the P plane coincide), the cavities 13 can be faceted by having portions parallel to crystallographic planes of the family of planes {111} (i.e. the planes (111), (-111), (1-11) and (-1-11)) or of the family of planes {113} (i.e. the planes (113), (-113), (1-13) and (-1-13)). However, the faceting does not necessarily depend on the plane at the interface 112 of the support layer 11 with the SiC layer 12. Other families of crystallographic planes are conceivable.

[0054] [Fig. 1] represents by arrows the directions

[111] and

[001] , normal to the crystallographic planes (001) and (111).

[0055] Each cavity 13 preferably extends from the SiC layer 12 over a distance 133 of between 5 nm and 100 nm. Said distance 133 is measured perpendicular to the plane P in which the SiC layer 12 extends, i.e. along

[001] in the present example. Said distance 133 is measured from the carbide layer 12, i.e. from the interface 112 separating the support layer 11 and the carbide layer 12.

[0056] In the example of [Fig.l], the stack 10 also comprises an insulating layer 14 and an active layer 15. In this way, the stack 10 forms a substrate SOL. The insulating layer 14 extends over the SiC layer 12. It advantageously has a thickness of between 100 nm and 1000 nm. It comprises, for example, an oxide, such as silicon oxide SiO2. The active layer 15 comprises a crystalline or polycrystalline semiconductor and extends over the insulating layer 14. The insulating layer 14 thus separates the SiC layer 12 and the active layer 15. It is said to be “buried” under the active layer 15. The active layer 15 advantageously has a thickness of between 50 nm and 500 nm and comprises, for example, crystalline silicon or polycrystalline silicon or another crystalline semiconductor material used in the radiofrequency field, such as indium phosphide or gallium nitride.

[0057] The SiC layer 12 is advantageously polycrystalline. Thus, it contributes to the trapping of charge carriers, in the same way as a polycrystalline silicon trapping layer, as described in the prior art. The charge carriers are trapped by the dangling bonds located at the grain boundaries of the polycrystalline arrangement.

[0058] [Fig.2] schematically represents a manufacturing method according to the invention, making it possible to manufacture the stack 10.

[0059] The manufacturing method 20 comprises, from a support layer 11, a step 22 of forming a silicon carbide layer 12 (called SiC layer), extending over the support layer 11. Two examples of silicon carbide layer 12 obtained are illustrated in [Fig.3a] and [Fig.3b].

[0060] The SiC layer 12 is for example formed 22 by vapor deposition, also called “CVD” for “Chemical Vapor Deposition” in English, from the support layer 11. This is for example a plasma-assisted CVD deposition (or “PECVD” for “Plasma Enhanced CVD” in English). The SiC layer 12 is for example obtained by PECVD deposition of a carbon precursor, such as tetramethylsilane Si(CH 3) 4, also called “TMS”. The SiC layer 12 produced then extends over the support layer 11.

[0061] The support layer 11 extends in a plane P. It preferably has a crystallographic plane (001) in the plane P. The SiC layer 12 has a thickness 121, measured from the support layer 11 and perpendicular to the plane P, greater than 5 nm and advantageously less than 500 nm.

[0062] The method 20 further comprises a step 23 of annealing the support layer 11 and the SiC layer 12 until cavities 13 extending into the support layer 11 are formed, as illustrated in [Fig. 4]. Each cavity 13 then extends into the support layer 11, from the SiC layer 12. During the annealing 23, the temperature increases the mobility of the silicon atoms of the support layer 11 and a portion of these atoms, in particular those close to the SiC layer 12. The difference in fractions of silicon atoms between the support layer 11 and the SiC layer 12 tends to direct the migration of the silicon atoms from the support layer 11 to the SiC layer 12, thus digging several cavities 13 in the support layer 11. The formation of each cavity 13 then finds its starting point at the interface between the support layer 11 and the SiC layer 12. Each cavity 13 then extends into the support layer 11 in a direction substantially perpendicular to the plane P. By substantially perpendicular is meant perpendicular to within 20°. The annealing 23 of the support layer 11 and the SiC layer 12 is preferably simultaneous.

[0063] When the support layer 11 comprises defects such as amorphous zones or grain boundaries, these defects can assist or facilitate the migration of silicon atoms towards the SiC layer 12.

[0064] The annealing temperature 23 for forming cavities 13 is advantageously between 900°C and 1100°C. Below 900°C, the mobility of the silicon atoms is not sufficient to form cavities 13 in a time that can be compatible with an industrial rate. Above 1100°C, the mobility of the silicon atoms is such that it allows the migration of atoms between cavities 13, tending to form cavities that are few in number but of very large sizes (i.e. extending beyond 100 nm of the SiC layer 12). The trapping of charge carriers is improved when the density of cavities 13 (i.e. the number of cavities 13 per unit area of ​​the interface 112) increases. Trapping, on the other hand, deteriorates when the density of cavities 13 decreases.

[0065] The SiC layer 12 is advantageously formed at a temperature between 300°C and 500°C. In this way, it has, before annealing 23, an amorphous phase. The annealing 23 of the layers, and in particular of the SiC layer 12, between 900°C and 1100°C has the effect of crystallizing the SiC layer 12 in a polycrystalline arrangement. This crystallization has two beneficial effects. Firstly, the grain boundaries of the polycrystalline arrangement contribute to the trapping of charge carriers, reinforcing the trapping achieved by the cavities 13. Secondly, the crystallization also accelerates the migration of silicon atoms from the support layer 11 to the SiC layer 12, in a manner similar to pumping of silicon atoms, having the effect of accelerating the formation kinetics of the cavities 13.

[0066] The annealing 23 is advantageously carried out for a duration of between 15 min and 2 h, so that the migration of the silicon atoms from the support layer 11 makes it possible to obtain cavities 13 extending at least 5 nm from the SiC layer 12 and at most 100 nm from this layer. The dimension of the cavities 13 (measured perpendicular to the plane P and from the SiC layer 12) is proportional to the duration of the annealing 23. An annealing duration of the order of 15 min is compatible with an industrial rate. An annealing duration of the order of 2 h makes it possible to form cavities 13 of large sizes, close to 100 nm, extending the coverage of the trapping of the charge carriers in the support layer 11. The annealing duration of the order of 2 h is also compatible with an industrial rate. Indeed, annealing can be carried out in a furnace, allowing several plates to be treated simultaneously, for example several dozen. In contrast, the ion implantation that can be implemented in the prior art performs treatment plate by plate.

[0067] The migration of the silicon atoms, and therefore the kinetics of formation of the cavities 13, is accelerated when the SiC layer 12 has a fraction of carbon atoms (also called carbon fraction) which is, before annealing 23, at least equal to the fraction of silicon atoms. The SiC layer 12 thus has, before annealing 23, a carbon fraction greater than 50% and advantageously less than 70%. The silicon fraction in the SiC layer 12 is thus, before annealing 23, less than 50.

[0068] The formation kinetics of the cavities 13 is especially accelerated when the difference in fractions between the carbon and silicon atoms is significant in the vicinity of the interface 112 between said SiC layer 12 and the support layer 11. The carbon fraction of the SiC layer 12 beyond 20 nm from the support layer 11 does not, however, show any significant impact on the formation kinetics of the cavities 13. Also, when the SiC layer 12 has a thickness 121 greater than 20 nm (measured perpendicular to the plane P and from the interface 112 with the support layer 11), as illustrated by [Fig. 3a], it then has a part, extending at least 20 nm from the support layer 11 and in which the carbon fraction is greater than 50% and advantageously less than or equal to 70%. When the SiC layer 12 has a thickness 121 less than or equal to 20 nm, as illustrated by [Fig.3b], it then has, over its entire thickness 121, a carbon fraction greater than 50% and advantageously less than or equal to 70%. In other words, the carbon fraction of the SiC layer 12, less than 20 nm from the support layer 11 (measured perpendicular to the plane P and from the interface 112), is advantageously between 50% and 70%.

[0069] The SiC layer 12 reacts with oxygen and can oxidize, for example by pitting. The annealing 23 is therefore carried out by minimizing the contact of oxygen with the SiC layer 12. The annealing 23 of the stack 10 is carried out by maintaining a concentration of oxygen in contact with the SiC layer 12 which is less than 10 ppm, preferably less than 5 ppm, or even zero.

[0070] The annealing 23 is for example carried out in a neutral atmosphere, comprising for example at least one neutral gas such as nitrogen or argon. The neutral atmosphere is then dimensioned so that it then has an oxygen concentration of less than 10 ppm, or even less, at least for the duration of the annealing 23.

[0071] The method 20, according to the embodiment of [Fig.2], can also comprise a step 25 of forming an insulating layer 14 and a step 26 of forming an active semiconductor layer 15 so that the stack 10 final forms an SOI substrate, as illustrated in [Fig. 1].

[0072] The formation 25 of the insulating layer 14, illustrated by [Fig. 6], is advantageously carried out by transfer from a donor substrate 30. The principle of transfer from a donor substrate 30 is known under the name SmartCut(TM). When the formation 25 of the insulating layer 14 is carried out by transfer, the formation 26 of the active layer 15 is advantageously also carried out by transfer from a donor substrate and if possible from the same donor substrate 30. Advantageously, the formation 25, 26 of the two aforementioned layers is carried out simultaneously.

[0073] Before forming 25 the insulating layer 14, it may be necessary to prepare a surface 122 of the SiC layer 12, intended to accommodate the insulating layer 14. In this case, the method 20 comprises, before forming 25 the insulating layer 14, a step 24 of smoothing said surface 122. The smoothing 24, illustrated by [Fig. 5], may be carried out by chemical mechanical planarization or CMP for “Chemical Mechanical Polishing” in English. The smoothing 24 is carried out so that the SiC layer 12 has a surface roughness less than or equal to 5 Å. The surface roughness is also called average roughness or “RMS” roughness for “Root Mean Square” in English. The roughness of the surface 122 of the SiC layer can be evaluated using an atomic force microscope, or “AFM”. The roughness can be evaluated on a portion of the surface 122 of approximately 1 pm2.

[0074] The simultaneous formations 25, 26 of the insulating and active layers 14, 15 by transfer can be carried out from the same donor substrate 30, the latter then comprising a semiconductor layer 35, for example made of crystalline or polycrystalline silicon or of crystalline indium phosphide or of crystalline gallium nitride, on which extends an insulating layer 34, for example made of silicon oxide. The insulating layer 34 has for example a thickness of between 100 nm and 1000 nm. The underlying semiconductor layer 35 has for example a thickness greater than 50 nm, or even greater than 500 nm.

[0075] The simultaneous formations 25, 26 can then comprise a sub-step of implantation of light ions (for example hydrogen or helium ions) in the semiconductor layer 35 of the donor substrate 30 up to a depth of between 50 nm and 500 nm under the insulating layer 34. The implantation is for example carried out at a dose of a few 1016 / cm2 and at an energy of a few tens of keV.

[0076] The simultaneous formations 25, 26 then comprise a sub-step of cleaning the free surface 341 of the insulating layer 34 of the donor substrate 30, in order to allow direct bonding between said insulating layer 34 of said donor substrate 30 and the SiC layer 12 of the stack 10. The cleaning of the free surface 341 of the insulating layer 34 advantageously uses known recipes from silicon technologies such as the so-called “RCA” recipe (for “Radio Corporation of America” in English) or a so-called CARO recipe, comprising a mixture of hydrogen peroxide and sulfuric acid.

[0077] It is however advantageous, to allow good adhesion of the insulating layer 34 to the SiC layer 12, that the cleaning is also followed by an activation of the free surface 341 of the insulating layer 34 of the donor substrate 34. Said activation is for example carried out by means of a plasma, for example oxygen or nitrogen.

[0078] The simultaneous formations 25, 26 of the insulating and active layers 14, 15 by transfer comprise a sub-step of bonding the donor substrate 30 onto the stack 10, as illustrated by [Fig.6], the free layer 341 of the insulating layer 34 of the donor substrate 34 being pressed against the SiC layer 12 of the stack 10. The bonding is then followed by an annealing called “separation annealing”, aimed at separating the semiconductor layer 35 of the donor substrate 30 into two parts, along a plane comprising the previously implanted light ions. The stack 10 thus comprises, after separation annealing, an insulating layer 14, as illustrated by [Fig.1], extending over the SiC layer 12 (because bonded to the latter). The semiconductor layer 35 forms the active layer 15 of the stack 10.

[0079] A planarization of the active layer 15 and / or a complementary annealing of the stack 10 can be carried out to prepare the active layer 15 and / or improve the adhesion of the layers of the stack 10.

[0080] [Fig.7] schematically represents a second mode of implementation of the method 20. According to this mode of implementation, the step 25 of forming the insulating layer 14 occurs before the step 23 of annealing the stack 10. This inversion of the steps makes it possible to simplify the step 23 of annealing in that the neutral atmosphere, previously described, no longer needs to have an oxygen concentration of less than 10 ppm. It can be less than only 1%. The manufacturing method 20 is thus simpler to implement, particularly with industrial equipment.

[0081] According to this embodiment, the insulating layer 14 is formed on the SiC layer 12, as illustrated by [Fig. 8]. It forms a barrier making it possible to reduce, or even stop, the diffusion of species coming from the surrounding atmosphere towards the SiC layer 12. The stack 10 can then simply be annealed 23 in a neutral atmosphere having an oxygen concentration of less than 1%.

[0082] The formation 25 of the insulating layer 14 before annealing is preferably carried out by CVD deposition, for example of a tetraethyl orthosilicate precursor Si(OCH2CH 3)4 (also called “TEOS”). The CVD deposition is advantageously plasma-assisted (called PECVD) to produce, from the precursor, a layer of silicon dioxide SiO2. This deposition can be carried out at a temperature between 300°C and 500°C, in order to not to anticipate the annealing 23 of the stack 10. The deposition is carried out so as to form an insulating layer 14 having a thickness 121, measured perpendicular to the plane P, between 100 nm and 1000 nm.

[0083] The formation 25 of the insulating layer 14 is advantageously carried out in the same equipment as that used to form the SiC layer 12. This makes it possible to prevent water vapor, coming from the external atmosphere (for example from the clean room), from being deposited on the SiC layer 12 (at the risk of oxidizing the latter).

[0084] The method 20 may also comprise, in order to manufacture a stack 10 of the SOI substrate type, the formation 26 of the active layer 15. Unlike the embodiment of [Fig. 2], the method 20 according to [Fig. 7] only forms the active layer 15 after the annealing 23. The active layer 15 may be formed by transfer from a donor substrate 30 as illustrated by [Fig. 6]. However, the donor substrate 30 here only comprises the crystalline or polycrystalline semiconductor layer 35. The formation 25 of the insulating layer 14 before the annealing 23 thus makes it possible to simplify the step 26 of forming the active layer 15 by transfer, in that only one layer is transferred.

[0085] The formation 26 of the active layer 15 by transfer preferably comprises an implantation of light ions, as described previously. However, the implantation depth is adjusted in order to transfer, onto the stack 10, an active layer 15 having a thickness of between 50 nm and 500 nm. The bonding of the donor substrate 30 is also preferably prepared as described previously. The free surface of the donor substrate 30 is in particular also activated by means of an oxygen or nitrogen plasma in order to improve the bonding.

[0086] The insulating layer 14 of the stack 10 may also comprise, before the formation 26 of the active layer 15, a smoothing 24 of a surface 141 of the insulating layer intended to receive the active layer 15. The smoothing 24 is advantageously similar to the smoothing described with reference to [Fig.5].

[0087] The method 20 may also comprise, in a manner common to the embodiments of [Fig. 2] and [Fig. 7], a step 21 of providing the support layer 11, prior to the step of forming the SiC layer 12. In addition to the provision of the support layer 11, the provision step 21 may comprise the preparation of the support layer 11 so as to allow, or even promote, during the annealing 23, the diffusion of the silicon atoms from the support layer 11 to the SiC layer 12. The preparation may comprise the removal of organic or metallic contaminants, dopants or particles. The removal may be carried out by implementing known recipes such as a wet recipe called "CARO" (aimed at removing organic contaminants) or sequences of the "RCA" recipe, comprising for example a cleaning called "HF" (aimed at removing dopants), a cleaning called "SCI" ​​(aimed at removing organic contaminants and particles) and / or so-called “SC2” cleaning (aimed at removing metallic contaminants). When the support layer 11 comprises a native oxide, it is then advantageous to remove it, for example by means of a plasma, preferably in the chamber which will accommodate the formation 22 of the SiC layer 12, or even the annealing 23 of the stack 10.

Claims

Claims

1. Method (20) for manufacturing a semiconductor stack (10), comprising, from a first silicon layer (11), called the support layer: - the formation (22) of a silicon carbide layer (12), extending over the support layer (11), having a thickness (121), measured from the support layer (11), greater than 5 nm, a fraction of carbon atoms of the silicon carbide layer (12), less than 20 nm from the support layer (11), being strictly greater than 50%; and - annealing (23) the support layer (11) and the silicon carbide layer (12) until cavities (13) are formed, each cavity (13) extending into the support layer (11) from the silicon carbide layer (12), an oxygen concentration in contact with the silicon carbide layer (12), during the annealing step (23), being less than 10 ppm.

2. Method (20) according to the preceding claim, in which the annealing (23) is carried out for a period of between 15 min and 2 h at a temperature of between 900°C and 1100°C.

3. Method (20) according to one of the preceding claims, in which the silicon carbide layer (12) resulting from the formation step (22) is amorphous, the annealing (23) of the layers being carried out so as to crystallize the silicon carbide layer (12) in a polycrystalline arrangement.

4. Method (20) according to one of the preceding claims, in which the support layer (11) is oriented in a plane (P) and in which a fraction of carbon atoms of the silicon carbide layer (12), less than 20 nm from the support layer (11), is less than or equal to 70%

5. / 0. Method (20) according to one of the preceding claims, in which the thickness (121) of the silicon carbide layer (12) is less than 500 nm.

6. Method (20) according to one of the preceding claims, in which each cavity (13) has facets, each facet being preferably- ably oriented parallel to a crystallographic plane.

7. Method (20) according to one of the preceding claims, in which the support layer (11) is oriented in a plane (P) and in which the cavities (13) extend over a distance (133), measured perpendicular to the plane (P) and from the silicon carbide layer (12), of between 5 nm and 100 nm.

8. A method (20) according to one of the preceding claims, comprising forming (25) an insulating layer (14) extending over the silicon carbide layer (12).

9. Method (20) according to the preceding claim, in which the formation (25) of the insulating layer (14) is carried out by deposition, before said annealing (23).

10. Method (20) according to one of the two preceding claims, in which the annealing (23) of the support layer (11), the silicon carbide layer (12) and the insulating layer (14) is carried out under an atmosphere comprising an oxygen concentration of less than 1%.

11. Semiconductor stack (10) comprising: - a first silicon layer (11), called the support layer; - a silicon carbide layer (12), extending over the support layer (11), having a thickness (121), measured from the support layer (11), greater than 5 nm; and - cavities (13), each cavity (13) extending into the support layer (11) from the silicon carbide layer (12).

12. Semiconductor stack (10) according to the preceding claim, in which the silicon carbide layer (12) is polycrystalline.

13. Semiconductor stack (10) according to one of the two preceding claims, in which each cavity (13) has a free surface (131, 132) surrounding an interior volume (130), at least one portion (131) of the free surface separating said interior volume (130) from the support layer (11) and at least one other portion (132) of the free surface separating the interior volume (130) from the silicon carbide layer (12).

14. Semiconductor stack (10) according to the preceding claim, in which each portion (131) of the free surface separating the interior volume (130) of the cavity (13) from the support layer (11) comprises silicon atoms of which at least a part has a bond hanging.

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