METHOD FOR MANUFACTURING MULTIPLE INTEGRATED CIRCUIT PACKAGES

Abstract

According to one aspect, an integrated circuit package (BT) is proposed comprising a support substrate (SUB) having a mounting face (FM), a side wall (RES) having an inner face (FINT) and an outer face (FEXT), the inner face (FINT) delimiting with the mounting face (FM) a cavity (ZCI), the outer face (FEXT) having a step (STP) extending outwards from the package (BT), an electronic chip (CHP) disposed in the cavity (ZCI) and electrically connected to electrically conductive contact pads (PAD), a sealing means (CAP), bonded by means of an adhesive (GL2), to an upper face (FH) of the side wall (RES) and sealing the cavity (ZCI), said adhesive (GL2) not extending onto the outer face (FEXT) of the side wall (RES),and electrically conductive connection means (BP) located on a lower face (FL) of the support substrate (SUB) and in electrical cooperation with said contact pads (PAD) via an interconnection network (INTCNX) located in the support substrate (SUB). Figure for the abstract: Fig 6,

Description

Title of the invention: METHOD FOR MANUFACTURING SEVERAL INTEGRATED CIRCUIT PACKAGES

[0001] Embodiments and implementations relate to the field of electronics, in particular the field of packaging of integrated circuits and more particularly the manufacture of several integrated circuit packages.

[0002] The manufacture of integrated circuit packages can be carried out from a support plate or substrate, for example but not limited to the laminate substrate type, on which the packages can be produced before their individualization by cutting the plate.

[0003] The boxes can be distributed by row and by column, in dedicated locations mutually separated by a wall which, after cutting, will form a side wall for each individual box.

[0004] This wall delimits for each location, a cavity where the different elements of the corresponding housing are mounted, such as an electronic chip and a means for closing the corresponding cavity, for example an optically transparent closing means such as a window in the case of an optical housing. In particular, the closing means is typically fixed, for example by means of an adhesive, on the side wall of each housing.

[0005] Before cutting, the projecting wall of the plate can also be used to fix several sealing means associated with housings respectively assembled in adjacent locations.

[0006] The wall is then wide enough to allow the sealing means to be fixed but narrow enough to allow the housing locations to be brought closer together, so that a larger quantity of housings can be manufactured on the plate.

[0007] However, a problem arises when the sealing means are glued to the wall before it is cut.

[0008] Indeed, a wall that is too thin does not allow the sealing means to be sufficiently spaced apart from each other so that, when the sealing means are pressed against the wall with glue between the wall and the end of the sealing means, glue overflows into the cutting areas of the wall.

[0009] And the presence of glue in the cutting areas produces defects on the edges of each housing, such as burrs, in particular when the glue used has mechanical properties different from the material of the wall, these burrs resulting from a tearing of the glue located in the cutting areas during the cutting of the wall.

[0010] Indeed, the cutting is typically preceded by a step of crosslinking the glue allowing chemical bonds to be created between the sealing means and the wall.

[0011] After formation of these chemical bonds, the glue can exhibit a certain elasticity.

[0012] The glue, due to its elasticity, can then be torn off when cutting the wall and weaken the sealing means of the respective boxes.

[0013] Furthermore, the boxes, once individualized, may have traces of glue torn off along their respective side wall.

[0014] In this regard, provision may be made to form a wider wall so as to distance the sealing means from the different cutting zones in order to prevent the glue from overflowing into the latter when fixing the sealing means.

[0015] However, by increasing the width of the walls formed on the plate, the width of the side walls of the packages after their individualization is also increased, thus making the integrated circuit packages less compact.

[0016] There is therefore a need in particular to propose a solution making it possible to avoid tearing of the glue when individualizing the boxes while obtaining compact boxes.

[0017] According to one aspect, there is provided a method of manufacturing a plurality of integrated circuit packages, comprising: - a supply of a support substrate having a mounting face and comprising a wall projecting from the mounting face and delimiting with the mounting face a matrix of cavities, each cavity comprising on the mounting face electrically conductive contact pads, the support substrate comprising under each cavity an interconnection network between the contact pads and a lower face of the support substrate, - a formation of first trenches extending partially into the wall around each cavity, - electronic chip assemblies on the mounting face of the support substrate in said cavities respectively and cooperating electrically with the corresponding contact pads, - sealing the cavities by gluing respective sealing means on an upper face of the wall between the first trenches using a suitable glue so as not to overflow into the first trenches, so as to obtain a matrix of boxes, - a formation of electrically conductive connection means under each cavity cooperating electrically with the corresponding interconnection network and - individualization of the boxes including a cutout of said wall and of the support substrate by forming in said wall and in the support substrate second trenches less wide than the first trenches, extending the first trenches to the lower face of the support substrate.

[0018] Thus, it is proposed to produce first trenches, for example by partially cutting the wall in the cutting zones, so that the wall has, after this partial cutting, a “U” shape. The “U” shape of the wall as well as the characteristics of the glue, for example the surface tension, contribute to preventing glue located on either side of the first trenches from overflowing into the first trenches, in particular in the cutting zones, when the cavities are sealed by the respective sealing means.

[0019] Furthermore, it is advantageous to achieve partial wetting of the upper face of the wall by the glue so that the glue does not overflow into the first trenches. The wetting of the glue corresponds to the behavior of the glue in contact with the upper face of the wall. We speak of total wetting when the glue spreads over the upper face and partial wetting when the glue forms a drop on this upper face. The wetting of the glue can in particular be determined by the characteristics of the glue such as the surface tension of the glue or the contact angle of the glue on the upper face of the wall. A person skilled in the art will be able to choose a suitable value for the surface tension and / or the contact angle depending on the intended application.

[0020] That being said, for information purposes, the glue typically has a sufficiently high contact angle (also referred to as "wetting angle"), for example a contact angle greater than 30°, to contribute to its non-overflow, in particular after the glue has been deposited on the wall or following the fixing of the sealing means on the wall. Furthermore, the formation of the second trenches which are narrower than the first trenches makes it possible to ensure a final cut, i.e. the cutting of the wall and the support substrate in the cutting zones in order to individualize the housings, which does not tear off the glue.

[0021] Therefore, the method according to this aspect makes it possible to perform cuts on relatively thin walls without producing defects such as torn glue so as to manufacture several compact packages having no traces of these defects.

[0022] According to one embodiment, the first trenches have a first width, the second trenches have a second width and the difference between the first width and the second width is greater than or equal to 100 μm.

[0023] Such a difference between the first width and the second width makes it possible to avoid, when forming the second trenches, cutting the wall too close to the edges of the first trenches and to guarantee as much as possible that the glue located on either side of the first trenches is not torn off during the formation of the second trenches.

[0024] In some cases, the first trenches may have a curved bottom so that the curved shape of the bottom of the trenches may extend to the edges of the first trenches which are then no longer steep enough to prevent the glue from overflowing into the first trenches.

[0025] It is therefore particularly advantageous for the first trenches to be sufficiently deep so as to have steep edges.

[0026] Thus, in this regard and according to one method of implementation, the depth of the first trenches is between 50% and 80% of the height of the wall.

[0027] According to another aspect, there is provided an integrated circuit package comprising: - a support substrate having a mounting face, - a side wall arranged on the mounting face, having an internal face and an external face, the internal face delimiting with the mounting face a cavity, the external face comprising a step extending towards the outside of the housing, - an electronic chip arranged in the cavity above the mounting face of the support substrate and electrically connected to electrically conductive contact pads located on the mounting face, - a sealing means glued by means of an adhesive to an upper face of the side wall and sealing the cavity, said adhesive not overflowing onto the external face of the side wall, and - electrically conductive connection means located on a lower face of the support substrate and in electrical cooperation with said contact pads via an interconnection network located in the support substrate.

[0028] According to one embodiment, the contact angle of the glue on the upper face of the wall is greater than 30°.

[0029] According to one embodiment, the step is located at a distance from the upper face of the side wall and has a width greater than or equal to 100 μm.

[0030] According to one embodiment, the distance is between 50% and 80% of the height of the side wall.

[0031] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:

[0032] [Fig.l] ;

[0033] [Fig.2] ;

[0034] [Fig.3] ;

[0035] [Fig.4] ;

[0036] [Fig.5] ; and

[0037] [Fig.6] schematically illustrate methods of implementation and realization of the invention.

[0038] [Fig.l] illustrates a step of providing (or obtaining) 100 a support substrate SUB according to a top view.

[0039] The support substrate SUB has an FM mounting face and comprises a RES wall projecting from the FM mounting face.

[0040] The wall is typically made of resin and has an upper face FH at a distance from the mounting face FM of the support substrate SUB.

[0041] The formation of a wall using a resin is known per se to those skilled in the art.

[0042] The RES wall delimits with the FM mounting face a matrix of ZCI cavities and serves in particular to delimit the adjacent ZCI cavities on a row or a column of the matrix.

[0043] The RES wall has ZSO cutting zones distributed along the rows and columns of the matrix and between the ZCI cavities.

[0044] [Fig.2] is a partial sectional view along line ILII of [Fig.l].

[0045] For the purpose of simplification, only some portions of the RES wall are re presented.

[0046] The RES wall has a height H of, for example, between 270 pm and 370 pm.

[0047] Each ZCI cavity comprises, in this embodiment, on the mounting face FM of electrically conductive contact pads PAD.

[0048] The support substrate SUB comprises a lower face FL opposite the mounting face FM.

[0049] Under each cavity ZCI, the support substrate SUB comprises an interconnection network INTCNX, very schematically represented and of conventional structure, between the contact pads PAD and contact pads of the lower face FL.

[0050] The INTCNX interconnection network comprises conductive tracks, typically made of copper (Cu), integrated in one or more layers of dielectric material such as resin mixed with glass fiber, of the support substrate SUB.

[0051] The support substrate SUB is therefore in this embodiment example a laminated plate.

[0052] [Fig.3] illustrates a step 101 of forming first TRC1 trenches in the RES wall.

[0053] The formation of the first trenches TRC1 may comprise a partial cutting of the wall RES along the cutting zones ZSO, so that the first trenches TRC1 extend partially into the wall RES around each cavity ZCI.

[0054] More particularly, the first trenches TRC1 here have a depth DTRC1 between 50% and 80% of the height H of the RES wall.

[0055] They have a first width LTRC1 comprised in this embodiment example between 350 pm and 450 pm.

[0056] The first trenches TRC1 are thus sufficiently deep to prevent the curved shape of the bottom of the trenches from extending to the edges of the first trenches TRC1.

[0057] Therefore, the first TRC1 trenches advantageously have relatively steep edges.

[0058] The RES wall, in which the first trenches TRC1 are respectively formed, then has a “U” shape. The “U” shape of the RES wall makes it possible to define, on the upper face FH of the RES wall, a surface on each side of the cutting zone ZSO between the cavities ZCI.

[0059] More particularly, the first trenches TRC1 can be formed for example by a SCI cutting blade. Other cutting means are however possible, for example a laser.

[0060] [Fig.4] illustrates a step 102 of assembling packages on the support substrate SUB.

[0061] For the purposes of simplification, only two adjacent boxes BT1 and BT2 have been shown.

[0062] The assembly 102 notably comprises a step of mounting electronic chips CHP on the FM mounting face of the support substrate SUB in the cavities ZCI respectively.

[0063] The CHP electronic chips electrically cooperate with the corresponding contact pads PAD in each ZCI cavity.

[0064] For example, the CHP electronic chips can be fixed on the FM mounting face between the PAD contact pads by GL1 glue and be electrically connected to the PAD contact pads by WB bonding wires.

[0065] According to another possible variant, the CHP electronic chips may comprise solder balls soldered to the PAD contact pads which would then be located under the CHP electronic chips.

[0066] The solder balls would be embedded in a layer of an underfill material (known to those skilled in the art by the English term “underfill”) allowing the CHP electronic chips to be mechanically fixed to the FM mounting face.

[0067] The CHP electronic chips are then electrically connected to the PAD contact pads via the solder balls.

[0068] The assembly 102 also comprises a step of closing the cavities ZCI by respective closing means CAP.

[0069] The CAP sealing means are fixed on the RES wall between the first trenches TRC1 so as to obtain a matrix of BT1, BT2 boxes.

[0070] In the case of optical housings, the CAP closure means may be an optically transparent closure means such as a window for example.

[0071] Furthermore, the sealing of each cavity ZCI comprises bonding the sealing means CAP to an upper face FH of the wall RES. More particularly, the bonding of the sealing means CAP positioned above the corresponding electronic chip CHP is carried out by means of a glue GL2 arranged between an end zone of the fixing face FCAP of the sealing means CAP and the upper face FH of the wall RES.

[0072] The GL2 adhesive may be a relatively soft adhesive, for example an acrylate type adhesive capable of crosslinking when exposed to ultraviolet (UV) radiation and during thermal annealing. The GL2 adhesive typically has mechanical properties different from the RES wall material, such as resin.

[0073] According to a first possibility, the bonding of the sealing means CAP comprises a step of depositing the glue GL2 on the upper face FH of the wall RES, in particular on the surface located on either side of the first trenches TRC1.

[0074] The GL2 adhesive located on the upper face FH of the RES wall typically has a contact angle 0 greater than 30°. The contact angle 0 of the GL2 adhesive corresponds more particularly to the angle formed between the upper face FH of the RES wall and the tangent to the surface of the GL2 adhesive at the point of contact with the upper face FH. The contact angle 0 of the GL2 adhesive makes it possible to achieve partial wetting of the upper face FH by the GL2 adhesive and therefore makes it possible to minimize the surface over which the GL2 adhesive spreads, in particular when the edges of the first trenches TRC1 at the end of this surface are abrupt.

[0075] The sealing means CAP is then pressed against the upper face FH of the wall RES, so that the glue GL2 spreads over the upper face FH without overflowing into the first trenches TRC1 and adheres to the fixing face FCAP of the sealing means CAP.

[0076] As an alternative to this first possibility, the glue GL2 can also be deposited on the end zone of the fixing face FCAP of the sealing means CAP so that, when the sealing means CAP is pressed against the upper face FH of the wall RES, the glue GL2 spreads over the upper face FH, in particular on the surface located on either side of the first trenches TRC1, without overflowing into the first trenches TRC1 and adheres to the upper face FH.

[0077] In particular, whatever the alternative used, the pressure applied to the sealing means CAP to press it against the upper face FH is sufficiently high so that the glue GL2 adheres to the fixing face FCAP and to this upper face. FH.

[0078] This pressure is, moreover, sufficiently low to prevent the GL2 glue from overflowing into the first TRC1 trenches, taking into consideration the surface tension of the GL2 glue or its contact angle.

[0079] This pressure also depends on the counter pressure inside the cavity and the desired thickness of glue.

[0080] A person skilled in the art will know how to adjust this pressure according to all these parameters to obtain both suitable adhesion and non-overflow of the glue into the first TRC1 trenches.

[0081] By way of example, the pressure applied to the sealing means CAP is chosen so that the thickness of the glue GL2 between the upper face FH and the fixing face FCAP of the sealing means CAP after fixing the sealing means CAP is between 100 μm and 250 μm.

[0082] The GL2 glue therefore typically has a contact angle 0 sufficiently high to contribute to the non-overflow of the GL2 glue, after deposition of the GL2 glue on the RES wall and following the fixing of the CAP sealing means to the RES wall.

[0083] The “U” shape of the RES wall, as well as the characteristics of the GL2 glue, for example the surface tension or the contact angle, make it possible to prevent the GL2 glue located on either side of the first TRC1 trenches from overflowing into the first TRC1 trenches, in particular in the ZSO cutting zones in which the final cutting is carried out as described below in relation to [Fig.5].

[0084] It is thus possible to obtain, after the assembly step 102, integrated circuit packages BT1 and BT2 produced on the same support substrate SUB and delimited by the first trenches TRC1 devoid of glue GL2.

[0085] [Fig.5] illustrates a step of forming electrically conductive connection means BP and a step 103 of individualizing the boxes BT1 and BT2.

[0086] The electrically conductive connection means BP, for example solder balls, are formed on the lower face FL of the support substrate SUB, below each cavity ZCI.

[0087] The connection means BP cooperate electrically with the corresponding interconnection network INTCNX via the contact pads located on the lower face FL of the support substrate SUB and allow, in particular, the respective electronic chips CHP to be electrically connected to a printed circuit board.

[0088] The step 103 of individualizing the BT1 and BT2 packages comprises cutting the RES wall and the support substrate SUB by forming second TRC2 trenches in said RES wall and the support substrate SUB.

[0089] More particularly, the second trenches TRC2 can be formed by example by an SC2 cutting blade different from the SCI cutting blade for example. Here again other cutting means can be considered, for example a laser.

[0090] Whatever the cutting means used, the second trenches TRC2 are less wide than the first trenches TRC1 and extend the first trenches TRC1 to the lower face FL of the support substrate SUB.

[0091] In particular, the second trenches TRC2 have a second width LTRC2 of between 200 pm and 300 pm.

[0092] The formation of the second trenches TRC2 less wide than the first trenches TRC1 makes it possible to ensure a final cut, i.e. the cutting of said wall RES and the support substrate SUB, which does not tear off the glue GL2.

[0093] Furthermore, the difference LSTP between the first width LTRC1 and the second width LTRC2 is advantageously greater than or equal to 100 pm.

[0094] Such a difference between the first width LTRC1 and the second width LTRC2 makes it possible to avoid cutting too close to the edges of the first trenches TRC1 and to guarantee as much as possible that the glue GL2 located on either side of the first trenches TRC1 is not torn off during the formation of the second trenches TRC2.

[0095] Therefore, the method allows as much as possible to make cuts on relatively thin RES walls without producing defects such as torn GL2 glue so as to manufacture several compact BT1 and BT2 integrated circuit packages not showing traces of these defects.

[0096] [Fig.6] schematically illustrates a sectional view of an example of a BT box according to one aspect of the invention and for example obtained by the method described previously in relation to figures 1 to 5.

[0097] The BT package comprises a support substrate SUB, an electronic chip CHP and a sealing means CAP. The support substrate SUB has a mounting face FM and a lower face FL opposite the mounting face FM.

[0098] The BT housing further comprises a RES side wall arranged on the FM mounting face.

[0099] The side wall RES has an internal face FINT, an external face FEXT and an upper face FH at a distance from the mounting face FM.

[0100] The internal face FINT delimits with the mounting face FM a cavity ZCI and the external face FEXT comprises a step STP.

[0101] The step STP extends towards the outside of the BT box and is located at a distance DTRC1 from the upper face FH of the side wall RES.

[0102] The distance DTRC1 is between 50% and 80% of the height H of the side wall RES.

[0103] Furthermore, the STP step has an LSTP width greater than or equal to 100 pm.

[0104] The CHP electronic chip is arranged in the ZCI cavity above the face of FM mounting of the SUB support substrate.

[0105] The electronic chip CHP is electrically connected to electrically conductive contact pads PAD located on the mounting face FM.

[0106] In particular, the PAD contact pads are located around the CHP electronic chip which is fixed on the FM mounting face by GL1 glue and which is electrically connected to the PAD contact pads by WB connecting wires.

[0107] According to a possible variant, the PAD contact pads may be located under the CHP electronic chip. The CHP electronic chip may then comprise solder balls fixed to the PAD contact pads making it possible to electrically connect the CHP chip to the PAD contact pads. The solder balls of the CHP electronic chip, according to this variant, are embedded in a layer of underfill material.

[0108] The CAP sealing means is glued using GL2 glue to the upper face FH of the RES side wall and seals the ZCI cavity.

[0109] The CAP closure means may be a transparent closure means such as a window in the case of an optical housing.

[0110] In particular, the sealing means CAP comprises a fixing face FC AP having an end zone glued to the upper face FH of the side wall RES, by the glue GL2.

[0111] The GL2 glue located on the upper face FH of the RES wall, typically has a contact angle 0 greater than 30° and does not overflow onto the external face FEXT of the RES side wall.

[0112] Furthermore, the integrated circuit package BT comprises electrically conductive connection means BP, such as solder balls. The connection means BP are located on the lower face FL of the support substrate SUB and are in electrical cooperation with the contact pads PAD via an interconnection network INTCNX located in the support substrate SUB.

Claims

1.

2.

3. Claims Method of manufacturing several integrated circuit packages (BT), comprising: - a supply of a support substrate (SUB) having a mounting face (FM) and comprising a wall (RES) projecting from the mounting face (FM) and delimiting with the mounting face (FM) a matrix of cavities (ZCI), each cavity comprising on the mounting face (FM) electrically conductive contact pads (PAD), the support substrate (SUB) comprising under each cavity an interconnection network (INTCNX) between the contact pads (PAD) and a lower face (FL) of the support substrate (SUB), - a formation of first trenches (TRC1) extending partially into the wall (RES) around each cavity (ZCI), - electronic chip assemblies (CHP) on the mounting face (FM) of the support substrate (SUB) in said cavities (ZCI) respectively and electrically cooperating with the corresponding contact pads (PAD), - sealing of the cavities (ZCI) by gluing respective sealing means (CAP) on an upper face (FH) of the wall (RES) between the first trenches (TRC1) using a glue (GL2) suitable for not overflowing into the first trenches (TRC1), so as to obtain a matrix of boxes, - a formation of electrically conductive connection means (BP) under each cavity (ZCI) cooperating electrically with the corresponding interconnection network (INTCNX) and - an individualization of the housings (BT) comprising a cutting of said wall (RES) and of the support substrate (SUB) by a formation in said wall (RES) and in the support substrate (SUB) of second trenches (TRC2) less wide than the first trenches (TRC1), extending the first trenches (TRC1) to the lower face (FL) of the support substrate (SUB). Method according to claim 1, in which the contact angle (0) of the glue (GL2) on the upper face (FH) of the wall (RES) is greater than 30°. Method according to one of claims 1 or 2, in which the first trenches (TRC1) have a first width (LTRC1), the second trenches (TRC2) have a second width (LTRC2) and the difference (LSTP) between the first width and the second width is greater than or equal to 100 pm.

4. Method according to one of the preceding claims, in which the depth (DTRC1) of the first trenches (TRC1) is between 50% and 80% of the height (H) of the wall (RES).

5. Integrated circuit package (BT) comprising: - a support substrate (SUB) having a mounting face (FM), - a side wall (RES) arranged on the mounting face (FM), having an internal face (FINT) and an external face (FEXT), the internal face (FINT) delimiting with the mounting face (FM) a cavity (ZCI), the external face (FEXT) comprising a step (STP) extending towards the outside of the package (BT), - an electronic chip (CHP) arranged in the cavity (ZCI) on the mounting face (FM) of the support substrate (SUB) and cooperating electrically with electrically conductive contact pads (PAD) located on the mounting face (FM), - a sealing means (CAP), bonded by means of an adhesive (GL2), on an upper face (FH) of the side wall (RES) and sealing the cavity (ZCI), said adhesive (GL2) not extending onto the external face (FEXT) of the side wall (RES),and - electrically conductive connection means (BP) located under the cavity on a lower face (FL) of the support substrate (SUB) and in electrical cooperation with said contact pads (PAD) via an interconnection network (INTCNX) located under the cavity between the contact pads (PAD) and the lower face (FL) of the support substrate (SUB).,

6. Housing according to claim 5, in which the contact angle (0) of the glue (GL2) on the upper face (FH) of the wall (RES) is greater than 30°.

7. Housing according to one of claims 5 or 6, in which the step (STP) is located at a distance (DTRC1) from the upper face (FH) of the side wall (RES) and has a width (LSTP) greater than or equal to 100 pm.

8. Housing according to one of claims 5 to 7, in which the distance (DTRC1) is between 50% and 80% of the height (H) of the side wall (RES)

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