Improved method for realizing the source and drain of doped transistors
Laser thermal annealing with nanosecond pulses and explosive recrystallization addresses doping challenges in transistors by ensuring uniform doping and reducing thermal impact, suitable for thin layers and 3D circuits.
Patent Information
- Application Number
- FR2022013950
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-12-20
- Publication Date
- 2026-02-20
- Estimated Expiration
- 2042-12-20
AI Technical Summary
Existing methods for doping source and drain regions in transistors face challenges such as high thermal budgets, difficulty in creating uniform amorphous regions, and contact resistance issues, especially in thin semiconductor layers.
A method involving laser thermal annealing with nanosecond pulses is used to amorphize and dope semiconductor regions, followed by explosive recrystallization, allowing simultaneous activation of dopants without a crystalline seed, thereby improving doping uniformity and reducing thermal impact.
This approach achieves uniform doping throughout the semiconductor regions' thickness, reducing thermal budget and contact resistance, suitable for thin layers and compatible with 3D circuit fabrication.
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Abstract
Description
Title of the invention: Improved method for implementing the source and drain of doped transistors
[0001] TECHNICAL FIELD AND PRIOR TECHNOLOGY
[0002] The present application relates to the field of transistor manufacturing processes, and more particularly to that of the formation of enhanced doped source and drain semiconductor regions.
[0003] In transistor manufacturing processes, doping the source and drain regions presents certain difficulties. First, the activation of dopants generally requires a high temperature.
[0004] In addition, it is generally sought to extend the doped regions by carrying out doping under insulating spacers in order to create so-called "extension" zones of the source and the drain.
[0005] Regarding the thermal budget problem, one solution is to activate the dopants at low temperature during a solid-phase epitaxial regrowth (SPER) step of amorphous semiconductor regions containing dopants. The SPER technique promotes the recrystallization of a solid with a reduced thermal barrier. This technique requires the presence of a crystalline layer to serve as a seed for recrystallization.
[0006] With such a technique, amorphous silicon (a-Si) can, for example, grow into a crystal from crystal seeds at low temperatures, for example on the order of 500°C. This SPER temperature can even be further reduced with the presence of dopants.
[0007] Thus, one method for creating doped source and drain regions consists of rendering upper areas of semiconductor regions amorphous and retaining an underlying crystalline portion to trigger SPER recrystallization. Dopants are then implanted, at least in the amorphous region. During the recrystallization process, dopant activation is implemented.
[0008] One disadvantage of this method is that an underlying undoped crystalline part is retained, which can induce a contact resistance between the channel and the source drain regions that is all the more penalizing as the thicknesses involved are small.
[0009] Another disadvantage of such a method is that for very thin semiconductor layers, for example less than 10 nm, it proves difficult to make the upper part of these layers amorphous while keeping in the lower portion a crystal seed of sufficient thickness.
[0010] Moreover, the lower crystalline part retained is generally not uniform in terms of thickness, which can lead to variations in resistance, in particular significant access resistances from one transistor to another over the entire surface of the support on which these transistors are made.
[0011] The problem arises of finding a new method for manufacturing transistors that is improved with regard to the disadvantages stated above. Description of the invention
[0012] An object of the invention is to propose a method for making a microelectronic device for making at least one transistor having source and drain regions with improved doping, in particular over their entire thickness, while limiting the thermal budget used.
[0013] One embodiment of the present invention provides a method for producing a transistor comprising the following steps:
[0014] - provided on a support having a surface semiconductor layer and resting on an insulating layer: at least one transistor gate block arranged on the surface layer, insulating spacers on either side of this gate block, and so-called raised semiconductor regions resting on the surface semiconductor layer on either side of this gate block and the insulating spacers, then,
[0015] - to render amorphous the raised semiconductor regions and portions of the superficial semiconductor layer located beneath these raised semiconductor regions, extending throughout their thickness and reaching the insulating layer,
[0016] - doping the raised semiconductor regions and portions of the semiconductor layer surface conductive
[0017] then,
[0018] - perform at least one laser thermal annealing using one or more im laser pulses so as to achieve recrystallization of raised regions and portions of the surface semiconductor layer while simultaneously activating dopants in these regions and portions.
[0019] Here, complete amorphization is achieved throughout the entire thickness of the semiconductor regions and portions of the surface semiconductor layer in order to perform doping throughout the entire thickness of the semiconductor regions and portions of the surface semiconductor layer. Doping and amorphization can be carried out simultaneously by implantation.
[0020] Laser annealing has the advantage of allowing activation of dopants without necessarily having previously preserved a crystalline thickness and while limiting the thermal budget used.
[0021] In particular, a nanosecond laser annealing with one or more pulses is used of duration less than 1 ps.
[0022] Laser thermal annealing can thus be carried out using a laser with a wavelength between 200 nm and 600 nm and advantageously between 200 and 400 nm, by emitting one or more successive laser pulses, with a pulse duration of less than one microsecond and preferably between 1 ns and 1000 ns, advantageously between 20 ns and 300 ns.
[0023] Laser thermal annealing is preferably carried out in an "explosive" recrystallization regime in which the raised semiconductor regions and portions are transformed into polycrystalline material.
[0024] A person skilled in the art would tend to want to produce single-crystal source and drain semiconductor regions, but the inventors have found experimentally, surprisingly, that raised semiconductor regions and recrystallized portions according to such a regime make it possible to produce source and drain regions with low resistance.
[0025] According to one embodiment, the step of rendering the raised semiconductor regions and portions amorphous can be carried out by ion implantation using an ion beam inclined with respect to a normal to a principal plane of the substrate, so as to achieve amorphization of areas of the surface layer that extend under the spacers. This contributes to improved doping of the extension areas under the spacers.
[0026] Advantageously, the process may further comprise the steps of:
[0027] - grid block formation,
[0028] - formation of spacers on either side of the grid block,
[0029] - formation of raised semiconductor regions on either side of the spacers.
[0030] The method may then further comprise, after formation of the grid block and prior to the formation of the spacers:
[0031] - doping of so-called extension zones of the surface semiconductor layer located on either side of the grid block, the spacers are formed opposite the extension areas.
[0032] Advantageously, the doping of the extension zones in the surface semiconductor layer on either side of the gate block comprises steps consisting of:
[0033] - to render amorphous and dope an upper part of the surface layer while retaining a lower crystalline zone of the surface layer in contact with the insulating layer,
[0034] - perform an annealing process so as to recrystallize the upper part of the super layer ficielle.
[0035] According to one possible embodiment, after the formation of the insulating spacers and prior to the amorphization of the raised semiconductor regions and portions of the surface semiconductor layer located beneath these semiconductor regions:
[0036] - to form by epitaxy the raised semiconductor regions on the upper part recrystallized from the surface layer.
[0037] According to an advantageous embodiment, after laser thermal annealing, the process can include a step of forming regions based on a compound of metallic material and semiconductor material in the raised semiconductor regions.
[0038] According to a first possibility, prior to laser thermal annealing, at least one layer of metallic material can be deposited so as to cover the raised semiconductor regions, the laser thermal annealing then being adapted to form the regions based on a composite of metallic material and semiconductor material in the raised semiconductor regions.
[0039] According to a second possibility, after laser thermal annealing, the process may include steps consisting of:
[0040] - to render amorphous the upper parts of the raised semiconductor regions, Then
[0041] - deposit at least one layer of metallic material so as to cover the raised semiconductor regions, and perform annealing to form regions based on a compound of metallic material and semiconductor material in the upper parts.
[0042] The support for the semiconducting surface layer can be a semiconductor-on-insulator type substrate such as an SOI substrate (for "Silicon On Insulator" or "Silicon on Insulator") or a support having one or more components of a first level of components formed in an underlying semiconductor layer.
[0043] Thus, the process is particularly well-suited to the fabrication of 3D devices or circuits with several superimposed semiconductor layers and several levels of components made within these layers. In particular, the ability to use a reduced thermal budget to form raised source and drain regions makes it especially compatible with the implementation of 3D circuits or devices, i.e., those fabricated on several levels of components formed in distinct semiconductor layers. Brief description of the drawings
[0044] The present invention will be better understood on the basis of the following description and the accompanying drawings in which:
[0045] [Fig.1A]
[0046] [Fig.1B]
[0047] [Fig.1C]
[0048] [Fig.1D]
[0049] [Fig. 1E] serve to illustrate a method of making a transistor with source and drain semiconductor regions doped over their entire thickness;
[0050] [Fig.2] serves to illustrate an alternative embodiment in which additionally metal and semiconductor alloy regions in doped semiconductor regions.
[0051] [Fig.3] serves to illustrate an alternative embodiment in which laser annealing is carried out after doping of the semiconductor regions then a step of deposition of metallic material in order to combine an activation of dopants with a silicification of the source and drain semiconductor regions;
[0052] [Fig.4A]
[0053] [Fig.4B]
[0054] [Fig.4C]
[0055] [Fig.4D]
[0056] [Fig.4E]
[0057] [Fig.4F] serve to illustrate another particular embodiment in which extension zones are doped before the raised parts of source and drain regions are formed and doped.
[0058] [Fig.5A]
[0059] [Fig.5B]
[0060] [Fig.5C]
[0061] [Fig.5D]
[0062] [Fig.5E]
[0063] [Fig.5F]
[0064] [Fig.5G]
[0065] [Fig.5H]
[0066] [Fig.51] serve to illustrate another example of a particular embodiment for which one performs a doping of areas of a superficial semiconductor layer before forming raised parts of the source and drain regions and making these areas and raised parts amorphous throughout their thickness.
[0067] [Fig.6] serves to illustrate a particular embodiment in which the support to the starting point for the process is already equipped with a level of components formed in an underlying semiconductor layer.
[0068] In addition, in the description below, terms which depend on the orientation of a structure such as "front", "upper", "rear", "lower", "lateral", apply considering that the structure is oriented in the manner illustrated in the figures.
[0069] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
[0070] A possible starting structure for carrying out a process according to the invention and implemented for the manufacture of at least one transistor is given in [Fig.1A].
[0071] This structure includes a support 100 having an insulating layer 11, for example of SiO2, and commonly called BOX (“buried-oxide”), the insulating layer 11 being itself coated with a superficial semiconducting layer 12 in which one or more transistors are intended to be formed.
[0072] The superficial semiconductor layer 12, for example made of silicon, is provided with a thickness which can be for example between 5 nm and 100 nm, advantageously between 5 and 30 nm.
[0073] The insulating layer 11 can be provided with a thickness of, for example, between 15 nm and 200 nm.
[0074] A particular embodiment provides for an insulating layer 11 of silicon oxide of 145 nm and a surface layer 12 and a silicon layer of the order of 23 nm or 30 nm thick.
[0075] The support 100 on which the insulating layer 11 rests is, in this particular embodiment, a semiconductor layer 10 supporting a semiconductor-on-insulator substrate, for example of the SOI type (SOI for "Silicon On Insulator" or "Silicon on Insulator").
[0076] The transistor(s) formed may be provided in FDSOI technology (for “Fully Depleted Silicon On Insulator” or “silicon on totally depleted insulator”).
[0077] In the illustrated embodiment, the structure has a transistor gate block 25. This block 25 is formed here of a gate dielectric region 21, for example made of SiO2 or HfO2, surmounted by a gate region 22 formed of one or more layers of gate material, for example based on polysilicon, TiN, or W, or a stack of at least several of these materials. Spacers 33 are formed on either side of the gate block 25. These spacers 33 can, for example, be based on SiN, SiBCN, or SiOCN.
[0078] Semiconductor regions 42 referred to as "raised", for example in silicon, are here formed on either side of the gate block 25, typically by epitaxy.
[0079] Next, an amorphization of the semiconductor regions 42 and of the portions 12a of the surface semiconductor layer 12 is carried out. This amorphization is typically implemented by means of at least one ion implantation.
[0080] In the example illustrated in [Fig. 1B], an inclined amorphization implant is performed. This uses an implanting beam that makes a non-zero angle α with respect to a normal n to a principal plane of the support 100 (i.e., a plane of the support parallel to the plane [O; x; y] of an orthogonal coordinate system [O; x; y; z] given in [Fig. 1B]). Preferably, the amorphization implant(s) are performed here after forming insulating spacers 33 on either side of grid block 25.
[0081] The amorphization is advantageously carried out here over the entire thickness e (e = e0+ ej of the semiconductor regions 42 and of the semiconductor layer 12. Thus, the raised semiconductor regions 42 of thickness ei are made entirely amorphous.
[0082] The portions 12a of the superficial semiconducting layer 12 e0 are also made amorphous over their entire thickness e0 and thus reach the insulating layer 11 so as to be in contact with the latter.
[0083] Due to the inclined beam implantation, the amorphous portions 12a of the surface semiconductor layer may include areas 12c which extend under the spacers 33.
[0084] To achieve amorphization, an implantation of a neutral and non-doping species, for example Silicon or Germanium ions, with dose and energy conditions determined by simulation and experimental verification by TEM (transmission electron microscopy) imaging, can be implemented. Simulation tools based on a Monte Carlo method, in particular of the TRIM type (TRIM for "TRansport of Ions in Matter", i.e., Transport of ions in matter, and / or KMC (for "kinetic Monte Carlo", i.e., kinetic Monte Carlo method).
[0085] For example, an implantation of Ge ions with a dose of 6xl014ions*cm2 at an energy of 9 keV can make it possible to obtain an amorphous thickness of the order of 15 nm of silicon.
[0086] In particular the case of an amorphization carried out using a neutral species, it is then possible ([Fig.lC]) to carry out a doping of the parts of the semiconductor layer 12 on either side of the gate block 25 and in particular a doping of extension zones located on either side of the gate opposite the insulating spacers 33.
[0087] Thus, in the embodiment example illustrated in [Fig.1C], a doping implantation is carried out using an inclined beam making a non-zero angle a' with respect to a normal n to a principal plane of the support 100 in order in particular to carry out doping of the portions 12a made amorphous and of the zones 12c located under the insulating spacers 33.
[0088] According to one possible implementation, this doping implantation can be provided at a low dose, that is to say typically less than 1.0x1014ions*cm2 and advantageously less than 5.0x1013ions*cm2.
[0089] Next, another doping implantation ([Fig.1D]) can be carried out, this time at a higher dose and using a straight beam, i.e. parallel or substantially parallel to a normal n to a principal plane of the support 100. Doping is then carried out on the raised and amorphous regions 42, in particular over their entire thickness.
[0090] A breakdown of doping into a low-dose, inclined implantation and into a Another implantation method, with a higher dose and a straight line (i.e., parallel to a normal to the substrate), can avoid doping too close to a region 121 of the semiconductor layer where the transistor channel is located. Alternatively, these two doping steps can be combined.
[0091] The doping step(s) on raised semiconductor regions 42 and portions 12a made amorphous over their entire thickness promotes the achievement of doping of regions 42 and portions 12a over their entire thickness.
[0092] A laser annealing L is then carried out ([Fig. 1E]) so as to achieve a recrystallization of the raised semiconductor regions 42 and of the portions 12a of the superficial semiconductor layer 12.
[0093] Laser treatment allows for rapid heating to high temperatures and rapid cooling of the structure once laser exposure has ceased. Laser recrystallization can be implemented in particular by subjecting regions 42 and portions 12a to one or more pulses of a laser beam L, and in particular of a so-called "nanosecond" laser, i.e. with a pulse duration typically less than 1 microsecond.
[0094] The use of a laser operating in pulsed mode makes it possible to limit the thermal budget, while avoiding an overall temperature rise that is too great for the rest of the structure.
[0095] The wavelength of the laser L, the pulse duration of the laser beam and preferably the energy density of the laser beam are chosen according to, in particular, the thickness of the surface layer and the raised regions 42 as well as the reflectivity of the underlying layers.
[0096] Preferably, the pulse duration and energy density of the laser are chosen so as to carry out recrystallization in a so-called "explosive recrystallization" regime. Such a regime is described, for example, in the document "Melting Temperature and Explosive Crystallization of Amorphous Silicon during Pulsed Laser Irradiation," Thompson et al., 1984. The laser thermal annealing is specifically designed to transform these portions 12a and regions 42 into polycrystalline material, particularly into polysilicon when these portions 12a and regions 42 are in amorphous silicon.
[0097] Typically, a laser with a wavelength between 200 nm and 600 nm, and in particular between 200 nm and 400 nm, is planned to be used.
[0098] The duration of the, or each, pulse of the laser beam can be, for example, between 1 ns and 1000 ns, and preferably between 10 ns and 500 ns.
[0099] At a given wavelength of the laser, the energy density of the chosen laser beam depends on the reflectivity of the stacking.
[0100] According to a particular embodiment with a silicon layer 12 of the order With 12 nm and 42 raised silicon regions with a maximum thickness between 20 and 30 nm, an energy density of between 0.5 and 1.0 J / cm2 can be predicted.
[0101] This range can be extended and / or modified depending on the stacking of the surface layer 12 and the regions 42 and the doses of dopants used. Those skilled in the art can use simulation tools such as COMSOL Multiphysics or LIAB (LASSE Innovation Application Booster) and physical characterization tools using imaging such as TEM (Transmission Electron Microscopy) and ellipsometer to determine the precise conditions according to the chosen stacking.
[0102] Since portions 12a and raised regions 42 are doped, laser heat treatment simultaneously enables activation of dopants.
[0103] Explosive recrystallization with a nanosecond laser has the advantage of being able to be implemented even when the regions to be recrystallized are entirely amorphous and, as in the embodiment described above, no underlying crystalline layer is provided to serve as a starting zone for a recrystallization front.
[0104] In addition to the aforementioned advantages, the implementation of recrystallization with a nanosecond laser operating in pulsed mode promotes the conservation of the shape of the raised semiconductor regions 42.
[0105] To help preserve the shape of the raised semiconductor regions 42 during activation annealing, in a particular optional embodiment, these regions can be coated with a transparent encapsulating layer prior to exposure to the nanosecond laser. Such an encapsulating layer then acts as a mold and preserves the shape of the raised semiconductor regions 42 despite possible partial melting of an upper portion of these regions.
[0106] According to one possible embodiment, after recrystallization of the portions 12a and raised regions 42, areas 155 of metal and semiconductor alloy can then be formed in the raised semiconductor regions 42 ([Fig.2]).
[0107] This step is preferably carried out at a temperature below 600°C and advantageously below 500°C. For this, a sputtering process can be used, for example, to deposit a metallic material followed by heat treatment. A particular example of such a process, when the raised regions 42 are made of silicon, involves silicification by forming zones 155 of a metal-silicon alloy, for example NiPtSi.
[0108] As an alternative to the example of the process described above, amorphization and doping steps can be combined by implementing an amorphization implantation using a doping species.
[0109] For example, implantation with an appropriate implantation energy and arsenic or phosphorus can be implemented to achieve N-type doping concurrently with amorphization of the raised regions 42 and the surface semiconductor layer 12. Another embodiment involves implantation of BF2 to achieve amorphization and concomitant P-type doping. For phosphorus implantation, the following conditions can be used, for example: dose = 5E14 at / cm2, energy = 100V, to achieve amorphization of approximately 16 nm. For similar doses and implantation energies, with BF2 ions, an amorphization depth on the order of 1 Inm can be obtained.
[0110] According to an alternative embodiment illustrated in [Fig. 3], a laser annealing as described above can be performed after a metal deposition step to form metal-semiconductor alloy zones 155 to recrystallize regions 42 and portions 12a. In this case, at least part of the recrystallization annealing can be combined to produce metal-semiconductor alloy zones. This can also allow the formation of metal-semiconductor alloy zones from a material free of crystalline defects.
[0111] According to another embodiment, the doping of the surface semiconductor layer 12 and the raised semiconductor regions can be carried out in several steps.
[0112] In particular, it is possible to plan to boost the extension zones after the formation of the grid block 25 but prior to the realization of spacers.
[0113] Thus, in the embodiment example illustrated in [Fig.4A], at least a first doping implantation is carried out for this purpose, preferably with a beam not inclined with respect to a normal to the main plane of the support.
[0114] Then ([Fig. 4B]), the spacers 33 are formed. This can be achieved, for example, by depositing an insulating layer, for example silicon nitride, followed by etching, for example dry etching using a plasma. Before proceeding with this etching, a photolithography step is typically carried out to protect the areas that are not to be etched.
[0115] Next, on either side of the spacers 33, the semiconducting regions 42 raised by epitaxy on the superficial semiconducting layer 12 are formed ([Fig.4C]).
[0116] Then, the amorphization ([Fig.4D]) of the regions 42 and portions of the superficial semiconductor layer 12a is carried out and then ([Fig.4E]) doping of these regions 42 is performed. These amorphization and doping steps can, again, be combined and carried out in a single implantation.
[0117] Recrystallization and activation of dopants are then carried out by laser annealing L, in particular a nanosecond laser and preferably by implementing the regime explosive recrystallization as described previously ([Fig.4F]).
[0118] According to another variant of the example of process described above, the doping implantation(s) of the surface semiconductor layer 12 are carried out and aimed at carrying out a doping of extension zones 122 this time by doping and rendering amorphous concomitantly an upper part 123 of the surface semiconductor layer.
[0119] In this case, a lower crystalline and non-amorphized region 124 of the surface semiconductor layer 12 is preferably preserved beneath this upper, amorphous, and doped portion 123. In the particular embodiment illustrated in [Fig. 5A], this step is performed before forming spacers.
[0120] The preserved crystalline zone 124 can have a thickness ei24 of for example between 2 and lOnm for a semiconductor layer of thickness between 5 and 30 nm.
[0121] Once the implantation of the dopants has been carried out, at least one heat treatment is performed so as to carry out a recrystallization anneal of the upper part 123 ( [Fig.5B]).
[0122] The lower zone 124 is then used as the starting zone of a recrystallization front. A solid phase epitaxial regrowth (SPER) process of the amorphous semiconductor material in contact with the crystalline semiconductor material is in particular carried out at a temperature preferably below 500°C and which may be for example between 400°C and 500°C.
[0123] Then ([Fig.5C]), the spacers 33 are formed, for example by deposition of a layer, for example, of thickness between 1 and 10 nm of silicon nitride and then etching.
[0124] Elevated semiconductor regions 42 ([Fig.5D]) are then formed by epitaxy.
[0125] A complete amorphization ([Fig.5E]) is then carried out by implanting these regions 42 and portions 12a of the superficial semiconducting layer 12 arranged on either side of the spacers 33 and extending over the entire thickness eO of this superficial layer 12 until reaching the underlying insulating layer 10.
[0126] Next ([Fig.5F]), a doping implantation can be performed so as to achieve a doping preferably over the entire thickness of regions 42 and portions 12a of the superficial semiconductor layer 12.
[0127] Then, recrystallization and activation of dopants is carried out by exposure to an L laser as described previously, in particular using a nanosecond laser and typically in such a way as to transform into polycrystalline material, in particular polysilicon, the raised regions 42 as well as the portions 12a of the surface semiconductor layer 12 ([Fig.5G]).
[0128] According to optional steps, a further amorphization ([Fig. 5H]) can then be carried out, this time of an upper portion 148 of the raised semiconductor regions 42. This amorphization is implemented using an implantation which can optionally be implemented using a doping agent.
[0129] Then ([Fig.51]), zones 155 of metal and semiconductor alloy are formed, in particularly in the upper part 148 of the raised 42 semiconductor regions. This is achieved by depositing a metal, for example Nickel or a Nickel and Platinum alloy, followed by annealing, for example at a temperature between 200 and 400°C.
[0130] According to another embodiment, it is possible to implement a process as described above on a support different from the substrate described above.
[0131] In particular, the starting structure of the process can be such as in the particular embodiment example of [Fig.6], where the surface semiconductor layer 12 and the insulating layer 11 rest here on a support 100' already comprising a first level Ni of components, for example transistors.
[0132] Thus, one or more Ti transistors of a first level Ni of components are, in the illustrated embodiment example, formed partly in an underlying semiconductor layer 2.
[0133] The first-level Nis Ti transistors are covered with one or more stages of metallic interconnections formed in one or more insulating layers, typically a stack of 5 insulating layers, for example in SiO2. The stack of 5 insulating layers is provided or coated with the insulating layer 11 of BOX, this insulating layer 11 being itself coated with the surface semiconductor layer 12.
[0134] The process described above can then be applied to fabricate one or more second-level transistors. An activation and recrystallization annealing process using a nanosecond laser, as described above and adapted in particular for performing recrystallization in an explosive regime as mentioned above, is then especially well-suited to this type of structure. In particular, it allows for doping of the source and drain regions of second-level transistors without impacting and risking damage to the first-level components.
Claims
Demands
1. A method for producing a transistor comprising the following steps: - providing on a support (100, 100') having a surface semiconductor layer (12) and resting on an insulating layer (11): at least one transistor gate block (25) arranged on the surface layer (12), insulating spacers (33) surrounding this gate block (25), and raised semiconductor regions (42) resting on the surface semiconductor layer (12) on either side of this gate block (25) and the insulating spacers (33), - rendering amorphous the raised semiconductor regions (42) and portions (12a) of the surface semiconductor layer (12) located beneath these raised semiconductor regions (42) throughout their entire thickness and so as to reach the insulating layer (11), - doping the raised semiconductor regions (42) and said portions (12a),- to perform at least one laser thermal annealing using one or more laser pulses (L) so as to achieve recrystallization of said raised regions (42) and said portions (12a) while simultaneously activating dopants in said regions and portions.
2. A method according to claim 1, wherein the step of rendering amorphous said raised semiconductor regions (42) and said portions (12a) is carried out by implantation using a beam inclined with respect to a normal (n) to a principal plane of the support, so as to achieve an amorphization of areas (12c) of the surface layer (23) which extend under the spacers (33).
3. A method according to any one of claims 1 or 2, wherein the step of doping said raised semiconductor regions (42) and said portions (12a) comprises implantation using a beam inclined with respect to a normal to a principal plane of the support, so as to dope areas (12c) of the surface layer (23) which extend under the spacers (33).
4. A method according to any one of claims 1 to 3, further comprising the steps of: - forming the grid block (25), - forming spacers (33) on either side of the grid block (25), - formation of said raised semiconductor regions (42) on either side of the spacers (33), the process further comprising after formation of the grid block and prior to the formation of the spacers: - the doping of areas (122) called extension zones of the surface semiconductor layer located on either side of the grid block (25), the spacers being formed opposite said extension zones (122).
5. A method according to claim 4, wherein the doping of the extension zones (122) in the surface semiconductor layer (12) on either side of the gate block (25) comprises steps consisting of: - rendering amorphous and doping an upper part (123) of the surface layer (12) while retaining a lower crystalline zone (124) of the surface layer (12) in contact with the insulating layer (11), - performing annealing so as to recrystallize said upper part (123) of the surface layer (12).
6. Method according to claim 5, wherein after formation of the insulating spacers (33) and prior to the amorphization of said raised semiconductor regions (42) and portions (12a) of the surface semiconductor layer (12) located under these semiconductor regions (42): - form by epitaxy the raised semiconductor regions (42) on said recrystallized upper part (123) of said surface layer (12).
7. A method according to any one of claims 1 to 6, wherein after laser thermal annealing regions (155) based on a composite of metallic material and semiconductor material are formed in the raised semiconductor regions (42).
8. Method according to claim 7, wherein prior to said laser thermal annealing at least one layer of metallic material is deposited so as to cover the raised semiconducting regions (42), the laser thermal annealing being adapted to form the regions (155) based on a composite of metallic material and semiconducting material in the raised semiconducting regions (42).
9. A method according to claim 7, wherein after said laser thermal annealing, the method comprises steps consisting of: - rendering amorphous upper portions (148) of said raised semiconductor regions (42), and then - depositing at least one layer of metallic material so as to cover said raised semiconducting regions (42) and perform annealing to form regions (155) based on a composite of metallic material and semiconducting material in said upper parts (148).
10. A method according to any one of claims 1 to 9, wherein the laser thermal annealing step is carried out using a laser by emitting one or more successive laser pulses, of pulse duration less than one microsecond and preferably between 1 ns and 1000 ns, advantageously between 20 ns and 300 ns, the laser having a wavelength between 200 nm and 600 nm and advantageously between 200 and 400 nm.
11. A method according to any one of claims 1 to 10, wherein laser thermal annealing is carried out so as to recrystallize said raised semiconductor regions (42) and said portions (12a) of the surface semiconductor layer (12) rendered amorphous in a recrystallization regime in which the raised semiconductor regions (42) and said portions (12a) are transformed into polycrystalline material.
12. A method according to any one of claims 1 to 11, wherein the support (100) is a semiconductor-on-insulator type substrate such as an SOI substrate or a support having one or more first-level (FL) components formed in an underlying semiconductor layer (2).