Method for manufacturing an electronic device

Abstract

Method for Improving an Electronic Device This description relates to a method for implementing an electronic device comprising the following successive steps: a) forming a structure comprising a diode stack (101) arranged on a first substrate (103) and a sacrificial layer (105) of a semiconductor material interposed between the first substrate (103) and the diode stack (101); b) transferring the structure onto a second substrate (131); and c) removing the first substrate (103) by electropolishing the sacrificial layer (105) by applying a bias voltage to the sacrificial layer (105) through the diode stack (101). Figure for the abstract: Fig. 1D

Description

Title of the invention: Method for making an electronic device technical field

[0001] This description relates generally to electronic devices. More specifically, this description relates to methods for manufacturing electronic devices comprising a step of removing a substrate on which a diode stack has been previously formed. Previous technique

[0002] Methods for manufacturing devices comprising a step of removing a substrate on which a diode stack has previously been formed have been proposed. In existing methods, wet etching techniques, for example using a mixture of hydrofluoric acid and nitric acid, dry etching techniques, for example using a sulfur hexafluoride-based plasma, or laser debonding are particularly employed to achieve substrate removal.

[0003] However, these embodiment methods suffer from various drawbacks. In particular, existing methods require, once the substrate has been removed, the implementation of complex buffer layer removal steps in order to expose the active layer(s) of the diode stack. Summary of the invention

[0004] An object of an embodiment is to overcome all or part of the drawbacks of known methods of manufacturing electronic devices comprising a step of removing a substrate on which a stack of diodes has been previously formed.

[0005] To this end, an embodiment provides a method for making an electronic device comprising the following successive steps: a) form a structure comprising a stack of diodes arranged on a first substrate and a sacrificial layer of a semiconductor material interposed between the first substrate and the stack of diodes; b) transfer the structure onto a second substrate; and c) remove the first substrate by electropolishing the sacrificial layer by applying a bias voltage to the sacrificial layer via the diode stack.

[0006] According to one embodiment, in step b), the transfer is carried out by conductive molecular bonding to the side of a first face of the diode stack opposite to the first substrate.

[0007] According to one embodiment, in step c), the structure is immersed in a electrolyte.

[0008] According to one embodiment, in step c), the bias voltage is applied between a first electrode connected to a conductive layer disposed on the second substrate and a second electrode immersed in the electrolyte.

[0009] According to one embodiment, the conductive layer covers the second substrate.

[0010] According to one embodiment, an insulating layer in which are formed contact re-establishment elements are interposed between the second substrate and the conductive layer.

[0011] According to one embodiment, the method further comprises, subsequent to step c), a step of etching the diode stack so as to form an elementary diode directly above each contact resumption element.

[0012] According to one embodiment, in step a), the first substrate is a whole plate having a maximum lateral dimension strictly less than that of the second substrate.

[0013] According to one embodiment, the method further comprises, between steps b) and c), a hollow via formation step extending from a face of the first substrate opposite the diode stack to the diode stack and through the sacrificial layer.

[0014] According to one embodiment, the diode stack comprises: - a first layer doped with a first type of conductivity coating the sacrificial layer; - an active layer coating the first layer; and - a second layer doped with a second type of conductivity, opposite to the first type of conductivity, coating the active layer.

[0015] According to one embodiment, the sacrificial layer is doped with the first type of conductivity.

[0016] According to one embodiment, the first layer has a level of doping strictly lower, for example at least ten times lower, preferably at least a thousand times lower, than that of the sacrificial layer.

[0017] According to one embodiment, the sacrificial layer is made of a III-V semiconductor material.

[0018] According to one embodiment, the sacrificial layer is made of gallium nitride.

[0019] According to one embodiment, the diode stack is a diode stack inorganic electroluminescent. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example. relationship with the attached figures, among which:

[0021] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D] and [Fig.1E] are schematic and partial cross-sectional views, illustrating successive steps of an example of a process for making an electronic device according to an embodiment;

[0022] [Fig.2A] and [Fig.2B] are schematic and partial cross-sectional views, illustrating successive stages of a variant of the process of figures IA to 1E;

[0023] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D] and [Fig.3E] are schematic and partial cross-sectional views, illustrating successive steps of an example of a process for making an electronic device according to an embodiment;

[0024] [Fig.4A], [Fig.4B] and [Fig.4C] are schematic and partial cross-sectional views, illustrating successive steps of an example of a process for making an electronic device according to an embodiment;

[0025] [Fig. 5] is a schematic and partial cross-sectional view illustrating a step in a variant of the process shown in Figures 4A to 4C; and

[0026] [Fig. 6] is a graph representing variations in pore size and density inside a gallium nitride layer depending on a doping level and bias voltage applied to said layer. Description of the implementation methods

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the construction of the diodes and their control circuits has not been detailed, as the construction of such diodes and circuits is within the capabilities of a person skilled in the art, based on the information provided in this description.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when reference is made to absolute positional qualifiers, such as the terms "front," "back," "top," "bottom," "left," "right," etc., or relative positional qualifiers, such as the terms "above," "below," "superior," "lower," etc., or to orientational qualifiers, such as the terms "horizontal," "vertical," etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean within 10%, preferably within 5%.

[0032] Figs [1A], [Fig.1B], [Fig.1C], [Fig.1D] and [Fig.1E] are schematic and partial cross-sectional views illustrating successive steps of an example of a process for making an electronic device according to an embodiment.

[0033] Fig. 1A illustrates more particularly a step in the formation of a structure comprising a stack of diodes 101, for example a stack of inorganic light-emitting diodes (LEDs), arranged on a substrate 103, and a sacrificial layer 105 of a semiconductor material interposed between the substrate 103 and the stack of diodes 101.

[0034] The substrate 103 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example silicon, sapphire, gallium nitride, or any other material on which a diode stack can be formed. By way of example, the substrate 103 is a free-standing gallium nitride substrate. In the method described in relation to Figures IA to 1E, the substrate 103 is a temporary support substrate intended to be removed, or discarded, during the fabrication of the device.

[0035] In the example shown, the substrate 103 is coated, on one of its faces facing the diode stack 101 (the upper face of the substrate 103, in the orientation of [Fig. 1A]), with a buffer layer 107. The buffer layer 107 is, for example, intended to form an interface between the substrate 103 and the diode stack 101, for example in order to improve the crystalline quality of the materials of the diode stack 101. As an example, the buffer layer 107 is formed by epitaxial growth from the upper face of the substrate 103.

[0036] In the illustrated example, one face of the buffer layer 107 opposite the substrate 103 (the upper face of the buffer layer 107, in the orientation of [Fig. 1A]) is coated with the sacrificial layer 105. The sacrificial layer 105 is, for example, made of an inorganic semiconductor material, for example, an IILV compound comprising at least a first element from Group III, a second element from Group V, and optionally, a third element, for example, a Group III element other than the first element. By way of example, the material of the sacrificial layer 105 is chosen from gallium nitride (GaN), indium nitride (InN), indium-gallium nitride (InGaN), aluminum nitride (AIN), aluminum-gallium nitride (AlGaN), and indium-gallium-aluminum nitride (InGaAlN).

[0037] The buffer layer 107 is for example made of the same material as the sacrificial layer 105, for example gallium nitride.

[0038] The sacrificial layer 105 is, for example, heavily doped with a first type of conductivity, for example type N (N++ doping), and exhibits, for example, a doping level between 1 x 10¹⁹ and 1 x 10²⁰ at. / cm³, for example in the case of silicon-based doping, the doping level can reach approximately 1 x 10²² at. / cm³, for example in the case of germanium-based doping. As an example, the sacrificial layer 105 is formed by epitaxial growth from the face of the buffer layer 107 opposite the substrate 103 (the upper face of the buffer layer 107, in the orientation of [Fig. 1A]).

[0039] Although a single buffer layer 107 located between the substrate 103 and the sacrificial layer 105 has been illustrated in [Fig.1A], the structure may alternatively comprise a stack of at least two buffer layers interposed between the substrate 103 and the sacrificial layer 105, the respective thicknesses and materials of these buffer layers being, for example, chosen according to the material or materials present in the stack of diode 101.

[0040] The diode stack 101 covers a face of the sacrificial layer 105 opposite the substrate 103 (the upper face of the sacrificial layer 105, in the orientation of [Fig.1A]). In the example shown, the diode stack 101 comprises a layer 109 doped with the first type of conductivity (type N, in this example) covering the upper face of the sacrificial layer 105, an active layer 111 covering the upper face of the layer 109, and a layer 113 doped with a second type of conductivity (type P, in this example), opposite to the first type of conductivity, covering the upper face of the active layer 111. The layer 109 of the diode stack 101 has, for example, a doping level strictly lower, for example at least ten times lower, preferably at least a thousand times lower, than that of the sacrificial layer 105. As an example, the layer 109 has a doping level on the order of 1 x 1018 at. / cm3.For example, layers 109 and 113 are made of the same material as sacrificial layer 105, for example gallium nitride.

[0041] In the example illustrated in [Fig.1A] where the diode stack 101 is an LED-type stack, the layers 109 and 113 are, for example, respectively an electron injection and / or transport layer and a hole injection and / or transport layer. The active layer 111 is, in this example, an emissive layer designed to emit light into an external environment when a potential difference is applied between layers 109 and 113 arranged on either side of the active layer 111. Although not detailed in [Fig. IA], the diode stack 101 may further include one or more hole-blocking layers, for example interposed between the emissive layer 111 and the electron injection and / or transport layer 109, and / or one or more electron-blocking layers, for example interposed between the emissive layer 111 and the electron injection and / or transport layer 113. of holes.

[0042] By way of example, the active layer 111 includes multiple quantum wells (“Multiple Quantum Wells” - MQW).

[0043] In the illustrated example, an electrically conductive layer 115 covers one face of the diode stack 101 opposite the substrate 103 (the upper face of the diode stack 101, in the orientation of [Fig. 1A]). In this example, the conductive layer 115 more precisely covers the upper face of the layer 113. The conductive layer 115 is, for example, an anode electrode connected to the diode stack 101 by the hole injection and / or transport layer 113. By way of example, the conductive layer 115 is made of a metal or a metal alloy.

[0044] In the example shown, another electrically conductive layer 117 covers a face of the conductive layer 115 opposite the substrate 103 (the upper face of the conductive layer 115, in the orientation of [Fig. 1A]). By way of example, the conductive layer 117 is made of a metal, for example titanium, or of a metallic alloy.

[0045] [Fig.1B] illustrates more particularly a later cutting (“dicing” in English) step of the structure previously described in relation to [Fig.1A].

[0046] In the example shown, the structure of [Fig.1A] is cut out over its entire height so as to form vignettes 121. Each vignette 121 comprises a part of the substrate 103 and a vertical stack comprising, in order from the substrate 103, parts of the buffer layer 107, the sacrificial layer 105, the diode stack 101, the conductive layer 115 and the conductive layer 117.

[0047] By way of example, each vignette 121 has, in top view, a perimeter of substantially rectangular, circular or square shape, and a surface area of ​​between a few square micrometers and a few square centimeters.

[0048] Although three vignettes 121 have been represented in [Fig.1B], the cutting step can of course lead to the formation of a number of vignettes 121 other than three, for example several tens or several hundred vignettes 121.

[0049] Fig. 1C illustrates more particularly a structure obtained at the end of a subsequent step of transferring the vignettes 121 (of two vignettes 121, in the illustrated example) onto a substrate 131.

[0050] The vignettes 121 are, for example, first turned over with respect to the orientation of [Fig. 1B] and then brought into contact, by the face of layer 117 opposite the substrate 103 (the lower face of layer 117, in the orientation of [Fig. 1C]), with an electrically conductive layer 133 covering a face of the substrate 131 (the upper face of substrate 131, in the orientation of [Fig. 1C]). During this step, the vignettes 121 are fixed to the substrate 131. By way of example, the fixing of the vignettes 121 to the Substrate 131 is obtained by molecular bonding between the two surfaces brought into contact. In the case where layers 117 and 133 are made of a metal or a conductive metal alloy, the bonding is described as "metal / metal" or "conductive".

[0051] The substrate 131 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example silicon. Although not detailed in [Fig. 1C], an electrically insulating layer, for example silicon dioxide, may be provided between the substrate 131 and the conductive layer 133. By way of example, the conductive layer 133 is made of the same material as the layer 117, for example titanium.

[0052] Fig. 1D illustrates more particularly a later step in the removal of the sacrificial layer 105.

[0053] In the example shown, the sacrificial layer 105 is removed by electropolishing by applying a bias voltage to it via the diode stack 101. The structure previously described in relation to [Fig. 1C] is, for example, immersed in an electrolyte 141 and a bias or anodizing voltage V_pol is, for example, applied by a potentiometer between a first electrode, for example an anode electrode connected to the conductive layer 133, and a second electrode, for example a platinum cathode electrode immersed in the electrolyte 141. In order not to clutter the drawing, the potentiometer and the first and second electrodes for applying the bias voltage V_pol have not been shown in [Fig. 1D].The voltage V_pol is, for example, approximately equal to the sum of a voltage V_LED, resulting from a voltage drop caused by the diode stack 101, and a voltage E applied to, or seen by, the sacrificial layer 105 (V_pol = E + V_LED). As an example, for an anodizing current density of approximately 100 pA / cm2, the voltage drop V_LED is approximately 2 V and the voltage E to which layer 105 is subjected is approximately 18 V, the anodizing voltage V_pol applied by the potentiostat then being approximately 20 V.

[0054] By way of example, electrolyte 141 is an aqueous solution of oxalic acid having a molar concentration between 0.3 and 0.9 M.

[0055] In the example shown, electropolishing leads to porosification of the sacrificial layer 105. In the example illustrated in [Fig.1D], the material of the part of the sacrificial layer 105 of each vignette 121 is progressively removed from its sides towards a central region of the part of the sacrificial layer 105. By way of example, the electropolishing speed of the sacrificial layer 105 is between 0.01 and 2 cm / h, for example between 1 and 2 cm / h.

[0056] Electropolishing is symbolized in [Fig. 1D] by the fact that the sacrificial layer 105 has V-shaped flanks. This example is not, however, limiting; the flanks of the sacrificial layer 105 which can, under the action of electropolishing, present any shape, for example a substantially concave circular shape or a flat shape, corresponding for example to the shape of an electropolishing front moving laterally towards the center of the layer.

[0057] Fig. 1E illustrates more particularly a structure obtained after subsequent steps of removing substrate 103 and etching layer 133.

[0058] The portions of the substrate 103 and the buffer layer 107 of each vignette 121 are, for example, removed, i.e. detached from the diode stack 101, after the sacrificial layer 105 has been removed by electropolishing during the step described above in relation to [Fig. 1D]. In the example illustrated in [Fig. 1E], the sacrificial layer 105 is completely removed.

[0059] An advantage of applying the voltage V_pol between an electrode connected to layer 133 and another electrode immersed in electrolyte 141 as described above in relation to [Fig.1D] is that it allows precise control of the detachment area of ​​parts of substrate 103 and buffer layer 107 of each vignette 121 with respect to the diode stack 101.

[0060] In the example shown, portions of layer 133 located between the vignettes 121 are removed, for example by photolithography followed by etching, while other portions of layer 133 located directly above the vignettes 121 are retained. This allows, for example, each vignette 121 to be electrically isolated from the other vignettes 121.

[0061] Subsequent steps in the manufacturing process of the electronic device can then be implemented from the structure illustrated in [Fig.1E], the substrate 131 being intended, for example, to be retained after these steps.

[0062] Fig. 2A and Fig. 2B are schematic and partial cross-sectional views illustrating successive stages of a variant of the process of Figures IA to 1E.

[0063] [Fig.2A] illustrates more particularly a structure obtained at the end of a step of transferring the vignettes 121 onto the substrate 131 analogous to the step previously described in relation to [Fig.1C].

[0064] The step illustrated in [Fig. 2A] differs from the step illustrated in [Fig. 1C] in that, in the step illustrated in [Fig. 2A], an electrically insulating layer 201, for example made of silicon dioxide, is interposed between the substrate 131 and the electrically conductive layer 133. In the example shown, contact elements 203, for example electrically conductive pads, are formed in the insulating layer 201 and are flush with the face of the insulating layer 201 coated with the layer 133 (the upper face of the insulating layer 201, in the orientation of [Fig. 2A]). By way of example, the insulating layer 201 and the contact elements 203 are part of an interconnect stack not detailed in [Fig. 2A]. The contact elements of Contact 203, for example, is intended to connect each vignette 121 to a control circuit (not shown) formed in and on the substrate 131.

[0065] By way of example, substrate 131 is said to be "active", that is to say, substrate 131 includes active electronic components such as transistors. Substrate 131 is, for example, of the CMOS type (from the English "Complementary Metal-Oxide-Semiconductor") or of the TFT type (from the English "Thin-Film Transistor").

[0066] [Fig.2B] illustrates more particularly a structure obtained after subsequent steps of removing the substrate 103 and etching parts of the layer 133 located between the vignettes 121 analogous to the steps previously described in relation to [Fig.1E],

[0067] The sacrificial layer 105 is removed by electropolishing, for example under conditions similar to those previously described in relation to [Fig.1D], so as to remove, or eliminate, the buffer layer 107 and the substrate 103. By way of example, the parts of the layer 133 extending laterally between the vignettes 121 are then removed by photolithography and then etching.

[0068] In the example shown, each vignette 121 is located directly above a contact resumption element 203 different from the contact resumption elements 203 directly above which the other vignettes 121 are located. Each contact resumption element 203 allows, for example, the diode stack 101 of the vignette 121 above to be controlled independently of the diode stacks 101 of the other vignettes 121 of the electronic device.

[0069] Subsequent steps in the manufacturing process of the electronic device can then be implemented from the structure illustrated in [Fig.2B], the substrate 131 being intended, for example, to be retained after these steps.

[0070] Figs. 3A, 3B, 3C, 3D and 3E are schematic and partial cross-sectional views illustrating successive steps of an example of a process for making an electronic device according to an embodiment.

[0071] Figure 3A illustrates more particularly a structure obtained after a step of transferring the vignettes 121 onto the substrate 131 analogous to the step previously described in relation to Figure 2A. Although the transfer of only one vignette 121 was illustrated in Figure 3A, several vignettes 121 can be transferred during this step.

[0072] The step illustrated in [Fig.3A] differs from the step illustrated in [Fig.2A] in that, in the step illustrated in [Fig.3A], each vignette 121 is transferred to the vertical position of several contact resumption elements 203 (three contact resumption elements 203, in the example shown).

[0073] Figure 3B illustrates more particularly a subsequent electropolishing step of the sacrificial layer 105 analogous to the step previously described in relation to the [Fig.1D].

[0074] Fig. 3C illustrates more particularly a structure obtained after a further step of removing substrate 103 and buffer layer 107.

[0075] Fig. 3D illustrates more particularly a structure obtained after a subsequent step of etching the stack of diodes 101 so as to form elementary diodes 301.

[0076] In the example shown, each elementary diode 301 is located directly above a contact resumption element 203 distinct from the contact resumption elements 203 directly above which the other elementary diodes 301 are located. In this example, the elementary diodes 301 have lateral dimensions smaller than those of the thumbnails 121.

[0077] Fig. 3E illustrates more particularly a structure obtained after a subsequent step of etching the conductive layers 115, 117 and 133.

[0078] In the example shown, portions of the conductive layers 115, 117, and 133 located between the elementary diodes 301 are removed, for example by photolithography followed by etching, while other portions of the layers 115, 117, and 133 located directly above the elementary diodes 301 are retained. This allows, for example, each elementary diode 301 to be electrically isolated from the other elementary diodes 301.

[0079] Subsequent steps in the manufacturing process of the electronic device can then be implemented from the structure illustrated in [Fig.3E], the substrate 131 being intended, for example, to be retained after these steps.

[0080] Fig. 4A, Fig. 4B and Fig. 4C are schematic and partial cross-sectional views illustrating successive steps of an example of a process for making an electronic device according to an embodiment.

[0081] Fig. 4A illustrates more particularly a structure obtained after a step of transferring the structure previously described in relation to Fig. 1A onto the substrate 131.

[0082] In the example shown, the structure of [Fig. 1A] is not cut out before being transferred onto the substrate 131. This corresponds, for example, to a case in which the substrate 103 is a whole wafer on which the diode stack 101 is formed. In this example, the substrate 103 has a maximum lateral dimension strictly smaller than that of the substrate 131. By way of example, in the case where the substrates 103 and 131 have, in top view, a substantially circular circumference, the substrate 103 has a diameter strictly smaller than that of the substrate 131.

[0083] Figure 4B illustrates more particularly a subsequent electropolishing step of the sacrificial layer 105 analogous to the step previously described in relation to the [Fig.1D].

[0084] Fig. 4C illustrates more particularly a structure obtained after a further step of removing substrate 103 and buffer layer 107.

[0085] Subsequent steps in the manufacturing process of the electronic device can then be implemented from the structure illustrated in [Fig.4C], the substrate 131 being intended, for example, to be retained after these steps.

[0086] Fig. 5 is a schematic and partial cross-sectional view illustrating a step of a variant of the process of Figures 4A to 4C.

[0087] Figure 5 illustrates more particularly a subsequent electropolishing step of the sacrificial layer 105 analogous to the step previously described in relation to Figure 4B.

[0088] The step illustrated in [Fig.5] differs from the step illustrated in [Fig.4B] in that, in the step illustrated in [Fig.5], hollow holes or vias 501 extend from a face of the substrate 103 opposite the diode stack 101 (the top face of the substrate 103, in the orientation of [Fig.5]) to a face of the diode stack 101 facing the substrate 103 (the top face of the diode stack 101, in the orientation of [Fig.5]). In the example shown, the vias 501 totally traverse the substrate 103, the buffer layer 107 and the sacrificial layer 105 and open onto a face of the electron injection and / or transport layer 109 facing the substrate 103 (the top face of layer 109, in the orientation of [Fig.5]).

[0089] Although only three vias 501 are shown in [Fig. 5], a number of vias 501 greater than three may be envisaged. Alternatively, the vias 501 may be replaced by trenches extending, in the orientation of [Fig. 5], from the upper face of the substrate 103 to the upper face of the electron injection and / or transport layer 109.

[0090] Providing vias 501 through the sacrificial layer 105 advantageously allows for a larger contact area between the sacrificial layer 105 and the electrolyte 141. This results in a reduction in the duration of the electropolishing step compared to the step previously described in relation to [Fig. 4B].

[0091] Fig. 6 is a graph representing variations in pore size and density within a gallium nitride layer, corresponding for example to the sacrificial layer 105, as a function of an Nd doping level (expressed in at. / cm3, the values ​​indicated on the ordinate being to be multiplied by 1018) and a bias voltage E (in volts, V) applied to said layer.

[0092] In the example shown, the graph includes: - a 601 prebreakdown region in which the the crystalline structure of the layer begins to degrade; - a 603 region of porification, in which pores form within the layer without these pores significantly reducing the mechanical cohesion of the layer; - a 605 region of the electropolishing boundary, in which the beginning of a degradation of the mechanical cohesion of the layer is observed; and - an electropolishing region 607, in which the layer is removed under the effect of the application of the bias voltage.

[0093] Furthermore, the graph in [Fig. 6] includes: - a zone 611 corresponding to an Nd doping level of approximately 3.5 x 1018 at. / cm3, in which the pores have a size between 25 and 52 nm and a density between 0.12 x 1010 and 2.4 x 1010 cm2; - a zone 613 corresponding to an Nd doping level of approximately 6 x 10¹⁸ at. / cm³, in which the pores have a size between 24 and 39.7 nm and a density between 3 x 10¹⁰ and 4.9 x 10¹⁰ cm²; and - a zone 615 corresponding to an Nd doping level of approximately 15 x 1018 at. / cm3, in which the pores have a size between 17 and 31 nm and a density between 5.7 x 1010 and 10.6 x 1010 cm2.

[0094] The size of a pore corresponds, for example, to the maximum lateral dimension of the pore.

[0095] In the case where the sacrificial layer 105 is made of gallium nitride, a level of Nd doping of the order of 13 x 1018 at. / cm3 and a voltage E applied to layer 105 of the order of 15 V, symbolized by a cross 621 located in the electropolishing region 607, allow for example the implementation of the electropolishing steps of the sacrificial layer 105 previously described in relation to figures 1D, 3B, 4B and 5. In this case, layer 109 of the diode stack 101 has for example a doping level of the order of 3 x 1018 at. / cm3, symbolized by a cross 623 located in the pre-break region 601. This allows the sacrificial layer 105 to be eliminated without damaging the layer 109 of the diode stack 101. As an example, the bias voltage V_pol is in this case on the order of 17 V. As an alternative, the doping level of the layer 109 can be such that the cross 623 is located in the 603 porosification region, or even in the 605 electropolishing limit region, for example less than or equal to 10 x 1018 at. / cm3.

[0096] Various embodiments and variants have been described. A person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to a person skilled in the art. In particular, a person skilled in the art is able to combine the variant of Figures 2A and 2B with the embodiment of Figures 4A to 4C and the variant of [Fig. 5], that is, to foresee, in the embodiment of Figures 4A to 4C and in the variant of [Fig.5], an active substrate 131 surmounted by an insulating layer in which contact re-establishment elements are formed.

[0097] Furthermore, a person skilled in the art is able to combine the embodiment described above in relation to Figures 3A to 3E with the embodiment and variant described in relation to Figures 4A to 5. For this purpose, the person skilled in the art can in particular provide, in the step described in relation to [Fig.3A], for the transfer onto the substrate 131 not of one or more vignettes 121 but of the structure described in relation to [Fig.1A].

[0098] A person skilled in the art is also able to adapt the variant shown in relation to [Fig.5] to the embodiments and variants described in relation to Figures IA to 3E, i.e. to provide vias or trenches to increase the contact area of ​​the sacrificial layer 105 with the electrolyte 141 during the electropolishing step of the sacrificial layer 105.

[0099] Although the embodiments described above take as an example the case where the diode stack 101 is of the LED type, these embodiments can be transposed by those skilled in the art to cases where the diode stack 101 is of any type, for example a stack of power diodes, photosensitive diodes, etc. More generally, the embodiments described apply to any type of stack comprising at least one PN junction.

[0100] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned above.

[0101] Furthermore, a person skilled in the art is able to select the material and the level of Nd doping of the sacrificial region 105 based on the information in this description. A person skilled in the art is also able to select the bias voltage V_pol to be applied during the electropolishing step of the sacrificial layer 105, for example, as a function of the voltage E that is to be applied to the layer 105.

Claims

Demands

1. Method of making an electronic device comprising the following successive steps: a) forming a structure comprising a diode stack (101) disposed on a first substrate (103) and a sacrificial layer (105) of a semiconductor material interposed between the first substrate (103) and the diode stack (101); b) transferring the structure onto a second substrate (131); and c) removing the first substrate (103) by electropolishing the sacrificial layer (105) by applying a bias voltage (E) to the sacrificial layer (105) via the diode stack (101).

2. Method according to claim 1, wherein, in step b), the transfer is carried out by conductive molecular bonding of the side of a first face of the diode stack (101) opposite the first substrate (103).

3. Method according to claim 1 or 2, wherein, in step c), the structure is immersed in an electrolyte (141).

4. Method according to claim 3, wherein, in step c), the bias voltage is applied between a first electrode connected to a conductive layer (133) disposed on the second substrate (131) and a second electrode immersed in the electrolyte (141).

5. Method according to claim 4, wherein the conductive layer (133) coats the second substrate (131).

6. Method according to claim 4, wherein an insulating layer (201) in which contact resumption elements (203) are formed is interposed between the second substrate (131) and the conductive layer (133).

7. Method according to claim 6, further comprising, subsequent to step c), a step of etching the diode stack (101) so as to form an elementary diode (301) in line with each contact resumption element (203).

8. A method according to any one of claims 1 to 7, wherein, in step a), the first substrate (103) is a whole wafer having a maximum lateral dimension strictly less than that of the second substrate (131).

9. A method according to any one of claims 1 to 8, further comprising, between steps b) and c), a hollow via formation step

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13.

14.

15. (501) extending from a face of the first substrate (103) opposite the diode stack (101) to the diode stack (101) and through the sacrificial layer (105). A method according to any one of claims 1 to 9, wherein the diode stack (101) comprises: - a first layer (109) doped with a first type of conductivity covering the sacrificial layer (105); - an active layer (111) coating the first layer; and - a second layer (113) doped with a second type of conductivity, opposite to the first type of conductivity, coating the active layer (111). Method according to claim 10, wherein the sacrificial layer (105) is doped with the first type of conductivity. Method according to claim 11, wherein the first layer (109) has a doping level strictly lower, for example at least ten times lower, preferably at least a thousand times lower, than that of the sacrificial layer (105). A method according to any one of claims 1 to 12, wherein the sacrificial layer (105) is made of a III-V semiconductor material. A method according to any one of claims 1 to 13, wherein the sacrificial layer (105) is made of gallium nitride. A method according to any one of claims 1 to 14, wherein the diode stack (101) is an inorganic light-emitting diode stack.

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