Random deterministic initialization SRAM memory

Abstract

Static random access memory device comprising a matrix in which each column is associated with an initialization circuit (100i, 100j), provided with a random value drawing stage (110) configured to, following the reception of the initialization activation signal (RAND_ENABLE), produce, randomly, respectively a first potential at a first node (NA) corresponding to a given logic state and a second potential at a second output node (NB) different from the first potential and corresponding to a given logic state complementary to said given logic state, in order to initialize cells of the same column to a given state and selected randomly between two states. Figure for the abstract: 3.

Description

Title of the invention: SRAM memory with random deterministic initialization Technical field

[0001] The present invention relates to the field of memories, and in particular of the SRAM type (SRAM for "Static Random Access Memory"), and more precisely concerns that of the initialization of SRAM memories.

[0002] The present invention implements an improved initialization circuit. STATE OF THE PRIOR ART

[0003] Transistors in PMOS technology undergo a physical phenomenon called NBTI (in English "Negative-Bias Temperature Instability"), which has the effect of increasing their threshold voltage, this even more when their dimensions are reduced. This phenomenon is also accelerated when the temperature and / or the negative voltage VGS applied between the gate and the source of the transistor increase.

[0004] An SRAM memory cell is commonly provided with two inverters connected in a head-to-tail cross-connection, each being formed in particular of a first P-type transistor and a second N-type transistor, with a ratio VTP1 / VTP2 of their respective threshold voltages of the two PMOS transistors.

[0005] The value stored in an SRAM memory cell will influence the PMOS transistors of a memory cell differently and the VTP1 / VTP2 ratio will change over time in one direction or the other depending on the stored value.

[0006] Thus, the NBTI phenomenon influences the probability of an SRAM cell to spontaneously initialize (when powered up) at logic level '1' or at its opposite level '0', given that the initialization logic level is linked to the VTP1 / VTP2 ratio.

[0007] However, memory data from the initialization of SRAM cells can be used to generate encryption keys or a hardware identifier or a unique digital fingerprint. They can be used to thus constitute a physical unclonable function (PUF for “Physical Unclonable Function”).

[0008] Certain cells having a high VTP1 / VTP2 ratio can in particular be identified as cells sufficiently stable to be used to constitute a PUF during a so-called enrollment phase.

[0009] However, due to the effects of the aforementioned NBTI phenomenon, the VTP1 / VTP2 ratio may be modified over time, which makes the cells less suitable for use in forming a PUF.

[0010] To limit such degradation over time of SRAM cells, one technique consists of inverting the contents of horizontal rows of memory cells regularly. Such a technique induces an increase in consumption and proves to be penalizing in terms of time during which the system can have access to the memory cells.

[0011] Bit inversion techniques are presented in the paper "Impact of NBTI on SRAM Read Stability and Design for Reliability", by S. Kumar et al., ISQED 2006 or in the paper "A Secure Data-Toggling SRAM for Confidential Data Protection", by W.-G. Ho et al., IEEE TCAS-I 2019. In the latter paper, the proposed solution has the disadvantage of modifying the cell structure by adding additional transistors. In all cases, the periodic inversion of bits results in a loss of time and energy in the memory user circuit.

[0012] A problem related to the effects of NBTI and which influences data security is the so-called "data imprint effect". Such an effect is described in the document: '^Challenging On-Chip SRAM Security with Boot-State Statistics", by J. McMahan et al., HOST 2017. When data stored in memory remains there for a long time (with a memory in operation, under power supply), the threshold voltage VTP of the PMOS transistor on changes, due to the same physical effect which causes NBTI. A harmful remanence effect or "data imprint" then makes it possible to recover data which has been previously stored even when the memory is reset.

[0013] Techniques such as "power analysis" (known as "CPA" or "DPA" according to the English acronyms "correlated Power analysis" or "differential power analysis") can be used to reveal data intended to remain secret, based among other things on this phenomenon of drift of the threshold voltage of the transistors by using means to accelerate this drift. Such a technique is described for example in the document: "Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications", by R. Giterman et al., ESSCIRC 2019.

[0014] The problem arises of producing an improved memory device with respect to at least one of the problems mentioned above. Statement of the invention

[0015] According to one aspect, the present invention relates to a memory device comprising a memory matrix arranged in rows and columns of SRAM memory cells, each column comprising a first bit line and a second complementary bit line respectively connected to access transistors of the memory cells of the column, each column being associated with an initialization circuit comprising a first coupling element and a second coupling element placed respectively between on the one hand the first and second bit lines of the associated column and on the other hand a control block, the control block being capable of imposing a voltage on the bit lines when at least one of said coupling elements is made conductive in a deterministic initialization mode of all or part of the cells of the column, and in which said control block comprises at least one random value drawing stage, to generate a value from two possible values ​​"0" or "1" associated with a column, and in which, in a so-called "random deterministic" initialization phase,the control block successively commands for at least one selected column: ,

[0016] - the generation of a random value by said random value drawing stage associated with each selected column; then

[0017] - the conduction of at least one coupling element among said first and second coupling elements of an initialization circuit associated with each selected column to connect at least one of the bit lines to the control block which imposes a voltage value, the choice of said coupling element put into conduction or the choice of the imposed voltage value being a function of the random value previously generated for the selected column, and the simultaneous putting into conduction of at least one access transistor of at least one cell of the selected column.

[0018] The random value drawing stage is capable of being coupled to a column of cells among said columns and provided with a first output node and a second output node, said random value drawing stage being configured to, following the reception of an initialization activation signal, produce, randomly, respectively a first potential at the first node corresponding to a given logic state and a second potential at the second output node different from the first potential and corresponding to a given logic state complementary to said given logic state,

[0019] at least one first initialization circuit associated with a first column being configured for, prior to a phase called “random deterministic initialization”:

[0020] - isolate the first output node and the second output node respectively of a first bit line and a second bit line of said first column while putting the first output node and the second node at the same potential,

[0021] then, during the random deterministic initialization phase triggered by the reception of said initialization activation signal,

[0022] - let the first output node and the second node settle respectively at different potentials, while coupling the first output node to said first bit line and the second output node to said second bit line of the first column.

[0023] Advantageously, the random value drawing stage is provided with a first inverter and a second inverter mutually connected in a cross-connected manner.

[0024] According to one possible implementation, the initialization circuit comprises:

[0025] - a transistor switching stage, arranged between a first element of polarization and the output nodes of said random value drawing stage, configured to, outside of random deterministic initialization phases, connect the output nodes of said random value drawing stage to the first polarization element and to isolate the output nodes of the random value drawing stage from said first polarization element during said random deterministic initialization phases,

[0026] - a switch element, in particular a transistor, configured to, outside of said random deterministic initialization phases, isolating said random value drawing stage from a second polarization element and during said random deterministic initialization phases, connecting said random value drawing stage to said second polarization element.

[0027] According to one possible embodiment, the transistor switching stage can be further configured to, outside of said random deterministic initialization phases, isolate the output nodes of said random value drawing stage from one another and, during said random deterministic initialization phases, connect the output nodes of said random value drawing stage to one another.

[0028] According to one possible implementation, the first coupling element is a first coupling transistor between the first bit line and a first output node of the random value drawing stage, wherein the second coupling element is a second coupling transistor arranged between the second bit line and a second output node of the random value drawing stage, the first coupling transistor and the second coupling transistor being controlled by said random deterministic initialization activation signal.

[0029] Advantageously, the random value drawing stage may comprise a shared circuit for drawing a random number from several bits, each bit being associated with a column.

[0030] According to a possible implementation of the device, at least a portion of the memory cell array includes so-called sensitive cells and the device comprises a memory controller capable of imposing a random deterministic initialization of these sensitive cells when the memory device is powered up or following an operation of erasing the memory array.

[0031] According to another aspect, the present application relates to a static random access memory device comprising a memory matrix arranged in rows and columns of SRAM memory cells, each column being associated with an initialization circuit, a first initialization circuit among said initialization circuits associated with a first column among said columns being provided with a stage capable of being coupled to a column of cells among said columns and provided with a first output node and a second output node, said random draw stage being configured to, following the reception of the initialization activation signal, produce, randomly, respectively a first potential at the first node corresponding to a given logic state and a second potential at the second output node different from the first potential and corresponding to a logic state complementary to said given logic state,the first initialization circuit being configured for, prior to a so-called random deterministic initialization phase: ,

[0032] - isolate the first output node and the second output node respectively of a first bit line and a second bit line of said column while putting the first output node and the second node at the same potential, then, during the random deterministic initialization phase triggered by the reception of said initialization activation signal:

[0033] - let the first output node and the second node settle respectively at different potentials, while coupling the first output node to said first bit line and the second output node to said second bit line.

[0034] With such an initialization circuit, a new way of initializing the cells of the same column to the same determined state is thus provided and makes it possible in particular to overcome the phenomenon of data printing. Such a circuit contributes to better data security and makes the use of certain memory cells more reliable, in particular those for constituting a PUF.

[0035] According to one possible implementation, the initialization circuit comprises:

[0036] - a transistor switching stage, arranged between a biasing means, and the output nodes of said stage, configured to, outside of random deterministic phases, connect the output nodes of said random draw stage to the first polarization element and to isolate the output nodes of said random draw stage from said first polarization element during said random deterministic phases,

[0037] - a switching element, in particular a transistor, configured to outside of said random deterministic phases isolating said draw stage from a polarization element and during said random deterministic phases, connecting said random draw stage to said polarization element.

[0038] Advantageously, the transistor switching stage can be further configured to isolate the nodes from each other outside of said random deterministic phases. output of said drawing stage and during said random deterministic phases, connecting the output nodes of said drawing stage to each other.

[0039] According to one possible implementation, the initialization circuit comprises:

[0040] - a first coupling transistor between the first bit line and the first node exit,

[0041] - a second coupling transistor arranged between the second bit line and the second output node, the first coupling transistor and the second coupling transistor being controlled by said random deterministic initialization activation signal.

[0042] Advantageously during the so-called random deterministic phase:

[0043] - said draw stage of said first initialization circuit produces respectively a first potential at its first node and a second potential at its second node, different from the first potential and corresponding to a complementary logical state of said first logical state,

[0044] - a second initialization circuit associated with a second column among said columns being provided with a second draw stage identical to said draw stage and producing respectively, said second potential and said first potential respectively at its first output node and at its second output node.

[0045] Advantageously, during a subsequent random deterministic phase, said drawing stage of said first initialization circuit produces, following the reception of said same initialization activation signal, respectively a first potential at its first output node and a second potential at its second output node. Brief description of the drawings

[0046] The present invention will be better understood on reading the description of exemplary embodiments given, for purely indicative and non-limiting purposes, with reference to the appended drawings in which:

[0047] [Fig.l] serves to illustrate a matrix of SRAM memory cells whose columns are each provided with a random deterministic column initialization circuit as implemented according to the invention.

[0048] [Fig.2] serves to illustrate a conventionally arranged SRAM memory cell and capable of being integrated into a memory device according to the invention.

[0049] [Fig.3] serves to illustrate an example of the implementation of a deterministic initialization circuit column randomization to initialize cells in the same column of cells randomly from one initialization to another.

[0050] [Fig.4A]

[0051] [Fig.4B] are used to illustrate different states to which the bit lines coupled to the column initialization circuit can be set.

[0052] [Fig.5] is used to illustrate different columns of a cell matrix whose columns are initialized independently of each other through their respective initialization circuits.

[0053] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0054] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0055] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0056] An example of an SRAM memory device is given in [Fig.l] and comprises a memory plane Mi formed of a plurality of columns COLi, ..., COLn (with n an integer strictly greater than 1, the columns corresponding in this example to vertical rows) and lines LINi, ..., LINm (with m an integer strictly greater than 1, the lines corresponding in [Fig.l] to horizontal rows) comprising n*m distinct SRAM memory cells Cn, ..., Cnm.

[0057] Conventionally, each column of cells is associated with a pair of bit lines from a set of pairs of bit lines BLTi, BLFi,..., BLTn, BLFn. Similarly, each line of cells is typically associated with a word line from a set of word lines WLi,..., WLm. Each word line makes it possible, when activated, to select the memory cells of a given line of SRAM cells from said lines of SRAM cells.

[0058] An initialization phase of the SRAM memory cells is provided when the memory device is powered up, but also following a memory erasure operation, for example following detection of an attempt to fraudulently access the memory without it being provided to turn off the entire memory device to reset the contents of the memory. During a memory erasure operation, the internal nodes of the memory cells can be positioned at identical or substantially identical values ​​(i.e. which differ by minus 10 mV), either by short circuit or by discharging the nodes following a power cut. A possible initialization phase therefore consists of changing a memory cell from an “undetermined” state (and undeterminable by reading) to a state with a “determined” stored value (and therefore determinable by reading).

[0059] The present application follows other patent applications of the applicant in connection with the subject of SRAM memory devices. Thus, reference may be made to patent application FR, No. 1761692, filed on December 6, 2017 in which a fast erase mechanism is described. Reference may also be made to a second French patent application No. 2111286 filed by the applicant on October 25, 2021 before the National Institute of Intellectual Property in which it A device for initializing the SRAM memory is described, according to several possible modes, a free mode and a deterministic mode. We subsequently use a common vocabulary with this second patent application. A so-called "free" initialization mode consists of letting each memory cell initialize itself to a specific value during the progressive power-up of the elements constituting the memory cell, in particular two looped inverters as illustrated in [Fig.2], without seeking to impose a value "0" or "1" on the internal nodes NT and NF of the cell. In the free initialization mode, the access transistors TAt and TAF are non-conducting, the cell being as if "isolated" from the other cells and from the bit lines BLT and BLF. In contrast, a so-called "deterministic" initialization mode consists of imposing or forcing a value to be memorized by the cell during its transition from an indeterminate state to a determined state.To impose a value during initialization, the memory device comprises at the bottom of the column means for imposing a value on the internal nodes of the cells being initialized, via the bit lines and by making the access transistors of the cells concerned conductive. In this second patent application, the initialization value that one wishes to impose can be “0” or “1”. The deterministic initialization means described in this second application, in particular in connection with its figures 4A and 4B, make it possible to write all the memory cells either to “0” or to “1”. To do this, the device provides for controlling, for each column, one of the BLT or BLF bit lines by connecting it to a supply voltage by turning on a bit line selection transistor. The selected and powered bit line thus tends to impose a value “1” on one of the nodes of each memory cell connected to this bit line.

[0060] In the present patent application, an initialization circuit, in particular deterministic, according to the meaning given above, and which makes it possible to impose a value on all or part of the cells of the same column; this same value having been previously defined by a random drawing method.

[0061] The expression “random deterministic initialization” is subsequently used for this type of initialization proceeding in two stages, random drawing then “forced” initialization as will be better understood by reading the detailed examples given below.

[0062] The device here has the particularity of associating with each column COLi, ..., COLn of cells a column initialization circuit 100i, ..., 100n, configured to implement a phase of initialization of the cells of a column of the matrix called "random deterministic initialization". The initialization circuits 100i,...,100n are typically each further provided with a portion at the end of the column and coupled to a pair of bit lines among the set of pairs of bit lines BLTb BLFi,..., BLTn, BLFn. Each 100i, 100n column initialization circuit is configured to, during a random deterministic initialization by column, initialize the column of cells with which this circuit is associated by placing all the cells composing this column in the same given state. This same initialization state is determined by the equivalent of a “random draw” or pseudo-random draw carried out outside the cell matrix and applied to all or part of the cells of the same column during their initialization. This “random deterministic” initialization state is produced randomly or pseudo-randomly by a “random draw” stage 110 (not shown in this figure) of the initialization circuit 100i, ..., 100n.

[0063] The initialization circuit 100i, ..., 100n is preferably provided so that when a “random deterministic initialization” phase is triggered, nodes NA, NB of this circuit are established randomly and according to a probability close to 0.5, respectively at a first potential between a high or low potential corresponding to a given logic state, and at a second potential between a low or high potential, the second potential being different from the first potential and corresponding to a logic state complementary to the given logic state.

[0064] Thus, from one “random deterministic” initialization operation to the next, each column COL; can have, depending on a random draw, its cells Ch, Cn i all initialized in the same state, which happens to be the same state as during a previous initialization or in an opposite state. The sequence of initialization values ​​of the same column has a random character.

[0065] Following an initialization carried out by means of the circuits 100;,100j, the respective cells Ch ,... Cn i and Ci j„„ Cnj of distinct columns COL; COLj can be initialized, according to the random draw per column carried out by their respective circuits 100i,100j, all in the same state (corresponding to a '1' or a '0' on one of their two nodes) but this case is statistically unlikely or in different states from one column COL; to the other COLj.

[0066] These 100i, ..., 100n initialization circuits integrating a random deterministic initialization of the memory cells make it possible to counter CPA and DPA attacks for memory areas where the user does not control the initialization value. Indeed, as explained in the aforementioned document, to carry out this type of attack it is necessary to know the initialization value or at least to know that the initialization value is always the same. These methods often use a repetition of an initialization followed possibly by a stress phase and a post-processing method based on the assumption that the initialization values ​​of the cells are always the same. Thus, by using an initialization circuit according to the invention making it possible to initialize the memory cells to unknown values ​​and different over time, thanks to random draws, it is possible to thwart this type of attack.

[0067] Furthermore, when the initializations are repeated and lead to different values ​​in the memory cells, the aging phenomenon in these cells is less. Indeed, from a statistical point of view, if the memory cells are left in their initialization state and this is changed regularly during successive initializations, it is not always the same PMOS transistor which ages more quickly, which makes it possible to statistically limit the drift in the ratio of the threshold voltages VTP1 / VTP2.

[0068] These results are obtained while limiting the impact on the matrix itself in terms of memory device footprint. The random deterministic initialization circuits 100i, ..., 100n thus contribute to the hardware security of the memory data.

[0069] It is noted that the use of random deterministic initializations for a PUF area of ​​the memory also makes it possible to improve the reliability of this PUF area by limiting the aging of the transistors, or rather by limiting the drift of the VtP2 / VTP1 ratio unlike a circuit in which the initialization of the PUF area would always be carried out freely, leading to the memorization of the same values ​​in the memory cells as long as they have not been subjected to the effect of the NBTI too much.

[0070] The internal structure of the cells Cn,... Cnm of the memory device can, for its part, follow a conventional arrangement, as in [Fig.2], where an example of the structure of the SRAM cell Cy of the memory device is given. The cell Cy is provided with two storage nodes NT and NF, designed to store a first logical information, and a logical information complementary to the first information. The maintenance of the logical information in the nodes is ensured by transistors forming inverters INV1, INV2 looped on themselves. For example, when the SRAM cell is of the type commonly called "6T" and thus formed of 6 transistors. The two inverters INV1, INV2, are typically produced by two load transistors and two conduction transistors.The inverters INV1, INV2 are here connected to a first supply line, in particular a so-called "high" supply line, and to a second supply line, in particular a so-called "low" supply line. The supply line is set to a so-called "high" potential, for example equal to a supply voltage VDD, which is consequently higher than the so-called "low" potential of the low supply line, and typically corresponds to a reference or ground potential GND. Access to the storage nodes NT and NF is achieved by means of two access transistors TAt and TAF connected respectively to bit lines BLT; and . BLFi shared by the SRAM cells of the same COLi column of cells in the matrix plane.

[0071] This access to the storage nodes NT and NF is controlled by a word line WLj generally shared by the SRAM cells of the same line LINj of cells of the matrix plane. The access transistors TAt and TAF are thus provided to, when activated, allow access to the first node NT and to the second node NF, or when deactivated to block access to the first node NT and to the second node Nf.

[0072] In the present case, during a random deterministic initialization phase, the respective access transistors TAt and TAF of the cells of the initialized column are activated to allow initialization of each cell of the column.

[0073] A particular example of an initialization circuit 100i associated with a column COLi of cells is given in [Fig. 3]. This initialization circuit 100i here requires the implementation of only a limited number of additional elements peripheral to the memory plane Mi. The circuit 100i is provided with a random draw stage 110, located at the end of a given column COLi. When an initialization activation signal is applied to the circuit 100i, which here results in a rising edge or transition from a state '0' to a state '1' of the signal RAND_ENABLE, the stage 110 produces, as mentioned above, randomly on a first output node NA and on a second output node NB, respectively, a first high or low potential and a second potential, low or high but different and complementary in logic to the first potential. The RAND_ENABLE signal for "random deterministic initialization" mode can be supplied by a memory controller.

[0074] [Fig. 3] illustrates a particular embodiment of the random draw stage 110 with here a limited number of components and a limited size. This random draw stage 110 is formed of a first inverter INVA and a second inverter INVB mutually connected in a cross-connected manner and here each formed of a transistor 11 IA, 11 IB of the PMOS type, and of a transistor 112A, 112B of the NMOS type.

[0075] Preferably, transistors 11 IA, 112A, 11 IB, 112B are chosen of large size, for example equal to that of the transistors forming a detection amplifier with which the COLi column is associated.

[0076] The first inverter INVA is preferably designed with transistors 11 IA, 112A substantially identical to the transistors 11 IB, 112B of the second first inverter INVB.

[0077] By "substantially identical" is meant here that the transistors 11 IA, 11 IB on the one hand and 112A, 112B on the other hand are provided with structures and dimensions similar and that any existing differences are mainly due to local variabilities in the manufacturing process.

[0078] Similarly, preferably, each random draw stage 110 is identical or substantially identical to the other random draw stages of the other initialization circuits distributed over different columns.

[0079] The inverters INVA, INVB of the random draw stage 110 are coupled, for their high supply, to a first polarization element, for example a supply line LVdd, making it possible to deliver a high supply potential, for example Vdd.

[0080] A switch element, in particular a switch transistor 115, here of the NMOS type, is arranged between a second polarization element and the stage 110. The gate of the switch transistor 115 is controlled by the activation signal RAND_ENABLE provided to activate a random deterministic initialization phase.

[0081] The second polarization element, for example a power supply line LGND, is provided to deliver a reference or ground potential GND.

[0082] The initialization circuit 100i is here also provided with a switching stage 102, provided with transistors 103, 104, in particular of the PMOS type, which makes it possible to connect the two output nodes NA and NB to the same potential, here a high potential Vdd outside the random deterministic initialization phases. The gates of the transistors 103, 104 are also controlled by the initialization activation signal RAND_ENABLE. Outside of said “random deterministic initialization” phases, the switching transistor 115 isolates the stage 110 from the second biasing element, which contributes to maintaining the output nodes NA and NB of the pull-up stage 110 at the same potential in association with the action of the aforementioned switching stage.

[0083] The switch transistor 115 is here provided to, following the reception or the change of state of the initialization activation signal RAND_ENABLE, connect the inverters INVA, INVB to the so-called “low” supply line LVss, which allows the nodes NA and NB to be able to maintain one, and to discharge the other.

[0084] During random deterministic initialization phases, the switching stage 102 makes it possible to isolate the two output nodes NA and NB from the high supply potential Vdd, to allow the output nodes NA and NB of the stage 110 to establish themselves at different potentials, once the stage 110 has been re-powered by turning on the transistor 115.

[0085] The switching stage 102 is advantageously further provided here with an additional switching transistor 105, for example of the PMOS type, between the first node NA and the second node NB in ​​order to ensure good equalization of the potentials. "starting" of these two nodes prior to powering up stage 110 when carrying out a new random draw.

[0086] The transistor 105 whose gate is controlled by the initialization activation signal RAND_ENABLE is thus configured to, during the “random deterministic initialization” phases, isolate the output nodes NA, NB of the draw stage 110 from each other and connect the output nodes of the draw stage 110 to each other outside this random draw phase.

[0087] The initialization circuit 100 also comprises here a coupling stage 130 formed here of a transistor 131, in particular of the PMOS type, arranged between the first node NA and the first bit line BLT of the column COLi and another transistor 132, in particular of the PMOS type, arranged between the second node NB and the second bit line BLF of the column COLi. In the particular embodiment example given in [Fig. 3], inverters 123, 124 are also provided between the nodes NA, NB and the coupling stage 130.

[0088] The respective gates of the transistors 131, 132 are controlled by a signal which depends on the signal RAND_ENABLE, here in particular a signal at the output of an inverter 119, providing a signal complementary to the signal RAND_ENABLE.

[0089] Outside of the random deterministic initialization phases (RAND_ENABLE = 0), the nodes NA, NB are isolated from the bit lines BLTi, BLFi. It follows in this exemplary embodiment that the bit lines BLTi, BLFi are driven to perform a free initialization of the memory cells; the access transistors of the cells are additionally made non-conductive to avoid any residual influence of the bit lines on the memory cells, even if the bit lines are not powered.

[0090] During the random deterministic initialization phases (RAND_ENABLE = 1), the output nodes NA, NB are connected to the bit lines BLTi, BLFi in order to be able to load or unload the bit lines BLTi, BLFi respectively at a given potential which depends on that at which the first output node NA of the random drawing stage 110 is established and at another potential which depends on that at which the second node NB is established and which corresponds to a logic state complementary to that to which the given potential corresponds.

[0091] In this way, the same logic state is imposed on all the cells of the column COLi which are initialized by the initialization circuit 110i, this logic state being established randomly by the output of the random selection stage 110. To allow the cells of the same column to be initialized, the initialization circuit is typically connected to means for simultaneously activating all or part of the word lines of the cell matrix.

[0092] In Figures 4A-4B, two successive phases of random deterministic initialization of the same column are illustrated.

[0093] During a first initialization ([Fig.4A]), following the reception or change of state of the activation signal RAND_ENABLE, for example a falling edge of this signal RAND_ENABLE, the output nodes NA, NB are set respectively to a first potential and to a second potential (among a high potential VDD and a low potential GND or reference), so as to charge respectively the bit lines BLTi, BLFi to the first or second potential in order to impose on the nodes NT of the cells of this column, the same logic state, in particular '1' or '0', and on the nodes NF of the cells of this column the same logic state, in particular a '0' or '1'.

[0094] [Fig.5] serves to illustrate a random deterministic initialization phase carried out on two distinct columns of the same matrix.

[0095] This phase following the reception or change of state of the activation signal RAND_ENABLE, makes it possible to load the bit lines BLTi, BLFi of a column COLi respectively to a high potential VDD and to a low or reference potential, while the bit lines BLTj, BLFj of another column COLj are respectively at a low or reference potential and at a high potential VDD, while their initialization circuits lOOi, lOOj which are of identical design randomly deliver outputs different from each other.

[0096] It will be noted that the present invention can be implemented with a random draw stage 110 different from that described previously based on head-to-tail inverters. Thus other random generators of distinct potentials corresponding to complementary logic states can be provided.

[0097] For example, we can use a pseudo-random circuit for generating a bit based on a random seed, as there are many.

[0098] Furthermore, instead of having n circuits for drawing a random bit, it is possible as a variant to use a single circuit for drawing a sequence of n random or pseudo-random bits and to provide a connection device between this single circuit for drawing n random bits and the different near-column initialization circuits provided to control the initialization of the cells of the column to a value corresponding to one of the bits of the sequence of n random bits.

[0099] For example, looped oscillators can be used, as well as optical devices or arbitration PUFs, as described in the document: “PUF and Applications: A tutorial", by C. Herder et al., IEEE 2014. It is sufficient to connect an n-bit entropy source to an n-bit register. In this case, the circuit lOOi associated with each column comprises only the coupling circuit 130 (with transistors 131, 132) and transistors 123 and 124. The output of the i-th bit of the n-bit register is connected directly to the NA node (input of transistor 123) and connected via an inverter to the NB node (input of inverter 124). In other words, the device memory comprises in this embodiment a random value drawing stage shared within the memory replacing the n random drawing stages 110 of the embodiment previously described in connection with [Fig.3].

[0100] In addition to a “random deterministic initialization” as described above, a memory device according to the invention may be provided to carry out other types of initialization, and in particular “free” and / or “deterministic” type initializations as described in the second aforementioned patent application No. 2111286 filed by the applicant on October 25, 2021.

[0101] With an initialization circuit as described in the present application, a new way is added to initialize all the cells of the same column to the same randomly determined state by means of a circuit provided with an entropy source different from that of the cells themselves. The entropy source fulfills the function of a random bit generator and can in certain embodiments be integrated into a voltage write amplifier whose outputs drive the bit lines of a column of cells in a complementary manner.

[0102] According to an alternative embodiment, it is possible for the random deterministic initialization to be performed not on all the cells of the same column, but only on a portion of the cells of a column. In the case, for example, where the matrix includes several areas with different access and security properties, it may be possible, for example, to choose to initialize in a “random deterministic” manner the areas where security is to be maximized and to choose a free initialization for the other, less sensitive areas. Indeed, it should be noted that the deterministic initialization requires powering the bit lines and the current draw may become significant if a large number of cells are initialized simultaneously. Thus, leaving a free initialization for the non-critical cells and reserving the deterministic initialization for the sensitive cells may be a good compromise in terms of consumption and current peak for the memory device.In general, we can therefore provide random deterministic initialization for only part of the cells in a column by providing row selection means making it possible to turn on the access transistors of only the cells that we wish to initialize in this mode.

[0103] According to another embodiment variant, it is also possible to provide a random deterministic initialization which is based on an initialization circuit similar to that described in the second patent application No. 2111286 filed by the applicant on October 25, 2021, namely a control circuit which provides for supplying only one of the BLT or BLF lines depending on the value that one wishes to impose which has been previously defined by random drawing. Thus, one can for example modify the circuit of [Fig. 3] to provide control of the transistors 131 and 132 depending not only on the RAND_ENABLE signal, but also on the values ​​present at the output of the inverters 123 and 124 after the random draw has been carried out. Similarly, in the case of using a pseudo-random number generator, the activation of one of the transistors 131 or 132 can also be conditioned by the value of the bit of the register giving the random number after carrying out a random draw.

[0104] Alternatively, it is possible to provide a control circuit which always controls the same bit line BLi or BLFi (and not the other) but imposes either a supply voltage Vdd or a reference voltage GND.

[0105] Such so-called “single” embodiment variants of a random deterministic initialization circuit make it possible to limit the current draws which can be significant when the number of cells is high. A disadvantage of such a “single” initialization circuit compared to a “differential” initialization circuit such as those described previously in connection with Figures 1 and 3 is that the initialization operation is generally slower and potentially likely to have a non-zero probability of initialization error, such an error being nevertheless acceptable in certain applications. Thus, in the case where one wishes to prioritize initialization speed above all, it may be necessary to provide for partitioning the memory matrix and having columns of reasonable size which can be initialized by the same differential circuit.

[0106] Furthermore, the random deterministic initialization can be applied in parallel to all or part of the columns of the matrix. Indeed, it may be, for example for reasons of current peak management, that it is necessary to carry out the initialization of the columns sequentially, possibly by column blocks. Furthermore, depending on the architecture and organization of the memory matrix, it is possible that only certain columns host sensitive memory cells, for example because they store sensitive data, for which it is deemed appropriate to apply a random deterministic initialization.

Claims

1.

2. Claims Memory device comprising a memory matrix (Mi) arranged in rows (LINi,.. .,LINm) and columns (COLi,.. .,COLn) of SRAM memory cells (Cn,..., Cnm), each column comprising a first bit line (BLTi) and a second complementary bit line (BLFi) respectively connected to access transistors of the memory cells of the column, each column being associated with an initialization circuit (lOOi, lOOj) comprising a first coupling element (131) and a second coupling element (132) placed respectively between on the one hand the first and second bit lines of the associated column and on the other hand a control block, the control block being capable of imposing a voltage on the bit lines when at least one of said coupling elements (131, 132) is made conductive in a deterministic initialization mode of all or part of the cells of the column,and in which said control block comprises at least one random value drawing stage (110), to generate a value or a logical state from among two possible logical values ​​or states '0' or '1' associated with a column, and in which, in a so-called random deterministic initialization phase, the control block successively commands for at least one selected column:, - generating a random value by said random value drawing stage (110) associated with each selected column; then - turning on at least one coupling element among said first and second coupling elements of an initialization circuit associated with each selected column to connect at least one of the bit lines to the control block which imposes a voltage value, the coupling element turned on among said first coupling element (131) and second coupling element (132) or the voltage value imposed by said control block being a function of the random value previously generated for the selected column, and simultaneously turning on at least one access transistor of at least one cell of the selected column. Memory device according to claim 1 wherein the random value drawing stage (110) is adapted to be coupled to a column (COL;) of cells among said columns and provided with a first output node (NA) and a second output node (NB), said random value drawing stage (110) being configured to, following the reception of an initialization activation signal (RAND_ENABLE), produce, randomly, respectively a first potential at the first node (NA) corresponding to a given logic state and a second potential at the second output node (NB) different from the first potential and corresponding to a given logic state complementary to said given logic state, at least one first initialization circuit (100i) associated with a first column (COL;) being configured to, prior to a random deterministic initialization phase: - isolate the first output node (NA) and the second output node (NB) respectively from a first bit line (BLTi) and a second bit line (BLFi) of said first column (COLi) while putting the first output node (NA) and the second node (NB) at the same potential, then, during the random deterministic initialization phase triggered by the reception of said initialization activation signal (RAND_ENABLE), - let the first output node (NA) and the second node (NB) settle respectively at different potentials, while coupling the first output node (NA) to said first bit line and the second output node (NB) to said second bit line of the first column.;

3. A memory device according to claim 2, wherein said random value drawing stage (110) is provided with a first inverter (INVA) and a second inverter (INB) mutually cross-connected.

4. Memory device according to one of claims 2 or 3, wherein the initialization circuit (100i, 100j) comprises: - a transistor switching stage (102) (103, 104, 105), arranged between a first bias element (L'Vdd) and the output nodes (NA, NB) of said random value drawing stage (110), configured to, outside of random deterministic initialization phases, connect the output nodes (NA, NB) of said random value drawing stage (110) to the first bias element (LVdd) and to isolate the output nodes of the random value drawing stage (110) random of said first polarization element (LVdd) during said random deterministic initialization phases, - a switch element, in particular a transistor (115), configured to, outside of said random deterministic initialization phases, isolate said random value drawing stage (110) from a second polarization element (LGND) and during said random deterministic initialization phases, connect said random value drawing stage (110) to said second polarization element (LGND).

5. Memory device according to claim 4, wherein the transistor (103, 104, 105) switching stage (102) is further configured to, outside of said random deterministic initialization phases, isolate from each other the output nodes (NA, NB) of said random value drawing stage (110) and during said random deterministic initialization phases, connect to each other the output nodes (NA, NB) of said random value drawing stage (110).

6. Memory device according to one of claims 2 to 5, wherein the first coupling element is a first coupling transistor (131) between the first bit line (BLT) and a first output node (NA) of the random value drawing stage (110), wherein the second coupling element is a second coupling transistor (132) arranged between the second bit line (BLF) and a second output node (NB) of the random value drawing stage (110), the first coupling transistor (131) and the second coupling transistor (132) being controlled by said random deterministic initialization activation signal (RAND_ENABLE).

7. A memory device according to claim 1, wherein said random value drawing stage (110) comprises a shared stage for drawing a random number on several bits, each bit being associated with a column.

8. Memory device according to one of claims 1 to 6, in which at least a part of the memory cell array includes so-called sensitive cells and comprising a memory controller capable of imposing a random deterministic initialization of these sensitive cells when the memory device is powered up. or following a memory matrix erase operation.

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