Read circuit comprising a read amplifier, and corresponding memory device.

Abstract

Read circuit comprising a read amplifier, and corresponding memory device. A read circuit comprises a read amplifier for amplifying and latching a data signal read, via a bit line, in a memory cell (having a variable resistance) of a resistive memory. The read amplifier comprises: two branches with in each two transistors connected to form a logic inverter; a capacitor connecting the output of the logic inverter of the first branch with the input of the logic inverter of the second branch; two reference resistors and at least five switches. The variable resistor and the two reference resistors are connected to the input electrode of one of the four transistors, allowing a reduction in power consumption and an improvement in detection speed and margins.Multi-phase operation enables readout with high detection margins and fast detection phases. The capacitor helps cancel the effects of mismatch on the structure. Abstract figure: Figure 1.

Description

Title of the invention: Reading circuit comprising a reading amplifier, and corresponding memory device. 1. TECHNICAL DOMAIN

[0001] The field of the invention is that of resistive memories.

[0002] The invention relates more particularly to the reading of such resistive memories.

[0003] It relates to a reading circuit comprising a reading amplifier configured and controlled by a control unit to amplify and lock a data signal read, via a bit line, in a memory cell of a resistive memory.

[0004] It also relates to a memory device comprising a resistive memory, having a capacity of (m+l)x(n+l) bits, and (m+1) sense amplifiers each configured to amplify and latch a data signal read, via a particular bit line among the (m+1) bit lines, in one of the (n+1) memory cells associated with the particular bit line.

[0005] The invention applies in particular, but not exclusively, to the reading of a non-volatile type resistive memory. In other words, it also applies to the reading of a volatile type resistive memory. Each elementary information, called bit, is stored in a memory cell in the form of a resistance value which can take two values, high or low, representing a data bit (1 or 0).

[0006] A sense amplifier is sometimes also called a "sense amplifier." It is part of the read circuits that are used when data is read from a memory. Its task is to bias the resistor connected to a bit line and then amplify the voltage developed across the resistor to a level that allows the data to be used by other circuits outside the memory. There is one sense amplifier for each bit line, so there are dozens or even hundreds of identical sense amplifiers on a modern memory chip. 2. Technological background

[0007] In the remainder of this document, we will focus more particularly on describing the problems existing in the particular case of non-volatile resistive memories. As already mentioned above, the invention is of course not limited to this particular application and it also applies to volatile resistive memories.

[0008] Although non-volatile memory (NVM) technologies, for "Non-Volatile While resistive NVMs such as magnetic RAM (MRAM), phase change RAM (PCRAM), oxide resistive RAM (OxRAM), and resistive RAM (RRAM) are promising candidates for bringing non-volatility to data storage circuits, low power consumption, high-speed access, high densities, and scalability, resistive NVMs suffer from poor read reliability due to technology scaling and resulting issues such as leakage currents and increasing process variations.

[0009] Although Spin Transfer Torque MRAM (STT-MRAM) memories are considered as an alternative to overcome the scaling problems of microelectronic technologies, they face a circuit design problem to maintain sufficient read reliability due to their low supply voltage, low read current and increasing process variations. In recent years, the design of detection circuits capable of overcoming the degradation of read efficiency has become critical for the implementation of STT-MRAM in the nodes of deep-submicrometer technologies.

[0010] To address the problems of low read reliability induced by offset, various detection techniques and topologies have been proposed. Conventional detection circuits are composed of a detection circuit and a lock-in sense amplifier.

[0011] In the OC-VLSA (Offset Cancellation - Voltage Latched Sense Amplifier) solution, a voltage-locked sense amplifier with offset cancellation is proposed. A compensated comparator is used to lock the detected voltage. It stores the threshold voltages on coupling capacitors to reduce the impact of the input offset voltage. Following this sense amplifier is a DSTA-VLSA (Double Switches and Transmission gate Access transistors - VLSA) used with a SDSC (Source Degeneration Sensing Circuit). The SDSC converts the current applied to the magnetic tunnel junction (MTJ) into a voltage difference, then the previously generated signal is amplified via a PCL (PMOS Cross-coupled Latch) and finally locked using the DSTA-VLSA to generate a digital signal.This conventional sense amplifier suffers from a high input-referred offset voltage caused by process variations during the lock-in phase in the advanced nodes.

[0012] Several lock-in (or "latched-based sense amplifiers" recently proposed for STT-MRAMs: - the LOC-SA solution (for “Latch Offset Cancellation - Sense Amplifier” in English), described in the following publication: “Song, T. Na, J. Kim, JP Kim, SH Kang, and S.-O. Jung, “Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 7, pp. 1776-1784, Jul 2015 »; - the OCHS-SA solution (for “Offset-Compensated High-Speed - Sense Amplifier” in English), described in the following publication: “DG Lee and SG Park, “STT-MRAM read-circuit with improved offset cancellation,” Journal of Semiconductor Technology and Science, vol. 17, no. 3, pp. 347-353, 2017”; and - the IORC solution (for “Improved Offset Read Circuit” in English), described in the following publication: “L. Bagheriye, S. Toofan, R. Saeidi, and F. Moradi, “Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 6, pp. 1051-1058,2018”.

[0013] The LOC-SA solution, illustrated in [Fig.9], is a lock-in and offset-cancelling sense amplifier. Its readout mode is based on four phases consisting of equalize (PI), develop (P2), compare (P3) and lock (P4). The purpose of PI is to equalize Vdata and Vref by short-circuiting the two outputs to improve the detection speed and then compare Vref to Vdata during the P2 phase by the saturation currents of transistors M1, M2, M5 and M6. The signal is amplified without any offset added at P3 to finally be locked and thus produce a digital output. This architecture fulfills several functions. It merges the SDSC, PCL and DSTA-VLSA mentioned above.

[0014] The OCHS-SA solution, illustrated in [Fig. 10], is an offset-compensated high-speed sense amplifier. Its topology is similar to that of the LOC-SA. It performs the sense operation in three phases: precharge (PI), evaluation (P2), and latching (P3). During the precharge phase, the bit lines are biased by transistors M1 and M2 connected by diodes. Similar to the LOC-SA, the evaluation or development phase (P2) uses the positive feedback mechanism of the PCL to amplify the bit line voltage difference. Since the sense margin is large enough, the performance degradation due to mismatch between PMOS loads can be mitigated. The latching phase P3 amplifies the voltage difference developed in P2 to provide digital signals.

[0015] The main interest of the LOC-SA and OCHS-SA architectures, besides the fact that they offer a compact solution, is their robustness against mismatching between devices during the amplification phase by the PCL. However, they still suffer from mismatching during the signal development stage (P2) where, if the mismatch is large enough, the sign of the voltage difference produced can be reversed, thus producing an error.

[0016] The IORC solution, illustrated in [Fig. 11], is an improved offset-cancelling read circuit. In the context of offset cancellation, the IORC solution proposes an architecture in which the mismatch information is stored in a capacitor. This has the advantage of canceling the offset in the signal development phase and in the signal amplification phase. Based on the same latching topology as in the previously described work, the read operation consists of four phases. In the first stage, identical currents, from identical transistors used as current sources, are supplied to the two connected reference cells. The voltage difference due to the device mismatch between the identical references is stored in a capacitor. In the second stage, the capacitor is disconnected and the data cell is connected.Current sources M3 and M4 provide currents as in the first phase. The difference between the generated voltages, corrected by the mismatch stored in the capacitor, is amplified by the positive feedback of the PCL during the third phase. Finally, the preamplified signal is detected by the latch and produces a digital output. Longer detection times and high power consumptions are reported in this architecture due to the storage of the mismatch in the capacitor.

[0017] On reading the above, it is understood that there is today a need for a sense amplifier for resistive memories, which offers better results than known solutions.

[0018] In other words, there is a need for a sense amplifier that has the advantages of detection reliability, compact silicon area, low power consumption (low power), fast detection time (high speed), and efficient compensation for offset resulting from mismatch effects. 3. SUMMARY

[0019] In one embodiment of the invention, there is provided a read circuit comprising a read amplifier configured and controlled by a control unit to amplify and latch a data signal read, via a bit line, in a memory cell of a resistive memory, the memory cell having a variable resistance. The read amplifier comprises: - a first branch comprising first and second transistors mounted to form a first logic inverter, and whose input electrodes are connected, directly or not, to a power supply and to ground respectively; - a second branch comprising third and fourth transistors mounted to form a second logic inverter, and whose input electrodes are connected, directly or indirectly, to the power supply and to ground respectively; - a capacitor connecting an output of the first logic inverter with an input of the second logic inverter; - a set of switches comprising: a first switch connecting the control electrode and the output electrode of the first transistor; a second switch connecting the control electrode and the output electrode of the third transistor; a third switch connecting the control electrode of the first transistor and the output electrode of the third transistor; a fourth switch connecting the variable resistor, via the bit line, to the input electrode of one of the transistors which is located on one of the first and second branches; and a fifth switch connecting said input electrode of one of the transistors to a first end of a first reference resistor, a second end of which is connected to a given element of the group consisting of the power supply and the ground; - a second reference resistor, of the same value as the first reference resistor, and having a first end connected to said given element of the group consisting of the power supply and the ground, and a second end connected to the input electrode of another of the transistors which is located on the other of the first and second branches.

[0020] Furthermore, the control unit is configured to control the switches according to an operation in successive phases comprising: a first phase in which the first, second and fifth switches are closed and the third and fourth switches are open; a second phase distinguished from the first phase in that the second and fifth switches are open and the fourth switch is closed; and a third phase distinguished from the second phase in that the first switch is open and the third switch is closed, making it possible to recover an amplified output signal locked on an output of the second logic inverter.

[0021] Thus, the proposed solution offers a completely new and inventive approach. Indeed, the proposed read amplifier has a particular structure comprising: two branches with in each two transistors mounted to form a logic inverter (therefore one logic inverter per branch); a capacitor connecting the output of the logic inverter of the first branch with the input of the logic inverter of the second branch; two reference resistors and at least five switches.

[0022] An essential characteristic of this structure is that the variable resistor (also called "data resistor") and the two reference resistors (respectively denoted Rdata, Rrefo and Rrefi in the figures described below) are connected to the input electrode of one of the four aforementioned transistors (i.e. the source in the case of a field effect transistor or the emitter in the case of a bipolar transistor).More precisely, the variable resistor (Rdata) and the first reference resistor (R refi) are connected (via the fourth and fifth switches respectively) to the input electrode of one of the transistors of one of the two branches and the second reference resistor (Rrefo) is connected to the input electrode of one of the transistors of the other of the two branches; furthermore the variable resistor (Rdata) and the two reference resistors (Rrefl and Rreffl) all have one end connected to ground (see the first and second configurations discussed below) or to the power supply (see the third and fourth configurations discussed below).In other words, the variable resistor (Rdata) and the first reference resistor (Rrefi) are connected in series with the two transistors of the logic inverter of one of the two branches, and the second reference resistor (Rrefo) is connected in series with the two transistors of the logic inverter of the other of the two branches.

[0023] This is a distinctive feature compared to the known LOC-SA, OCH-SA and IORC solutions, in which the variable resistor (and a reference resistor if there are two) is (are) connected to the output electrode of one of the transistors of one of the two branches and the other reference resistor is connected to the output electrode of one of the transistors of the other of the two branches. By output electrode is meant the drain in the case of a field effect transistor or the collector in the case of a bipolar transistor. For example, in the LOC-SA and OCH-SA solutions of Figures 9 and 10. the variable resistor Rdata is connected to the output electrode of transistors M1 and M5 and the reference resistor Rref is connected to the output electrode of transistors M2 and M6. Similarly, in the IORC solution of [Fig.l 1], the variable resistor Rdata and the first reference resistor Rref0 are connected to the output electrode of transistors M3 and Ml and the second reference resistor R refi is connected to the output electrode of transistors M4 and M2. In the sense amplifiers of these known solutions, a high bias current is then required, and a small signal is obtained, which leads to limitations in terms of detection margins, power consumption and speed.

[0024] On the contrary, with the aforementioned distinctive feature (variable resistor and reference resistors connected across the input electrodes of the transistors), no additional branch is needed to connect the resistors, which allows to achieve a reduction in power consumption. Power consumption is also made lower thanks to the recycling of current within the particular structure proposed, since the metastability current of the logic inverter (of one of the branches) is used to bias the detected resistance (and connected to the other branch). In addition, by connecting resistors to the input electrode of a transistor (e.g. the source of a MOS transistor), the latter acts as an analog amplifier, which improves both the speed and the detection margins (for reading).

[0025] Another essential characteristic of the proposed structure is that the multi-phase operation, made possible by the switches, makes it possible to obtain a reading with high detection margins and fast detection phases.

[0026] Yet another essential characteristic of the invention is that the capacitor makes it possible to cancel the effects of mismatch on the structure and the resulting degradation of reading reliability.

[0027] In summary, the sense amplifier architecture that is proposed for reading resistive memories has the advantages of compact silicon area, low power consumption, fast detection time and cancellation of mismatch effects (offset compensation).

[0028] In a particular implementation, the second phase is composed of two successive sub-phases: - a first sub-phase distinguished from the first phase in that the second switch is open; and - a second sub-phase distinguished from the first sub-phase in that the fifth switch is open and the fourth switch is closed.

[0029] The first sub-phase ensures that the clock does not overlap. It is a sub-phase for equalizing the second logic inverter (right branch in the figures described below), the latter remaining balanced in its metastable state.

[0030] It should be mentioned that i) the time required for the first sub-phase is negligible since it is sufficient to have non-overlapping phases to guarantee the equalization operation, ii) the detection speed (during the second sub-phase that follows) is improved by equalizing the input and output voltages of the second inverter.

[0031] Because the second phase is composed of two sub-phases, this particular implementation is also called, in the remainder of the description, “mode of operation in four successive phases”, the two sub-phases of the aforementioned second phase and the aforementioned third phase then being renamed second, third and fourth phases respectively.

[0032] In a first particular configuration of the resistors: the fourth switch connects the variable resistor, via the bit line, to the input electrode of the second transistor located on the first branch; the fifth switch connects the input electrode of the second transistor to the first end of the first reference resistor, the second end of which is connected to ground; and the second reference resistor has its first end connected to ground and its second end connected to the input electrode of the fourth transistor located on the second branch.

[0033] This first configuration is suitable for reading a resistive memory whose variable resistances of the different memory cells are connected to ground.

[0034] In a second particular configuration of the resistors: - the fourth switch connects the variable resistor, via the bit line, to the input electrode of the fourth transistor located on the second branch; - the fifth switch connects the input electrode of the fourth transistor to the first end of the first reference resistor, the second end of which is connected to ground; and - the second reference resistor has its first end connected to ground and its second end connected to the input electrode of the second transistor located on the first branch.

[0035] This second configuration is also suitable for reading a resistive memory whose variable resistances of the different memory cells are connected to ground.

[0036] In a third particular configuration of the resistors: - the fourth switch connects the variable resistor, via the bit line, to the input electrode of the third transistor located on the second branch; - the fifth switch connects the input electrode of the third transistor to the first end of the first reference resistor, the second end of which is connected to the power supply; and - the second reference resistor has its first end connected to the power supply and its second end connected to the input electrode of the first transistor located on the first branch.

[0037] This third configuration is suitable for reading a resistive memory whose variable resistances of the different memory cells are connected to the power supply. Said power supply may be a voltage source or a current source without altering operation.

[0038] In a fourth particular configuration of the resistors: - the fourth switch connects the variable resistor, via the bit line, to the input electrode of the first transistor located on the first branch; - the fifth switch connects the input electrode of the first transistor to the first end of the first reference resistor, the second end of which is connected to the power supply; and - the second reference resistor has its first end connected to the power supply and its second end connected to the input electrode of the third transistor located on the second branch.

[0039] This fourth configuration is also suitable for reading a resistive memory whose variable resistances of the different memory cells are connected to the power supply.

[0040] According to a particular characteristic, the reading circuit further comprises a bit line precharging circuit comprising: - a third branch, of similar structure to the first branch and comprising fifth and sixth transistors, the control and output electrodes of the fifth and sixth transistors being directly connected to each other; and - a sixth switch connecting the third branch to the bit line

[0041] and the control unit is configured to control the switch as the fifth switch.

[0042] This makes it possible to improve (reduce) the reading time, because from the end of the first phase, the potential of the bit line is close to its final value.

[0043] According to a particular characteristic, each of the first and second branches comprises an additional switch always closed to compensate, in number of switches closed concurrently, a selection switch of said memory cell.

[0044] Thus, this additional switch makes it possible to increase the symmetry of the structure and therefore to reduce the offset to be compensated.

[0045] According to a particular characteristic, that of the first and second branches to which the fourth and fifth switches are not connected comprises another additional switch which is always closed to compensate, in terms of the number of switches closed concurrently, for one of the fourth and fifth switches.

[0046] These other additional switches also make it possible to increase the symmetry of the structure and therefore to reduce the offset to be compensated.

[0047] According to a particular characteristic, the control unit is formed by, or included in, a resistive memory controller.

[0048] Thus, the resistive memory controller is adapted to control the switches as desired.

[0049] According to a particular characteristic, the first and third transistors are of P type and the second and fourth transistors are of N type.

[0050] Thus, the proposed solution can be implemented with both field effect transistors and bipolar transistors.

[0051] According to a particular characteristic, the input electrode, the output electrode and the control electrode correspond respectively: - at the source, drain and gate in the case of a field effect transistor; and - to the emitter, the collector and the base in the case of a bipolar transistor.

[0052] According to a particular characteristic, the resistive memory is of the non-volatile type.

[0053] The performance of the proposed solution is particularly interesting for an application to the reading of a non-volatile type resistive memory. But as already mentioned above, the proposed solution also applies to the reading of a volatile type resistive memory.

[0054] In another embodiment of the invention, there is provided a memory device comprising a resistive memory having a capacity of (m+l)x(n+l) bits and based on the use of (m+1) bit lines each allowing access to (n+1) memory cells. The memory device comprises (m+1) read circuits (such as the one presented above, in any of its embodiments), sharing a common control unit, each of the (m+1) read circuits comprising a sense amplifier configured and controlled by the common control unit to amplify and latch a data signal read, via a particular one of the (m+1) bit lines, into one of the (n+1) memory cells associated with the particular bit line.

[0055] Because it comprises (m+1) read circuits such as the one discussed above (in any of its different embodiments), the advantages of such a memory device are those already discussed above for the read circuit (and the read amplifier it contains).

[0056] In another embodiment of the invention, there is provided a memory device comprising a resistive memory having a capacity of (m+l)x(n+l) bits and based on the use of (m+1) bit lines each allowing access to (n+1) memory cells. The memory device comprises a read circuit (such as that presented above, in any of its embodiments) and an (m+1) to 1 multiplexer for selectively connecting one of the (m+1) bit lines to the sense amplifier included in the read circuit, the sense amplifier being controlled by the control unit included in the read circuit to amplify and latch a data signal read, via the connected one of the (m+1) bit lines, in one of the (n+1) memory cells associated with the connected bit line.

[0057] In this variant, because it comprises a (single) reading circuit such as that discussed above (in any of its various embodiments), the advantages of such a memory device are those already discussed above for the read circuit (and the read amplifier it contains). 4. LIST OF FIGURES

[0058] Other characteristics and advantages of the invention will appear on reading the following description, given by way of illustrative and non-limiting example, in relation to the appended drawings, in which:

[0059] [Fig-1] [Fig.l] shows the structure of a reading amplifier according to a first embodiment of the invention;

[0060] [Fig.2A]

[0061] [Fig.2B]

[0062] [Fig.2C] Figures 2A to 2C illustrate a first mode of operation, in three successive phases, of the reading amplifier of [Fig.l];

[0063] [Fig.3A] [Fig.3A] illustrates a first variant of the sense amplifier of [Fig.l], including a bit line precharge circuit and additional switches providing symmetry, and illustrating the connection to ground of the variable resistances of the different memory cells associated with the bit line;

[0064] [Fig.3B] [Fig.3B] illustrates a second variant of the sense amplifier of [Fig.l], which differs from the first variant of [Fig.3A] in that several bit lines are connected to the sense amplifier using a multiplexer;

[0065] [Fig.4A] [Fig.4A] shows the structure of a read amplifier according to a second embodiment of the invention;

[0066] [Fig.4B] [Fig.4B] shows the structure of a read amplifier according to a third embodiment of the invention;

[0067] [Fig.4C] [Fig.4C] shows the structure of a read amplifier according to a fourth embodiment of the invention;

[0068] [Fig.5] [Fig.5] illustrates a variant of the sense amplifier of [Fig.4C], including a bit line precharge circuit and additional switches providing symmetry, and illustrating the connection to the power supply of the variable resistors of the various memory cells associated with the bit line;

[0069] [Fig.6A] [Fig.6A] illustrates a memory device according to a first embodiment of the invention, comprising m+1 sense amplifiers according to the first variant of [Fig.3A] and operating in three phases as illustrated in Figures 2A to 2C;

[0070] [Fig.6B] [Fig.6B] illustrates a memory device according to a second embodiment of the invention, comprising a single read amplifier (according to the second variant of [Fig.3B], i.e. associated with a multiplexer) and operating in three phases as illustrated in FIGS. 2A to 2C;

[0071] [Fig.7A]

[0072] [Fig.7B]

[0073] [Fig.7C]

[0074] [Fig.7D] Figures 7A to 7D illustrate a second mode of operation, in four successive phases, of the reading amplifier of [Fig.l];

[0075] [Fig.8] [Fig.8] illustrates a memory device according to a second embodiment of the invention, comprising m+1 sense amplifiers according to the variant of [Fig.5] and operating in four phases as illustrated in Figures 7A to 7D;

[0076] [Fig.9] [Fig.9], already described in relation to the prior art, presents the structure of a detection amplifier according to the known LOC-SA solution;

[0077] [Fig. 10] [Fig. 10], already described in relation to the prior art, shows the structure of a detection amplifier according to the known OCHS-SA solution; and

[0078] [Fig. 11] [Fig. 11], already described in relation to the prior art, presents the structure of a detection amplifier according to the known IORC solution. 5. DETAILED DESCRIPTION

[0079] In all figures of this document, identical elements and steps are designated by the same numerical reference.

[0080] In the remainder of the description, the circuits described for illustrative purposes comprise MOS field effect transistors (PMOS and NMOS). It is clear, however, that the present invention is not limited to this type of transistor, and circuits equivalent in terms of operation can be produced with field effect transistors (of P and N types) other than MOS or even with bipolar transistors (of PNP or NPN types).

[0081] The transition from an implementation with field effect transistors to an implementation with bipolar transistors can be achieved simply by considering that the input electrode, the output electrode and the control electrode of a transistor correspond respectively: - at the source, drain and gate in the case of a field effect transistor; and - to the emitter, the collector and the base in the case of a bipolar transistor.

[0082] It is recalled that, conventionally, when two complementary transistors, of P and N types respectively, are mounted to form a logic inverter: the input electrode of the first transistor is connected to the power supply, the output electrodes of the two transistors are connected directly to each other, the input electrode of the second transistor is connected to ground, and the control electrodes of the two transistors are connected directly to each other.

[0083] We now present, in relation to [Fig.l], a reading amplifier according to a first embodiment of the invention.

[0084] The sense amplifier is configured, and controlled by a control unit (as detailed below), to amplify and latch a data signal read, via a bit line, in a memory cell of a resistive memory, the memory cell having a variable resistor Rdata. In a particular implementation, the resistive memory is of the non-volatile type. In a variant, the resistive memory is of the volatile type.

[0085] The sense amplifier comprises a first branch (left branch) comprising a PMOS type transistor M3 and an NMOS type transistor Mi mounted to form a first logic inverter. Thus, the source of the transistor M3 is connected to the power supply Vdd, the drains of the two transistors M3 and Mi are connected directly to each other (this is the output of the first logic inverter), the source of the transistor Mi is connected indirectly to ground either via the switch S4 and the resistor Rdata or via the switch S5 and the resistor Rrefi (elements described below), and the gates of the two transistors M3 and Mi are connected directly to each other (this is the input of the first logic inverter). In this implementation, the power supply is a voltage source, but in a variant it can be a current source without altering the operation.

[0086] It comprises a second branch (right branch) comprising a PMOS type transistor M4 and an NMOS type transistor M2 mounted to form a second logic inverter. Thus, the source of the transistor M4 is connected to the power supply Vdd, the drains of the two transistors M4 and M2 are connected directly to each other (this is the output of the second logic inverter and also the output of the sense amplifier, denoted Vout), the source of the transistor M2 is indirectly connected to ground via the resistor Rreffl (element described below), and the gates of the two transistors M4 and M2 are connected directly to each other (this is the input of the second logic inverter).

[0087] A capacitor Co connects the output of the first logic inverter with the input of the second logic inverter.

[0088] The reading amplifier also comprises: - a switch Si connecting the gate and the drain of transistor M3, i.e. connecting the input and the output of the first logic inverter; - a switch S2 connecting the gate and the drain of the transistor M4, i.e. connecting the input and the output of the second logic inverter; - a switch S3 connecting the gate of transistor M3 and the drain of transistor M4, i.e. connecting the input of the first logic inverter and the output of the second logic inverter; - a switch S4 connecting one end of the variable resistor Rdata, via the bit line, to the source of the transistor Mi (in this configuration, the other end of the variable resistor Rdata is connected to ground); - a switch S5 connecting the source of the transistor Mi to a first end of a first reference resistor Rrefi, a second end of which is connected to ground; and - a second reference resistor Rreffl, of the same value as the first reference resistor, and having a first end connected to ground and a second end connected to the source of transistor M2.

[0089] The read amplifier is controlled by a control unit. More specifically, the control unit is configured to control the switches S1 to S5 according to a successive phase operation.

[0090] In [Fig. 1], an annotation in the format “ ” is present near each in switch to specify the phase(s) of rank(s) "x" during which this switch is closed. For example, the annotation "4>w" near the switch Si specifies that it is closed during phases 1 and 2.

[0091] As detailed below in relation to [Fig.6A], the control unit is preferably formed by, or included in, the controller 61 of the resistive memory 62. More generally, the control unit comprises a reprogrammable computing machine (for example a computer, a processor, a microcontroller, etc.) executing a program comprising a sequence of instructions, or a dedicated computing machine (for example a set of logic gates such as an FPGA or an ASIC, or any other hardware module).

[0092] We now present, in relation to Figures 2A to 2C, a first mode of operation, in three successive phases (P1, P2 and P3), of the reading amplifier of [Fig. 1]. In this case, the control unit is configured to control the switches S1 to S5 as follows.

[0093] In the first phase PI, illustrated in [Fig.2A], the switches S1, S2 and S5 are closed and the switches S3 and S4 are open. Thus, each of the two logic inverters has its input connected to its output and the reference resistors Rrefi and Rref0 are connected to the source of the transistors Mi and M2 respectively. The offset of the structure is stored across the capacitor Co and the two logic inverters are biased in their amplification zone.

[0094] The second phase P2, illustrated in [Fig.2B], differs from the first phase in that switches S2 and S5 are open and switch S4 is closed. Thus, opening switch S2 allows the second logic inverter to be configured in amplification mode. The variable resistor Rdata (resistance to be evaluated) is connected in place of the reference resistor Rrefi. The signal obtained by this connection of the variable resistor Rdata is transferred, by the left branch and the coupling capacitor Co, to the input of the second logic inverter (output inverter) in order to be amplified by the gain of the latter.

[0095] The third phase P3, illustrated in [Fig.2C], differs from the second phase in that the switch Si is open and the switch S3 is closed, making it possible to recover an amplified output signal locked to the output of the second logic inverter (which is also the output Vout of the sense amplifier). Indeed, such a connection of the two logic inverters makes it possible to develop a logic signal in the memory point thus formed.

[0096] Thus, the proposed sense amplifier makes it possible to determine whether the unknown variable resistance Rdata has a value greater or less than the value of the reference resistance Rref0. Its structure is notably characterized by the fact that the resistors Rdata and Rrefo are connected to the sources of the transistors Mi and M2 respectively, in order to amplify the signal represented by the difference between Rdata and Rreffl. Its operation is characterized by the control phases of the switches in order to reduce the reading errors by compensating for the electronic offset of the sense amplifier and to increase the reading margins.

[0097] [Fig.3A] illustrates a first variant of the sense amplifier of [Fig.l], including a circuit (referenced 30) for precharging the bit line (referenced “Bitline”). The precharging circuit 30 comprises a third branch, of similar structure to the first branch and comprising transistors M3a and M[a. The gate and the drain of the transistors M3a and M[a are directly connected to each other. The drains of the transistors M3a and Mu are directly connected to each other. The gates of the transistors M3a and Mia are directly connected to each other. The source of the transistor M3a is connected to the power supply Vdd. The precharging circuit 30 also comprises a switch S6 connecting the third branch (and more precisely the source of the transistor M ia) to the bit line during the first phase (it is closed during the same phase as the switch S5).The precharge circuit allows to improve (reduce) the reading time by using a structure identical to the left branch of the sense amplifier, so that the potential on the bit line is, from the end of the first PI phase, close to its final value.

[0098] According to a particular characteristic, also illustrated in [Fig.3A], that of the first and second branches on which the switches S4 and S5 are not connected (i.e. the right-hand branch in the configuration of [Fig.3A]) comprises an additional switch always closed S7 to compensate, in number of switches closed concurrently, one of the switches S4 and S5 (only one of the two being closed in each phase). The additional switch S7 makes it possible to increase the symmetry of the structure and to reduce the offset to be compensated. It can be implemented independently of the precharging circuit.

[0099] According to another particular characteristic, also illustrated in [Fig.3A], each of the first and second branches may include an additional switch (also called a balancing switch) always closed (referenced S8 for the left branch and S9 for the right branch) to reduce mismatching, by making the number of switches closed concurrently in each of the branches of the sense amplifier equal. Indeed, as illustrated in [Fig.3A], each bit line of a memory is associated with (n+1) memory cells and each of the memory cells has a variable resistor (one end of which is connected to ground, in this configuration). For a bit line, there are therefore (n+1) variable resistors which are noted Rdata0 to Rdatan in [Fig.3A]. Each memory cell (and therefore each variable resistor) can be selected for reading using a selection switch associated with it.For a bit line, there are therefore (n+1) selection switches which are noted Sel0 to Seln on [Fig.3A]. Only one is closed at a time. In number of switches closed concurrently on a branch, switch S9 of the right branch therefore compensates switch S8 of the left branch when switch S5 is closed or one of the switches Sel0 to Seln of the left branch when switch S4 is closed. The additional switches S8 and S9 also make it possible to increase the symmetry of the structure and to reduce the offset to be compensated. They can be implemented independently of the precharge circuit.

[0100] [Fig.3B] illustrates a second variant of the sense amplifier of [Fig.l], which differs from the first variant of [Fig.3A] in that m+1 bit lines (referenced "Bitline_0" to "Bitline_m") are connected to the sense amplifier using an m+1 to 1 multiplexer (referenced 31). In this variant, optionally, two additional balancing switches may be added in series with Rref0 and Rrefi respectively, in order to compensate for the closed internal switch of the multiplexer.

[0101] The second variant also differs from the first in that the switches S8, S9 and Sel0 to Seln are connected as close as possible to ground for better performance.

[0102] [Fig.4A] shows the structure of a read amplifier according to a second embodiment of the invention. This second embodiment differs from the first, that of [Fig.1] in that: - the variable resistor Rdata and the reference resistor Rrefi, as well as the associated switches S4 and S5, are located on the right branch and are connected at one end to the source of the transistor M2 (via their associated switches) and at the other end to ground; and - the reference resistor Rrefo is located on the left branch and is connected at one end to the source of the transistor Mi and at the other end to the mass.

[0103] [Fig.4B] shows the structure of a read amplifier according to a third embodiment of the invention. This third embodiment differs from the first, that of [Fig.1] in that: - the variable resistor Rdata and the reference resistor Rrefi, as well as the associated switches S4 and S5, are located on the right branch and are connected at one end to the source of the transistor M4 (via their associated switches) and at the other end to the power supply Vdd; and - the reference resistor Rref0 is located on the left branch and is connected at one end to the source of transistor M3 and at the other end to the supply Vdd.

[0104] [Fig.4C] shows the structure of a read amplifier according to a fourth embodiment of the invention. This fourth embodiment differs from the first, that of [Fig.1] in that: - the variable resistor Rdata and the reference resistor Rrefi, as well as the associated switches S4 and S5, are located on the left branch and are connected at one end to the source of the transistor M3 (via their associated switches) and at the other end to the power supply Vdd; and - the reference resistor Rrefo is located on the right branch and is connected at one end to the source of transistor M4 and at the other end to the supply Vdd.

[0105] [Fig.5] illustrates a variant of the sense amplifier of [Fig.4C], including a circuit (50) for precharging the bit line and additional switches (S7, S8 and S9) providing symmetry, and illustrating the connection to the Vdd supply of the variable resistors (Rdatao to Rdatan) of the different memory cells associated with the bit line.

[0106] The precharge circuit 50 differs from that referenced 30 in [Fig.3A] in that the switch S6 connects the source of the transistor M3a to the bit line during the first phase (it is closed during the same phase as the switch S5) and in that the source of the transistor Mu is connected to ground. The operation of the precharge circuit 50 is easily deduced from that referenced 30 in [Fig.3A]. It is therefore not described in detail.

[0107] The role of the additional switches S7, S8 and S9 is the same as in the case of [Fig.3A]. It is therefore not described again.

[0108] It will be noted that each of the memory cells has a variable resistor (R data0 to Rdatan) one end of which is connected to the bit line (via one of the selection switches Sel0 to Seln) and the other end is connected to the power supply Vdd.

[0109] [Fig.6A] illustrates a memory device 60 according to a first embodiment of the invention. It comprises a resistive memory 62, a memory controller 61 and a plurality of sense amplifiers.

[0110] The resistive memory 62 has a capacity of (m+l)x(n+l) bits and is based on the use of (m+1) bit lines (referenced "Bitline_0" to "Bitline_m") each allowing access to (n+1) memory cells. Each of the (n+1) memory cells associated with a bit line has a variable resistor, one end of which is connected to ground, in this configuration identical to that of [Fig.3A]. For a bit line, there are therefore (n+1) variable resistors which are denoted R data0 to R datan, as in [Fig.3A]. Each memory cell (and therefore each variable resistor) can be selected for reading using a selection switch associated with it. For a bit line, there are therefore (n+1) selection switches which are denoted Sel0 to Seln as in [Fig.3A].

[0111] For the sake of simplification, only one sense amplifier is shown in [Fig.6A]. It is referenced 63, as well as “Sense Amplifier_0” to show that it is the one associated with the bit line referenced “Bitline_0”. In this example, it is identical to that of [Fig.3A].

[0112] Common to all bit lines, the memory controller 61 (called above “control unit” and which is here common to the (n+1) reading amplifiers) generates: - the signals (referenced 64i to 64n) for controlling the selection switches (referenced Sel0 to Seln) included in the resistive memory 62 (to select one memory cell at a time on each bit line); and - the signals (referenced 651 to 654) for controlling the switches (referenced S1 to S6; the switches from S7 to S9 are not controlled because they are always closed) included in each reading amplifier, for three-phase operation (as described above with figures 2A to 2C).

[0113] Variants of [Fig.6A] can be easily obtained by replacing the sense amplifier 63 (based on the embodiment of [Fig.3A] which is a variant of [Fig.l]) by a sense amplifier according to one of the other embodiments described above with Figures 4A, 4B, 4C and 5.

[0114] [Fig.6B] illustrates a memory device 60' according to a second embodiment of the invention. It comprises a resistive memory 62, a memory controller 61, a (single) sense amplifier 63 and a multiplexer 31. The resistive memory 62 and the memory controller 61 are identical to those of [Fig.6A]. In this example, the sense amplifier 63 is identical to that of [Fig.3B]. The m+1 to 1 multiplexer (referenced 31) makes it possible to selectively connect one of the m+1 bit lines (referenced “Bitline_0” to “Bitline_m”) to the sense amplifier.

[0115] We now present, in relation to Figures 7A to 7D, a second mode of operation, in four successive phases (PI, P2a, P2b and P3), of the reading amplifier of [Fig.l].

[0116] This second mode of operation differs from the first mode (described above with figures 2A to 2C) in that the second phase P2 of the first mode (described above with [Fig.2B]) is here broken down into two successive sub-phases P2a and P2b.

[0117] The first phase PI, illustrated in [Fig.7A], is identical to that described above with [Fig.2A]. It is not described again.

[0118] The second phase P2a (which corresponds to the first sub-phase mentioned above), illustrated in [Fig.7B], differs from the first phase PI in that the switch S2 is open, allowing the second logic inverter to be configured in amplification mode. It is as short as possible and is intended to guarantee non-clock overlap.

[0119] The third phase P2b (which corresponds to the aforementioned second sub-phase), illustrated in [Fig.7C], differs from the second phase P2a (first sub-phase) in that the switch S5 is open and the switch S4 is closed. Thus, the variable resistor R data (resistance to be evaluated) is connected in place of the reference resistor Rrefi. The signal obtained by this connection of the variable resistor Rdata is transferred, by the left branch and the coupling capacitor Co, to the input of the second logic inverter (output inverter) in order to be amplified by the gain thereof.

[0120] The fourth phase P3, illustrated in [Fig.7D], is identical to the third phase of the first embodiment, described above with [Fig.2C]. It is not described again.

[0121] [Fig.8] illustrates a memory device 80 according to a second embodiment of the invention. It comprises a resistive memory 62 (identical to that of [Fig.8]), a memory controller 81 and a plurality of sense amplifiers.

[0122] For the sake of simplification, only one sense amplifier is shown in [Fig.8]. It is referenced 83, as well as “Sense Amplifier_0” to show that it is the one associated with the bit line referenced “Bitline_0”. Structurally, it is identical to that referenced in [Fig.6A]. However, its operation differs from it in that it receives control signals from the switches for four-phase operation (as described above with Figures 7A to 7D).

[0123] Thus, in a manner common to all the bit lines, the memory controller 81 (called above “control unit” and which is here common to the (n+1) reading amplifiers) generates: - the signals (referenced 64i to 64n, as in [Fig.6A]) for controlling the selection switches (referenced Sel0 to Seln) included in the resistive memory 62 (to select one memory cell at a time); and - the signals (referenced 851 to 855) for controlling the switches (referenced S1 to S6; the switches from S7 to S9 are not controlled because they are always closed) included in each reading amplifier, for four-phase operation.

[0124] Variants of [Fig.8] can be easily obtained by replacing the sense amplifier 83 (based on the embodiment of [Fig.3A] which is a variant of [Fig.l]) with a sense amplifier according to one of the other embodiments described above with Figures 4A, 4B, 4C and 5.

Claims

Claims

1. A read circuit comprising a read amplifier and a control unit, the amplifier being configured and controlled by the control unit to amplify and latch a data signal read, via a bit line, in a memory cell of a resistive memory, the memory cell having a variable resistance (Rdata), characterized in that the read amplifier comprises: - a first branch comprising first and second transistors (M3, Mi) mounted to form a first logic inverter, and whose input electrodes are connected, directly or not, to a power supply (Vdd) and to ground respectively; - a second branch comprising third and fourth transistors (M4, M2) mounted to form a second logic inverter, and whose input electrodes are connected, directly or not, to the power supply and to ground respectively; - a capacitor (Co) connecting an output of the first logic inverter with an input of the second logic inverter; - a first reference resistance (Rrefi); - a set of switches comprising: a first switch (Si ) connecting the control electrode and the output electrode of the first transistor (M3); a second switch (S2) connecting the control electrode and the output electrode of the third transistor (M4); a third switch (S3) connecting the control electrode of the first transistor (M3) and the output electrode of the third transistor (M4); a fourth switch (S4) connecting the variable resistor (Rdata), via the bit line, to the input electrode of one of the transistors (Mi to M4) which is located on one of the first and second branches; and a fifth switch (S5) connecting said input electrode of one of the transistors to a first end of the first reference resistor (Rrefi), a second end of which is connected to a given element of the group consisting of the power supply and the ground; - a second reference resistor (Rrefo), of the same value as the first reference resistor, and having a first end connected to said given element of the group consisting of the power supply and the ground, and a second end connected to the input electrode of another of the transistors (Mi to M4) which is located on the other of the first and second branches; and in that the control unit is configured to control the switches (S1 to S5) according to an operation in successive phases comprising: a first phase in which the first, second and fifth switches (S2, S5) are closed and the third and fourth switches (S3 and S4) are open; a second phase distinguished from the first phase in that the second and fifth switches (S2, S5) are open and the fourth switch (S4) is closed; and a third phase distinguished from the second phase in that the first switch (S1) is open and the third switch (S3) is closed, making it possible to recover an amplified output signal locked on an output of the second logic inverter.

2. Reading circuit according to claim 1, in which the second phase is composed of two successive sub-phases: - a first sub-phase distinguished from the first phase in that the second switch (S2) is open; and - a second sub-phase distinguished from the first sub-phase in that the fifth switch (S5) is open and the fourth switch (S4) is closed.

3. A read circuit according to claim 1 or 2, wherein: - the fourth switch (S4) connects the variable resistor (Rdata), via the bit line, to the input electrode of the second transistor (Mi) located on the first branch; - the fifth switch (S5) connects the input electrode of the second transistor (Mi) to the first end of the first reference resistor (Rrefi) the second end of which is connected to ground; and - the second reference resistor (Rrefo) has its first end connected to ground and its second end connected to the input electrode of the fourth transistor (M2) located on the second branch.

4. Reading circuit according to claim 1 or 2, wherein: - the fourth switch (S4) connects the variable resistor (Rdata), via the bit line, to the input electrode of the fourth transistor (M2) located on the second branch; - the fifth switch (S5) connects the input electrode of the fourth transistor (M2) to the first end of the first reference resistor (Rrefi) whose second end is connected to ground; and - the second reference resistor (Rrefo) has its first end connected to ground and its second end connected to the input electrode of the second transistor (MJ located on the first branch.

5. A reading circuit according to claim 1 or 2, wherein: - the fourth switch (S4) connects the variable resistor (Rdata), via the bit line, to the input electrode of the third transistor (M4) located on the second branch; - the fifth switch (S5) connects the input electrode of the third transistor (M4) to the first end of the first reference resistor (Rrefi) whose second end is connected to the power supply (Vdd); and - the second reference resistor (Rrefo) has its first end connected to the power supply (Vdd) and its second end connected to the input electrode of the first transistor (M3) located on the first branch.

6. A reading circuit according to claim 1 or 2, wherein: - the fourth switch (S4) connects the variable resistor (Rdata), via the bit line, to the input electrode of the first transistor (M3) located on the first branch; - the fifth switch (S5) connects the input electrode of the first transistor (M3) to the first end of the first reference resistor (Rrefi) whose second end is connected to the power supply (Vdd); and - the second reference resistor (Rrefo) has its first end connected to the power supply (Vdd) and its second end connected to the input electrode of the third transistor (M4) located on the second branch.

7. A reading circuit according to any one of claims 1 to 6, further comprising a bit line precharging circuit comprising: - a third branch, of similar structure to the first branch and comprising fifth and sixth transistors (M3a, Mia), the control and output electrodes of the fifth and sixth transistors (M3a, M[a) being directly connected to each other; and - a sixth switch (S6) connecting the third branch to the bit line and in that the control unit is configured to control the switch (S6) like the fifth switch (S5).

8. Reading circuit according to any one of claims 1 to 7, wherein each of the first and second branches comprises an additional always-closed switch (S8, S9) to compensate, in number of concurrently closed switches, a selection switch of said memory cell (Sel;).

9. Reading circuit according to any one of claims 1 to 8, in which that of the first and second branches to which the fourth and fifth switches (S4, S5) are not connected comprises another additional switch always closed (S7) to compensate, in number of switches closed concurrently, one of the fourth and fifth switches (S4, S5).

10. A read circuit according to any one of claims 1 to 9, wherein the control unit is formed by, or included in, a controller of the resistive memory.

11. A read circuit according to any one of claims 1 to 10, wherein the first and third transistors (M3, M4) are P-type and the second and fourth transistors (Mb M2) are N-type.

12. A readout circuit according to any one of claims 1 to 11, wherein the input electrode, the output electrode and the output electrode control correspond respectively: - to the source, the drain and the gate in the case of a field effect transistor; and - to the emitter, the collector and the base in the case of a bipolar transistor.

13. A reading circuit according to any one of claims 1 to 12, wherein the resistive memory is of the non-volatile type.

14. A memory device comprising a resistive memory having a capacity of (m+l)x(n+l) bits and based on the use of (m+1) bit lines each allowing access to (n+1) memory cells, characterized in that it comprises (m+1) read circuits according to any one of claims 1 to 13, sharing a common control unit, each of the (m+1) read circuits comprising a read amplifier configured and controlled by the common control unit to amplify and latch a data signal read, via a particular bit line among the (m+1) bit lines, in one of the (n+1) memory cells associated with the particular bit line.

15. Memory device comprising a resistive memory having a capacity of (m+l)x(n+l) bits and based on the use of (m+1) bit lines each allowing access to (n+1) memory cells, characterized in that it comprises a read circuit according to any one of claims 1 to 13 and an (m+1) to 1 multiplexer allowing selectively connecting one of the (m+1) bit lines to the read amplifier included in the read circuit, the read amplifier being controlled by the control unit included in the read circuit to amplify and latch a data signal read, via the connected bit line among the (m+1) bit lines, in one of the (n+1) memory cells associated with the connected bit line.

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