OPTICAL BOX WITH ELECTROMAGNETIC SHIELDING

Abstract

Optical integrated circuit package (BT), comprising a support substrate (SUB) comprising a mounting face (FM) and an electrical interconnection network (INTCNX) between the mounting face and contact pads (PAD1, PAD2) located on a lower face (FL) of the support substrate, a cover (CPT) having a side wall (PRLAT) fixed on the mounting face and an upper wall (PRSUP1) comprising a first opening (FNT1), a first optical element (OPT1) fixed on the upper wall of the cover (CPT) and closing the first opening (FNT1), an electromagnetic shielding element (SHLD) embedded in the cover (CPT) and intended to be coupled to a cold supply point (GND) via the interconnection network (INTCNX) and at least one contact pad (PAD1), a first electronic chip (CHP1) mounted on the mounting face (FM) and in optical cooperation with the first optical element (OPT1). Figure for abstract: Fig 1

Description

Title of the invention: OPTICAL BOX WITH ELECTROMAGNETIC SHIELDING

[0001] Embodiments and implementations relate to the field of packaging of integrated circuits, in particular the field of optoelectronics, and more particularly the reduction of electromagnetic interference within an optical integrated circuit package or in its vicinity.

[0002] An optical integrated circuit package typically comprises electronic chips capable of emitting or receiving optical radiation such as a laser for example. A typical electronic chip of this type of package emits stray electromagnetic waves, in addition to the optical radiation, which can propagate outside the optical package. These stray electromagnetic waves cause electromagnetic interference which can degrade and limit the performance of electronic systems in which the optical package is used. Indeed, electromagnetic interference can occur in the vicinity of the optical package and disrupt the operation of the circuits located around this package, in particular the circuits located on the same printed circuit board (usually known by the English term "Printed Circuit Board") as that of the optical package.

[0003] Conversely, the optical housing may be exposed to external parasitic electromagnetic waves, for example waves emitted by some of these circuits, causing electromagnetic interference which may affect the performance of the housing.

[0004] A conventional solution to this interference problem proposes the use of adhesive tapes designed to reduce or even eliminate electromagnetic interference. The adhesive tape, stuck to a wall of the optical package cover, prevents the propagation of electromagnetic waves through this wall. In this way, the electromagnetic waves emitted by the package chip to the outside of the package and the electromagnetic waves generated by circuits outside the package are blocked by the adhesive tape.

[0005] However, it is necessary to fix an adhesive strip, often thick enough to block electromagnetic waves, on each wall of the cover to ensure effective shielding of the housing, which contributes to increasing the size of the housing. This solution can therefore prove complicated to implement in electronic systems for which the management of the space between components is becoming increasingly important.

[0006] There is therefore a need to find a solution to reduce or even eliminate electromagnetic interference in and around the housing while making it compact, for example making it easier to integrate the box into an electronic system.

[0007] According to one aspect, there is provided an optical integrated circuit package, comprising - a support substrate comprising a mounting face and an electrical interconnection network between the mounting face and contact pads located on a lower face of the support substrate, opposite the mounting face, - a cover having a side wall fixed to the mounting face and an upper wall comprising a first opening, the cover defining with the support substrate at least a first cavity, - a first optical element fixed to the upper wall of the hood and closing the first opening.

[0008] The housing comprises according to this aspect also comprises - an electromagnetic shielding element embedded in the cover and intended to be coupled to a cold supply point, for example ground, via the interconnection network and at least one contact pad, -a first electronic chip, for example a chip capable of emitting optical radiation, mounted on the mounting face in said at least one first cavity and in optical cooperation with the first optical element.

[0009] The electromagnetic shielding element, typically made of an electrically conductive material such as copper, forms a Faraday cage around the electronic chip and makes it possible to block electromagnetic waves, for example waves that may be emitted by circuits in the vicinity of the package or those emitted by the electronic chip of the package.

[0010] Similarly, the electromagnetic waves emitted by the electronic chip of the package are blocked by the shielding element and therefore cannot create interference with the circuits in the vicinity of the optical package. The electronic chip is also protected by the electromagnetic shielding element from electromagnetic interference.

[0011] Furthermore, integrating the shielding element into the housing cover makes it possible to make the case more compact.

[0012] Furthermore, the optical package, for example of the LGA type (which is the English acronym for "Land Grid Array" which means "matrix of pads" in French) provides contact pads or pads connected to the interconnection network of the substrate and making it possible to electrically connect the electronic chip to a printed circuit board. It is thus possible to advantageously use some of these contact pads to electrically connect the electromagnetic shielding element to a cold power supply point, for example a ground, and thus obtain the electromagnetic shielding function of the package.

[0013] According to one embodiment, the electromagnetic shielding element is embedded in a molding resin.

[0014] The molding resin makes it possible to protect the electromagnetic shielding element from deterioration due to mechanical shocks or corrosion, for example.

[0015] According to one embodiment, the shielding element also forms at least one inductive element.

[0016] The shielding element advantageously has another function, namely an inductive element function which can be connected to the electronic chip of the package.

[0017] According to one embodiment, the cover comprises an additional wall extending into the first cavity, connected to the side wall and having an additional opening.

[0018] The housing also comprises an additional optical element fixed on the additional wall, closing the additional opening and in optical cooperation with the first optical element and the first electronic chip.

[0019] The additional optical element advantageously comprises a circuit electrically connected to at least one other contact pad by means of electrically conductive connection means embedded in the side wall of the cover and the interconnection network.

[0020] The additional optical element makes it possible to provide an optical function (for example polarization, filtering, lens effect) while making it possible to prevent a failure, such as delamination or breakage of the additional optical element. Indeed, the circuit of the additional optical element makes it possible to detect a failure of the optical element. More particularly, the circuit of the optical element can form with the connection means and the interconnection network a closed circuit in which a current flows continuously in the absence of a failure and is interrupted when the circuit is open, for example when the optical element breaks.

[0021] The circuit of the optical element can therefore be useful for controlling a cut-off of the power supply to the electronic chip so as to prevent it from emitting optical radiation in the event of failure of the additional optical element, for example.

[0022] According to one embodiment, the cover defines with the support substrate a second cavity, the upper wall of the cover comprises a second opening opening into the second cavity, and the housing comprises a second electronic chip, for example a chip, for example a chip capable of receiving optical radiation, mounted on the mounting face of the support substrate in the second cavity.

[0023] The cover comprises a second optical element fixed on the upper wall of the cover, closing the second opening and in optical cooperation with the second chip electronics and the electromagnetic shielding element embedded in the cover surrounds the two electronic chips.

[0024] The electromagnetic shielding element also makes it possible to protect the second electronic chip from electromagnetic interference linked to electromagnetic waves coming from outside the optical housing.

[0025] According to another aspect, there is provided a method of manufacturing an optical integrated circuit package comprising: - a supply of a support substrate comprising a mounting face and a lower face opposite the mounting face, the support substrate comprising contact pads located on the lower face and an electrical interconnection network between the mounting face and the contact pads, - a formation of a hood having a side wall and a top wall and comprising an electromagnetic shielding element embedded in the hood as well as a first opening, - a fixing of a first optical element on the upper wall of the hood, the first optical element closing the first opening, - mounting a first electronic chip on the mounting face, - a fixing of the side wall of the cover on the mounting face of the substrate, the cover defining with the support substrate at least one first cavity, the first chip being located in said at least one first cavity and being in optical cooperation with the first optical element after said fixing of the side wall on the mounting face.

[0026] According to one embodiment, the electromagnetic shielding element is embedded in a molding resin.

[0027] According to one embodiment, the electromagnetic shielding element also forms at least one inductive element.

[0028] According to one embodiment, the formation of the cover comprises embedding electrically conductive connection means in the side wall, forming an additional wall connected to the side wall and extending into the first cavity when the side wall is fixed to the mounting face, and forming an additional opening in the additional wall, the method further comprising: - a fixing of an additional optical element on the additional wall, the additional optical element comprising a circuit and closing the additional opening, the optical element being in optical cooperation with the first optical element and the first electronic chip after said fixing of the side wall on the mounting face, - a connection of said circuit of the additional optical element to at least one pad contact via electrically conductive connection means and the interconnection network.

[0029] According to one embodiment, the embedding of electrically conductive connection means and the embedding of the electromagnetic shielding element are carried out simultaneously.

[0030] According to one embodiment, the formation of the cover comprises a formation of a second opening in the upper wall, the cover defining with the support substrate a second cavity and the second opening opening into the second cavity when the side wall is fixed on the mounting face, the method further comprising: - a fixing of a second optical element on the upper wall, the second optical element closing the second opening, and - mounting a second electronic chip on the mounting face, the second chip being located in said at least one second cavity and being in optical cooperation with the second optical element, then the electromagnetic shielding element surrounding the two electronic chips after said fixing of the side wall on the mounting face.

[0031] According to another aspect, there is provided a method of connecting a housing obtained by the method as defined previously, on a printed circuit board, comprising a connection of said at least one contact pad electrically coupled to the shielding element on electrically conductive means of the printed circuit board intended to be connected to a cold supply point.

[0032] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:

[0033] [Fig.l] ;

[0034] [Fig.2] ;

[0035] [Fig.3] ;

[0036] [Fig.4] ;

[0037] [Fig.5] ;

[0038] [Fig.6] ;

[0039] [Fig.7] ;

[0040] [Fig.8] ; and

[0041] [Fig.9] schematically illustrate methods of implementation and realization of the invention.

[0042] [Fig.l] schematically illustrates a sectional view of a BT integrated circuit optical package according to one embodiment of the invention.

[0043] The BT housing comprises a support substrate SUB comprising a mounting face FM and a lower face FL opposite the FM mounting face. The substrate SUB comprises an electrical interconnection network INTCNX between the FM mounting face and contact pads PAD1, PAD2 located on the lower face FL. In the case of an LGA type optical package, the contact pads PAD1 and PAD2 form a matrix of “pads”, typically made of copper, fixed and electrically connected to a printed circuit board PCB by soldering for example. The printed circuit board PCB comprises electrically conductive means such as conductive tracks PST1, PST2, typically made of copper (Cu), integrated in one or more layers of dielectric material such as resin mixed with fiberglass and intended to be connected to a power supply cold point, for example to a GND ground.

[0044] The SUB support substrate is of conventional structure and known per se. The SUB substrate comprises an INTCNX interconnection network also comprising conductive tracks, typically made of copper, integrated in one or more layers of dielectric material such as resin mixed with fiberglass.

[0045] The support substrate SUB is therefore in this case a laminated support substrate (“laminate substrate” in English).

[0046] The optical box BT also comprises a first electronic chip CHP1, typically an emitting chip capable of emitting optical radiation of the infrared or laser type for example, and a second electronic chip CHP2, typically a receiving chip capable of capturing optical radiation.

[0047] The chips CHP1 and CHP2 are mounted and connected to the support substrate in a conventional manner known per se, for example by means of solder wires (“wire bonding”) WB1 and WB2.

[0048] The optical package BT further comprises a cover CPT having a side wall PRLAT fixed on the mounting face FM and an upper wall PRSUP1. The cover CPT defines with the support substrate SUB a first cavity CAV1 in which the first chip CHP1 is mounted, and a second cavity CAV2 in which the second chip CHP2 is mounted. In particular, the first cavity CAV 1 and the second cavity CAV2 may be separated by a middle part PM of the side wall of the cover CPT fixed on the mounting face FM.

[0049] Alternatively (not shown), this middle part PM of the PRLAT wall may not not be fixed to the mounting face FM and have an opening allowing the second chip CHP2 to be mounted which can then extend into the first cavity CAV1. The foot of the middle wall PM of the side wall PRLAT can therefore be positioned on a face of the second chip CHP2 or be spaced from it so that the first cavity CAV1 and the second cavity CAV2 communicate with each other.

[0050] Furthermore, the upper wall PRSUP1 of the CPT cover comprises a first opening FNT1 and a second opening FNT2. The BT housing further comprises a first optical element OPT1 and a second optical element OPT2 fixed on the upper wall PRSUP1.

[0051] The first optical element OPT1 closes the first opening FNT1 and is in optical cooperation with the first chip CHPL. The second optical element OPT2 closes the second opening FNT2 and is in optical cooperation with the second chip CHP2. The first optical element OPT1 and the second optical element OPT2 are, for example, filters or lenses.

[0052] In operation, the electronic chip CHP1 emits, in addition to optical radiation, unwanted electromagnetic waves that can propagate in several directions towards the outside of the BT package. These unwanted electromagnetic waves typically generate electromagnetic interference with electronic circuits that could be located in the vicinity of the BT package, for example circuits of the printed PCB, and if these waves are not blocked, can degrade or limit the performance of the electronic system in which the optical package is used.

[0053] Furthermore, the first chip CHP1 and the second chip CHP2 may be sensitive to external electromagnetic waves, coming from circuits located outside the BT box, which may degrade or limit their performance.

[0054] In this respect, the optical package BT comprises an electromagnetic shielding element SHLD embedded in the cover CPT and capable of blocking the electromagnetic waves generated by the electronic chip CHP1 as well as those generated by the circuits outside the package BT. The electromagnetic shielding element SHLD is typically an electrical conductor, for example made of copper, and surrounds the two chips CHP1 and CHP2 thus forming a Faraday cage. In addition, the shielding element SHLD is embedded in a molding resin to protect it from deterioration due to mechanical shocks or corrosion for example. The shielding element SHLD can be embedded in the middle part PM of the side wall PRLAT separating the cavities CAV1 and CAV2 in order to prevent electromagnetic interference between the two chips CHP1 and CHP2 for example.

[0055] The electromagnetic shielding element SHLD is intended to be coupled to the power supply cold point GND via the interconnection network INTCNX of the substrate SUB and one or more contact pads PAD1. The contact pads PAD1 can be connected to the conductive tracks PST1, PST2 of the printed circuit board PCB by soldering to allow the coupling of the shielding element SHLD to the power supply cold point GND and thus allow shielding of the BT housing.

[0056] The effectiveness of the shielding depends on parameters such as the material used, its thickness and the frequency to be blocked. Those skilled in the art will be able to adapt these parameters depending on the intended application so as to obtain a SHLD shielding element capable of blocking the electromagnetic waves generated by the first CHP1 chip as well as those coming from outside the BT box.

[0057] Thus, the SHLD shielding element makes it possible to avoid interference with the circuits in the vicinity of the BT optical package and to protect the CHP1 and CHP2 electronic chips from interference that could be generated by electromagnetic waves coming from outside the BT package. In addition, the SHLD shielding element contributes to making the BT package more compact since it is integrated into the CPT cover unlike an adhesive strip conventionally used as electromagnetic shielding which would increase the size of the package.

[0058] The CPT cover advantageously comprises an additional wall PRSUP2 extending into the first cavity CAV1 and connected to the side wall PRLAT of the CPT cover. The additional wall PRSUP2 has an additional opening FNT3 which is for example aligned with the first opening FNT1 of the upper wall PRSUP1.

[0059] The BT housing comprises an additional optical element OPT3, for example a filter or a lens, comprising a circuit CIRC, and fixed on the additional wall PRSUP2. The additional optical element OPT3 is in optical cooperation with the first optical element OPT1 and the first electronic chip CHP1. In this way, the first electronic chip CHP1 can receive optical radiation passing through the first optical element OPT1 and the additional optical element OPT3.

[0060] Of course, the CIRC circuit is positioned so as not to obstruct the path of the optical radiation. It can, for example, be placed on the periphery of the lens or the filter.

[0061] [Fig.2] illustrates a sectional view of the BT optical housing described previously in relation with [Fig.l] along axis II-II.

[0062] The circuit CIRC of the additional optical element OPT3 is electrically connected to at least one other contact pad PAD2, different from the contact pad PAD1, via electrically conductive connection means CNX and the interconnection network INTCNX of the substrate SUB. The contact pad PAD2 is in particular connected by soldering to a conductive track (not shown) of the printed circuit board PCB. The electrically conductive connection means CNX are embedded in the side wall PRLAT of the cover CPT and are electrically separated from the shielding element SHLD by the molding resin.

[0063] The circuit CIRC comprises, for example, conductive tracks which can be connected to the connection means CNX by electrically conductive wires WB3. The connection means CNX are themselves electrically coupled to the contact pad PAD2 by the interconnection network INTCNX of the substrate SUB.

[0064] Consequently, the circuit CIRC forms with the connection means CNX and the interconnection network INTCNX a closed circuit in which a current can flow, for example a current coming from the conductive track (not shown) of the printed PCB coupled to the connection pad PAD2. Such a circuit makes it possible to detect a failure of the additional optical element OPT3 such as delamination, for example in the event of a break in a conductive track of the circuit CIRC caused by the delamination. For example, the power supply of the first electronic chip CHP1 can be cut off when no more current flows in the circuit CIRC of the optical element OPT3, so as to prevent the chip CHP1 from generating the optical radiation when a failure of the additional optical element OPT3 is detected.

[0065] [Fig.3] illustrates a sectional view of the CPT cover described previously in relation to [Fig.l] along axis III-III.

[0066] The SHLD electromagnetic shielding element can have several different shapes depending on the application and can for example form a grid making it possible to reduce the quantity of material used for the manufacture of the SHLD shielding element while allowing it to ensure its function of blocking electromagnetic waves.

[0067] [Fig.4] illustrates a sectional view of the CPT cover described previously in relation to [Fig.1] along the axis III-III according to a second embodiment of the invention.

[0068] The electromagnetic shielding element SHLD here advantageously forms at least one inductive element, for example a first inductive element L1 and a second inductive element L2 allowing the circuits of the electronic chips CHP1 and CHP2 to be connected to these inductive elements.

[0069] Figures 5 to 9 illustrate the steps of a manufacturing method of the BT optical housing described previously in relation to Figures 1 to 4 according to one embodiment.

[0070] [Fig.5] schematically illustrates the result of a step 100 of forming the CPT cover.

[0071] The CPT cover has a side wall PRLAT and a top wall PRSUP1. The CPT cover comprises an electromagnetic shielding element SHLD embedded in the CPT cover as well as a first opening FNT1. The formation 100 of the CPT cover also comprises a formation of a second opening FNT2 in the top wall PRSUP1.

[0072] The SHLD shielding element is typically made from an electrically conductive material such as copper and may have a different shape depending on the intended application. Those skilled in the art will be able to adapt the parameters of the SHLD shielding element such as the material used or its thickness so as to obtain a SHLD shielding element capable of blocking electromagnetic waves, for example those that may be generated by a microchip or other circuits.

[0073] During this step 100, a CPT cover can be formed, the shielding element SHLD of which forms a grid like that described in relation to [Fig. 3] or advantageously forms at least one inductive element like the shielding element described in relation to [Fig. 4].

[0074] In this step 100, the shielding element SHLD is embedded in a molding resin. The step 100 of forming the cover CPT also comprises embedding electrically conductive connection means CNX in the side wall PRLAT and forming an additional wall PRSUP2 connected to the side wall PRLAT. In particular, the embedding of connection means CNX is advantageously carried out at the same time as the embedding of the shielding element SHLD. Furthermore, step 100 comprises forming an additional opening FNT3 in the additional wall PRSUP2.

[0075] [Fig.6] schematically illustrates the result of a step 101 of fixing optical elements on the walls of the CPT cover.

[0076] Step 101 comprises in particular a fixing, for example by gluing, of a first optical element OPT1 and a second optical element OPT2 on the upper wall PRSUP1. The first optical element OPT1 closes the first opening FNT1 and the second optical element OPT2 closes the second opening FNT2. In addition, step 101 comprises a fixing of an additional optical element OPT3 comprising a circuit CIRC on the additional wall PRSUP2 and a connection of the circuit CIRC to the connection means CNX, for example by conductive wires WB3. The additional optical element OPT3 closes the additional opening FNT3.

[0077] [Fig.7] schematically illustrates the result of a step 102 of providing a support substrate SUB and mounting a first chip CHP1 and a second chip CHP2.

[0078] The support substrate SUB comprises a mounting face FM and a lower face FL opposite the mounting face FM. The support substrate SUB comprises contact pads PAD1, PAD2 located on the lower face FL and an electrical interconnection network INTCNX between the mounting face FM and the contact pads PAD1, PAD2.

[0079] More particularly, step 102 comprises mounting a first chip CHP1, typically a chip capable of emitting optical radiation, on the mounting face FM via conductive wire WB1, and mounting a second chip CHP2, typically a chip capable of receiving the optical radiation, on the mounting face FM via conductive wires WB2.

[0080] Step 102 can be carried out in parallel with steps 100 and 101 described previously in relation to figures 5 and 6, or before or after step 100 and / step 101 for example.

[0081] [Fig.8] schematically illustrates the result of a step 103 of fixing the wall PRLAT side of the CPT cover on the FM mounting face of the SUB substrate.

[0082] More particularly, the PRLAT side wall can be fixed on the FM mounting face, using glue for example, so that the SHLD shielding element is coupled with the INTCN interconnection network of the SUB substrate.

[0083] When fixing the side wall PRLAT, the cover CPT defines with the support substrate SUB a first cavity CAV1 and a second cavity CAV2, the additional wall PRSUP2 extends into the first cavity CAV1, and the second opening FNT2 opens into the second cavity CAV2. The first chip CHP1 is located in the first cavity CAV1 and is in optical cooperation with the first optical element OPT1 and the additional optical element OPT3. Similarly, the second chip CHP2 is located in the second cavity CAV2 and is in optical cooperation with the second optical element OPT2.

[0084] The method further comprises a connection of the circuit CIRC of the additional optical element OPT3 to one or more contact pads PAD2, different from the contact pads PAD1 via the electrically conductive connection means CNX and the interconnection network INTCNX of the substrate SUB.

[0085] [Fig.9] schematically illustrates a method of connecting a BT box obtained by the method described previously in relation to figures 5 to 8, on a PCB printed circuit board.

[0086] The connection method notably comprises a connection of the contact pads PAD1 electrically coupled to the shielding element SHLD on electrically conductive means PST1, PST2 of the printed circuit board PCB. The electrically conductive means PST1 and PST2 are connected to a cold supply point, for example a ground GND. Consequently, the electromagnetic shielding element SHLD can be connected to this ground GND via the contact pads PAD1, the interconnection network INTCNX and the tracks PST1, PST2,

[0087] The shielding element SHLD thus forms a Faraday cage around the electronic chips CHP1 and CHP2 capable of blocking unwanted electromagnetic waves generated by the electronic chip CHP1 as well as those generated by the circuits outside the BT box.

Claims

Claims

1. Optical integrated circuit package (BT), comprising a support substrate (SUB) comprising a mounting face (FM) and an electrical interconnection network (INTCNX) between the mounting face and contact pads (PAD1, PAD2) located on a lower face (FL) of the support substrate, opposite the mounting face, a cover (CPT) having a side wall (PRLAT) fixed on the mounting face and an upper wall (PRSUP1) comprising a first opening (FNT1), the cover (CPT) defining with the support substrate (SUB) at least one first cavity (CAV1), a first optical element (OPT1) fixed on the upper wall of the cover (CPT) and closing the first opening (FNT1), an electromagnetic shielding element (SHLD) embedded in the cover (CPT) and intended to be coupled to a power supply cold point (GND) via the interconnection network (INTCNX) and at least one contact pad (PADI),a first electronic chip (CHP1) mounted on the mounting face (FM) in said at least one first cavity (CAV1) and in optical cooperation with the first optical element (OPT1), in which the cover (CPT) comprises an additional wall (PRSUP2) extending into the first cavity (CAV1), connected to the side wall (PRLAT) and having an additional opening (FNT3), and the housing (BT) comprises an additional optical element (OPT3) fixed on the additional wall (PRSUP2), closing the additional opening (FNT3) and in optical cooperation with the first optical element (OPT1) and the first electronic chip (CHP1), the additional optical element (OPT3) comprising a circuit (CIRC) electrically connected to at least one other contact pad (PAD2) via electrically conductive connection means (CNX) embedded in the side wall (PRLAT) of the cover (CPT) and of the interconnection network (INTCNX).,

2. A housing according to claim 1, wherein the electromagnetic shielding element (SHLD) is embedded in a molding resin.

3. Housing according to claim 1 or 2, wherein the shielding element (SHLD) also forms at least one inductive element (L1, L2).

4. Housing according to one of the preceding claims, in which the cover (CPT) defines with the support substrate (SUB) a second cavity (CAV2), the upper wall (PRSUP1) of the cover comprises a second opening (FNT2) opening into the second cavity (CAV2), and the housing (BT) comprises a second electronic chip (CHP2) mounted on the mounting face (FM) of the support substrate (SUB) in the second cavity (CAV2), and the cover (CPT) comprising a second optical element (OPT2) fixed on the upper wall (PRSUP1) of the cover (CPT), closing the second opening (FNT2) and in optical cooperation with the second electronic chip (CHP2), the electromagnetic shielding element (SHLD), embedded in the cover surrounding the two electronic chips (CHP1, CHP2).

5. A method of manufacturing an optical integrated circuit package (BT) comprising: - a supply of a support substrate (SUB) comprising a mounting face (FM) and a lower face (FL) opposite the mounting face (FM), the support substrate (SUB) comprising contact pads (PAD1, PAD2) located on the lower face (FL) and an electrical interconnection network (INTCNX) between the mounting face (FM) and the contact pads (PAD1, PAD2), - a formation of a cover (CPT) having a side wall (PRLAT) and an upper wall (PRSUP1) and comprising an electromagnetic shielding element (SHLD) embedded in the cover (CPT) as well as a first opening (FNT1), - a fixing of a first optical element (OPT1) on the upper wall (PRSUP1) of the cover (CPT), the first optical element (OPT1) closing the first opening (FNT1), - mounting a first electronic chip (CHP1) on the mounting face (FM), - a fixing of the side wall (PRLAT) of the cover (CPT) on the mounting face (FM) of the substrate (SUB), the cover (CPT) defining with the support substrate (SUB) at least one first cavity (CAV1), the first chip (CHP1) being located in said at least one first cavity (CAV1) and being in optical cooperation with the first optical element (OPT1) after said fixing of the side wall (PRLAT) on the mounting face (FM), wherein the formation of the cover (CPT) comprises a embedding of electrically conductive connection means (CNX) in the side wall (PRLAT), a formation of an additional wall (PRSUP2) connected to the side wall (PRLAT) and extending into the first cavity (CAV1) when the side wall (PRLAT) is fixed on the mounting face (FM), and a forming an additional opening (FNT3) in the additional wall (PRSUP2), the method further comprising: - fixing an additional optical element (OPT3) on the additional wall (PRSUP2), the additional optical element (OPT3) comprising a circuit (CIRC) and closing the additional cover (FNT3), the optical element (OPT3) being in optical cooperation with the first optical element (OPT1) and the first electronic chip (CHP1) after said fixing of the side wall (PRLAT) on the mounting face (FM), - connecting said circuit (CIRC) of the additional optical element (OPT3) to at least one contact pad (PAD2) via the electrically conductive connection means (CNX) and the interconnection network (INTCNX).

6. The method of claim 5, wherein the electromagnetic shielding element (SHLD) is embedded in a molding resin.

7. Method according to claim 5 or 6, wherein the electromagnetic shielding element (SHLD) also forms at least one inductive element (L1, L2).

8. Method according to one of claims 5 to 7, in which the embedding of electrically conductive connection means (CNX) and the embedding of the electromagnetic shielding element (SHLD) are carried out simultaneously.

9. Method according to one of claims 5 to 8, wherein the formation of the cover (CPT) comprises a formation of a second opening (FNT2) in the upper wall (PRSUP1), the cover (CPT) defining with the support substrate (SUB) a second cavity (CAV2) and the second opening (FNT2) opening into the second cavity (CAV2) when the side wall (PRLAT) is fixed on the mounting face (FM), the method further comprising: - a fixing of a second optical element (OPT2) on the upper wall (PRSUP1), the second optical element (OPT2) closing the second opening (FNT2), and - a mounting of a second electronic chip (CHP2) on the mounting face (FM), the second chip (CHP2) being located in said at least one second cavity (CAV2) and being in optical cooperation with the second optical element (OPT2), then the electromagnetic shielding element (SHLD) surrounding the two electronic chips (CHP1,CHP2) after said fixing of the side wall (PRLAT) on the face of, assembly (FM).

10. Method for connecting a housing obtained by the method according to one of claims 5 to 9, on a printed circuit board (PCB), comprising a connection of said at least one contact pad (PAD1) electrically coupled to the shielding element (SHLD) on electrically conductive means (PST1, PST2) of the printed circuit board (PCB) intended to be connected to a cold power supply point (GND).

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