Frequency shift of a clock signal

Abstract

Frequency shift of a clock signal The present description relates to an electronic device (200) configured to apply a frequency shift function to a first signal (Clk_F) having a first frequency (F) comprising: - a delay element (206) adapted to provide a second signal (Clk_F_D) corresponding to the first signal delayed by a duration equal to a first period of said first signal (Clk_F) divided by four; - a branch successively comprising a first circuit (201) adapted to divide the frequency of a signal by a number, a second integrator circuit (203), said branch being adapted to provide a third signal (Q_comp) and a fourth signal (I_comp); and a third single-sideband mixer circuit (208). Figure for abstract: Fig. 2

Description

Title of the invention: Frequency shift of a clock signal Technical field

[0001] The present description relates generally to the radiofrequency transmission of data, and to the processing of signals. The present description relates more particularly to the realization of a frequency shift function of a signal generated by a local oscillator, that is to say a clock signal. Prior art

[0002] Signal analysis and processing techniques are used nowadays to optimize data transmission.

[0003] It would be desirable to be able to improve, at least in part, certain aspects of signal processing and transmission. Summary of the invention

[0004] There is a need for more efficient data transmission.

[0005] There is a need for more efficient signal transmission.

[0006] There is a need for an implementation of a frequency shift function of a more efficient clock signal.

[0007] One embodiment overcomes all or part of the drawbacks of known data transmission chains.

[0008] One embodiment overcomes all or part of the drawbacks of known devices implementing a frequency shift operation of a clock signal.

[0009] One embodiment provides an electronic device configured to apply a frequency shift function to a first signal having a first frequency comprising: - a delay element adapted to provide a second signal corresponding to the first signal delayed by a duration equal to a first period of said first signal divided by four; - a branch successively comprising a first circuit adapted to divide the frequency of a signal by a number, a second integrator circuit, said branch being adapted to provide a third signal and a fourth signal; and a third single-sideband mixer circuit adapted to combine the first signal, the second signal, and the third signal and the fourth signal to provide a fourth-fifth signal.

[0010] According to one embodiment, said first circuit is adapted to provide a sixth signal corresponding to the quadrature of the first signal whose frequency is divided by said number, the third signal being obtained by supplying the sixth signal to said second integrator circuit.

[0011] According to one embodiment, said first circuit is adapted to provide, in addition, a seventh signal corresponding to the first signal whose frequency is divided by said number, and said branch further comprising a fourth integrator circuit adapted to receive the sixth signal and to supply the fourth signal.

[0012] According to one embodiment, the device further comprises a fifth sign change circuit adapted to modify the sign of said second signal to provide an eighth signal.

[0013] According to one embodiment, the fifth signal is given by the following mathematical formula: [Math 1] Mix_F _offset(t) = Clk_F[t)*I comp^t) + Clk_F in which: - Mix_F_offset(t) represents the fifth signal; - Clk_F(t) represents the first signal; - I_comp(t) represents the fourth signal; - Clk_F_Q(t) represents the eighth signal; and - Q_comp(t) represents the third signal.

[0014] According to one embodiment, said fifth sign change circuit is controllable.

[0015] According to one embodiment, the number is a multiple of two.

[0016] According to one embodiment, the number is a multiple of four.

[0017] According to one embodiment, said delay element is a delay element programmable.

[0018] According to one embodiment, the first signal is a clock signal.

[0019] Another embodiment provides a signal transmission chain comprising a device described above.

[0020] According to one embodiment, the chain further comprises: - a frequency generator; - a carrier frequency modulator; and - a power amplifier circuit. Brief description of the drawings

[0021] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0022] [Fig.l] represents, very schematically and in the form of blocks, an embodiment of a part of a data transmission chain;

[0023] [Fig.2] represents, very schematically and in the form of blocks, an embodiment of a device implementing a frequency shift operation of a clock signal;

[0024] [Fig.3] represents timing diagrams illustrating the operation of the embodiment of [Fig.2];

[0025] [Fig.4] is a graph illustrating an example of a compression function used in the embodiment of [Fig.2]; and

[0026] [Fig.5] represents another timing diagram illustrating the operation of the embodiment of [Fig.2]. Description of the embodiments

[0027] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0029] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0032] [Fig. 1] represents, very schematically and in the form of blocks, an embodiment of a part 100 of a radiofrequency data transmission chain. In other words, [Fig. 1] represents an embodiment of a part of a transmission chain adapted to transmit data using signals whose frequency is between 3 kHz and 300 GHz.

[0033] Part 100 of the transmission chain comprises: - a frequency generator circuit 101 (Freq Syn);

[0034]

[0035]

[0036]

[0037] - an embodiment of a device 102 (Freq Offset) adapted to implement a frequency offset function of a clock signal received at the input; - a modulator on carrier frequency 103 (Modulator); - a power amplifier circuit 104 (Power Amp); and - an antenna 105. The frequency generator circuit 101, or frequency synthesizer, is a circuit suitable for generating a clock signal, i.e. a constant frequency signal, preferably a constant frequency square wave signal, also called a constant frequency square wave signal. According to one example, the frequency generator circuit is a local oscillator. According to one example, the circuit 101 is a phase-locked loop (PLL). Thus, in [Fig.l], the circuit 101 provides, at its output, a periodic square-type clock signal Clk_lo having a constant frequency F_lo. It is agreed, in the remainder of the description, that a clock signal of frequency F denotes a square periodic signal of period 1 / F. In the remainder, the signals whose reference begins with Clk are clock signals. Moreover, an ideal clock signal Clk(t) of frequency F is given by the following mathematical formula: [Math 2] Clk(t) = sign(sin(2nFt + 0 o ) ) in which (pQ denotes the initial phase, and the mathematical function sign is given by the following mathematical formula: [Math 3] z . f 1 if x > 0 sign(x) = 1 - . 1-1 otherwise The device 102 implements a frequency offset function (Frequency Offset) of the clock signal Clk_lo that it receives as input. Thus, the device 102 receives, as input, the clock signal Clk_lo of frequency F_lo, and provides as output a clock signal Clk_offset_lo of square type having a frequency F_offset_lo. An embodiment of the device 102 is described in more detail with [Fig.2]. The clock signal Clk_offset_lo is obtained by a Single Side Band Mixing (SSB Mixing) of the clock signal Clk_lo with a signal corresponding to the clock signal Clk_lo whose frequency F has been divided by an integer N. Thus, the frequency F_offset_lo of the clock signal Clk_offset_lo is given by the following mathematical formula: [Math 4] Foffsetlo = F_lo + sign_offset ( ^- ) where the sign_offset function is a controllable sign function that is equal to 1 or -1.

[0038] The carrier frequency modulator 103 (Modulator) receives as input a data signal Sig_bb and the clock signal Clk_offset_lo, and provides, as output, a modulated output signal Sig_rf. The signal Sig_bb is the signal to be transmitted comprising, for example, data, this signal is also called baseband signal. The clock signal Clk_offset_lo is used as the carrier signal. In other words, the frequency F_offset_lo is the carrier frequency of the modulated signal Sig_bb.

[0039] According to a variant, the clock signal Clk_offset_lo may undergo a possible frequency division by an integer K before serving as a carrier signal. In this case, the carrier frequency of the modulated signal Sig_rf is equal to the frequency F_offset_lo divided by the integer K.

[0040] The power amplifier circuit 104 receives, at its input, the modulated signal Sig_rf, and provides, at its output, an amplified modulated signal Sig_amp_rf. The amplifier circuit 104 can, in certain architectures, generate a coupling phenomenon with the frequency generator circuit 101. The use of the device 102 makes it possible to avoid this phenomenon by preventing the harmonics of the signal Sig_rf whose frequencies are integer multiples of the frequency F_rf of the signal Sig_rf from coinciding with the clock signal Clk_lo of frequency F_lo.

[0041] The antenna 105 receives the amplified modulated signal Sig_amp_rf and transmits it.

[0042] [Fig.2] represents, schematically and in the form of blocks, a mode of production of a device 200 adapted to apply a frequency shift function of the type of the device 102 described in relation to [Fig.l].

[0043] The device 200 comprises an input node IN200 adapted to receive a clock signal Clk_F of frequency F.

[0044] The device 200 comprises a branch comprising, in the following order: - a frequency divider circuit 201 (DIV N); - two integrator circuits 202 (INT) and 203 (INT); and - two circuits 204 (COMP) and 205 (COMP), optional, suitable for applying a compression function.

[0045] The frequency divider circuit 201 receives, as input, the clock signal Clk_F and provides as output two signals Clk_F_N_I and Clk_F_N_Q. The clock signal Clk_F_N_I corresponds to the signal Clk_F whose frequency has been divided by an integer N, which is subsequently denoted F_N. The clock signal Clk_F_N_Q corresponds to the quadrature of the clock signal Clk_F_N_I. In practice, the clock signal Clk_F_N_Q is a delayed version of the signal Clk_F_N_I by a duration Tau_N. The clock signal Clk_F_N_Q(t) is given by the following mathematical formula: [Math 5] ClkFNQ(t) = Clk_F_N_I(t-Tau_N)

[0046] To allow a perfect quadrature between the clock signals Clk_F_N_I and Clk_F_N_Q, the time offset Tau_N is given by the following mathematical formula: [Math 6] Tau N = in which T is the period of the signal Clk_F, i.e. the inverse of the frequency F.

[0047] The value of the integer N can be controllable. According to one embodiment, the integer N is a multiple of two. According to a preferred embodiment, the integer N is a multiple of four. The duration Tau_N corresponds, in this case, to an integer number of periods T.

[0048] The integrator circuit 202 receives, as input, the clock signal Clk_F_N_I, and provides as output an analog signal I. The signal I is obtained by integrating, in the time domain, the clock signal Clk_F_N_I. Thus, in practice, since the clock signal Clk_F_N_I is a square signal of frequency F_N, the signal I is a triangular signal of frequency F_N.

[0049] The integrator circuit 203 receives, as input, the clock signal Clk_F_N_Q, and provides as output an analog signal Q. The signal Q is obtained by integrating, in the time domain, the clock signal Clk_F_N_Q. Thus, in theory, since the clock signal Clk_F_N_Q is a shifted version of the duration Tau_N of the clock signal Clk_F_N_I, the signal Q is a delayed version of the duration Tau_N of the signal I. In other words, the signal Q(t) is given by the following mathematical formula: [Math 7] Q(t) =I(t-Tau_N)

[0050] The circuit 204 adapted to optionally apply a compression function, in the time domain, receives, as input, the signal I, and provides as output a signal I_comp. A well-chosen compression function, this choice being within the reach of the person skilled in the art, makes it possible to provide a signal approaching a sinusoidal signal. The signal I_comp(t) is given by the following mathematical formula: [Math 8] I_comp(t) = Gcomp(I(t)) in which Gcomp is the compression function.

[0051] An example of a compression function implemented by circuits 204 and 205 is described in relation to [Fig.4].

[0052] Circuit 205 is identical to circuit 204, optional and is adapted to apply the compression function Gcomp described previously. Circuit 205 receives, in input, the signal Q, and outputs a signal Q_comp. In theory, since the signal Q is a delayed version of the signal I by the duration Tau_N, the signal Q_comp is therefore a delayed version of the signal I_comp by the duration Tau_N. In other words, the signal Q_comp(t) is given by the following mathematical formula: [Math 9] Q_comp(t) = I_comp(t-Tau_N)

[0053] The device 102 further comprises a delay element 206 (DTC) adapted to temporally shift a signal of a duration Tau. The delay element receives, as input, the clock signal Clk_F and provides as output a temporally shifted clock signal Clk_F_D. Thus, the clock signal Clk_F_D(t) is given by the following mathematical formula: [Math 10] Clk_F_D(t) = ClkF(t-Tau)

[0054] According to one embodiment, the duration Tau is given by the following mathematical formula: [Math 11] Tau = j

[0055] Furthermore, and according to one embodiment, the delay element 206 is configurable. In particular, the duration Tau is configurable, which allows the device 102 to adapt to any input frequency F.

[0056] The device 102 further comprises, optionally, a sign change circuit 207 (SIGN). The sign change circuit 207 makes it possible to define the operation performed by the sign_offset function described previously. More particularly, the circuit 207 makes it possible to determine whether the frequency of the output signal of the device 200 is equal to the sum or the difference of the frequencies F and F_N. According to one example, if the device 200 provides as output a signal whose frequency is the result of a difference, in this case the sign_offset function is equal to minus one, the sign change circuit is not present. According to one example, if the device 200 provides as output a signal whose frequency is the result of a sum, in this case the sign_offset function is equal to one, the sign change circuit makes it possible to invert the sign of the signal that it receives.According to another example, the circuit 207 can be a controllable circuit allowing, from a control signal, to invert or not the sign of the clock signal that it receives or not.

[0057] Thus, the sign change circuit 207 receives, as input, the clock signal Clk_F_D, and provides as output a clock signal Clk_F_Q. The signal Clk_F_Q corresponds to the clock signal Clk_F whose sign has been inverted or not. The signal Clk_F_Q(t) is given by the following mathematical formula: [Math 12] Clk_F_Q(t) = -sign_offset*Clk_F_D(t)

[0058] The device 102 further comprises a single sideband mixer circuit 208 (SSB Mixer), which is used to modulate the quadrature analog signals I_comp and Q_comp by the clock signals Clk_F and Clk_F_Q, providing as output the signal Mix_F_offset. In theory, the single sideband mixer performs the operation described by the following mathematical equation: [Math 13] MixFoffset(t) = Clk F(t) *I_comp(t) + Clk F_Q(t) *Q_comp(t)

[0059] According to a variant, the compression functions of circuits 204 and 205 are directly implemented by circuit 208.

[0060] The Mix_F_offset signal obtained at the output is, by construction, a periodic analog signal of frequency F_N. However, the greater part of the power of this signal is concentrated in the harmonic of the Mix_F_offset signal of frequency F_offset, given by the following equation: [Math 14] Foffset = F + signoffset*^

[0061] The device 102 finally comprises a clock regeneration device 209, which, from the analog input signal Mix_F_offset, provides the clock signal Clk_F_offset, by making a comparison with respect to zero. The signal Clk_F_offset(t) is given by the following mathematical formula: [Math 15] Clk_F_offset(t) = sign(Mix_F_offset(t))

[0062] Optionally, the clock signal regeneration circuit 209 integrates a filter before the comparison to zero in order to improve the spectral purity of the clock signal Clk_F_offset. In this case, the signal Clk_F_offset(t) is given by the following mathematical formula: [Math 16] Clk_F_offset( t) = sign(h( t) ®Mix_F_offset( t) ) where h(t) is the impulse response of the filter.

[0063] The operation of the device 200 is illustrated in more detail in relation to the timing diagrams of Figures 3 and 5 and with the graph of [Fig.4].

[0064] [Fig. 3] includes timing diagrams illustrating a practical example of operation of the device 200 described in relation to [Fig. 2].

[0065] [Fig.3] includes the following timing diagrams: - a timing diagram referenced Clk_F representing the temporal evolution of the clock signal Clk_F described in relation to [Fig.2]; - a timing diagram referenced Clk_F_N_I representing the temporal evolution of the clock signal Clk_F_N_I described in relation to [Fig.2]; - a timing diagram referenced Clk_F_N_Q representing the temporal evolution of the clock signal Clk_F_N_Q described in relation to [Fig.2]; - a timing diagram referenced I representing the temporal evolution of the signal I described in relation to [Fig.2]; and - a timing diagram referenced Q representing the temporal evolution of the signal Q described in relation to [Fig.2].

[0066] As previously stated, the clock signal Clk_F is a clock signal of frequency F and period T.

[0067] The clock signals Clk_F_N_I and Clk_F_N_Q are also periodic square signals. However, since the clock signals Clk_F_N_I and Clk_F_N_Q are the output signals of the circuit 201, their frequency is the frequency F_N, and their period is a duration T_N equal to the period T multiplied by the integer N. In [Fig. 3], the integer N is equal to eight. The clock signal Clk_F_N_Q is time-shifted relative to the clock signal Clk_F_N_I by the time shift Tau_N described previously.

[0068] The signals I and Q are triangular periodic signals. However, since the signals I and Q are obtained by integrating the clock signals Clk_F_N_I and Clk_F_N_Q, their frequency is the frequency F_N, and their period is a duration T_N. The signal Q is time-shifted relative to the signal I by the time shift Tau_N described above.

[0069] [Fig.4] is a graph 400 illustrating the evolution of a compression function Gcomp applied by the circuits 204 and 205 described in relation to [Fig.2].

[0070] The abscissa axis of the graph 400 represents the value of the amplitude of the input signal, and the ordinate axis represents the amplitude of the input signal transformed by the Gcomp function.

[0071] According to one example, the function Gcomp is a function of the hyperbolic tangent type.

[0072] [Fig.5] comprises two timing diagrams illustrating a practical example of operation of the device 200 described in relation to [Fig.2].

[0073] [Fig.5] includes the following timing diagrams: - the chronogram referenced I, in dotted line, representing the temporal evolution of the signal I described in relation to [Fig.2]; and - a timing diagram referenced I_comp representing the temporal evolution of the I_comp signal described in relation to [Fig.2].

[0074] As described previously, signal I is a periodic signal of triangular shape.

[0075] The signal I_comp corresponds to the application of the compression function of the circuit 204 to the signal I. As previously stated, the signal I_comp is a signal whose shape is pseudo-sinusoidal and has a frequency equal to the frequency F_N.

[0076] Similarly, the signal I_comp, not shown, has a pseudo-sinusoidal shape, has a frequency equal to the frequency F_N, and has a time shift equal to the duration Tau_N relative to the signal I_comp.

[0077] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0078] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Electronic device (102; 200) configured to apply a frequency shift function to a first signal (Clk_F_lo; Clk_F) having a first frequency (F_lo; F) comprising: - a delay element (206) adapted to provide a second signal (Clk_F_D) corresponding to the first signal delayed by a duration (Tau) equal to a first period (T) of said first signal (Clk_F) divided by four; - a branch successively comprising a first circuit (201) adapted to divide the frequency of a signal by a number (N), a second integrator circuit (203) and a sixth circuit (204) adapted to implement a compression function, said branch being adapted to provide a third signal (Q_comp) and a fourth signal (I_comp);and a third single-sideband mixer circuit (208) adapted to combine the first signal (Clk_F), the second signal (Clk_F_D), the third signal (Q_comp) and the fourth signal (I_comp) to provide a fifth signal (Mixer_F_offset), wherein said first circuit (201) is adapted to provide a sixth signal (Clk_F_N_Q) corresponding to the quadrature of the first signal (Clk_F) whose frequency (F) is divided by said number (N), the third signal (Q_comp) being obtained by providing the sixth signal (Clk_F_N_Q) to said second integrator circuit (203), and wherein said first circuit (201) is adapted to provide, in addition, a seventh signal (Clk_F_N_I) corresponding to the first signal (Clk_F) whose frequency (F) is divided by said number (N), and said branch further comprising a fourth integrator circuit (202) adapted to receive the sixth signal (Clk_F_N_I) and provide the fourth signal (I_comp).;

2. Device according to claim 1, further comprising a fifth sign changing circuit (206) adapted to modify the sign of said second signal (Clk_F_D) to provide an eighth signal (Clk_F_Q).

3. Device according to claim 2, in which the fifth signal (Mixer_F_offset) is given by the following mathematical formula: [Math 17] Mix F offset^t)= Clk compft) + Clk FQ(t]*Q cornet)

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10. in which: - Mix_F_offset(t) represents the fifth signal (Mix_F_offset); - Clk_F(t) represents the first signal (Clk_F); - I_comp(t) represents the fourth signal (I_comp); - Clk_F_Q(t) represents the eighth signal (Clk_F_Q); and - Q_comp(t) represents the third signal (Q_comp). Device according to claim 2 or 3, wherein said fifth sign change circuit (207) is controllable. Device according to any one of claims 1 to 4, in which the number (N) is a multiple of two. Device according to claim 5, wherein the number (N) is a multiple of four. A device according to any one of claims 1 to 6, wherein said delay element (201) is a programmable delay element. Device according to any one of claims 1 to 7, wherein the first signal (Clk_F) is a clock signal. Transmission chain (100) of a signal comprising a device (102; 200) according to any one of claims 1 to 8. The chain of claim 9, further comprising: - a frequency generator (101); - a carrier frequency modulator (104); and - a power amplifier circuit (105), in which said device (102; 200) is adapted to receive said first signal (Clk_F_lo; Clk_F) from the frequency generator (101) and is adapted to supply said fifth signal (Mixer_F_offset) to said carrier frequency modulator (104).

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