Double layer transfer process

Abstract

The invention relates to a method, comprising: the provision of a heterostructure comprising a growth substrate (1), an intercalated layer of two-dimensional material (2) and an epitaxial layer of semiconductor material (3); the provision of a rigid substrate (4) comprising a weakening plane (5); the realization of a first assembly by bonding the rigid substrate with the heterostructure, the first face (F) and the epitaxial layer (3) being at the bonding interface; the separation of the first assembly at the level of the intercalated layer of two-dimensional material (2) so as to obtain a second assembly resulting from the transfer of the epitaxial layer (3) from the heterostructure to the rigid substrate (4); the realization of a third assembly by bonding the second assembly with a target substrate (7), the epitaxial layer (3) being at the bonding interface; the separation of the third assembly along the weakening plane (5) of the rigid substrate (4).Figure for the abbreviation: Figure 6.

Description

Title of the invention: Double layer transfer method Technical field

[0001] The field of the invention is that of methods for manufacturing a stacked structure comprising a thin layer of semiconductor material adhering to a target substrate. The invention relates more particularly to methods which implement a 2D material-based layer transfer technique. Prior art

[0002] Remote epitaxy is a method for producing thin layers of semiconductor material discussed for example in Kim, H., Chang, C.S., Lee, S. et al. Remote epitaxy. Nat Rev Methods Primers 2, 40 (2022), https: / / doi.org / 10.1038 / s43586-022-00122-w.

[0003] This method consists of interposing, between a growth substrate and the semiconductor layer that is grown by epitaxy, a layer of two-dimensional material (2D material also called Van der Waals material or in English "Van der Waals material") which has strong atomic bonds in the plane but weak Van der Waals interactions out of the plane. This layer of 2D material behaves like a transparent pseudo-substrate: the crystalline structure of the epitaxial layer copies that of the growth substrate, as if the intermediate layer of 2D material did not exist. The advantage is that the epitaxial layer can be easily separated from the growth substrate due to the absence of covalent bonds between the growth substrate and the epitaxial layer. The substrate, which can be expensive, can thus be reused.

[0004] As explained in the article cited above, the separation at the level of the 2D material layer involves first depositing on the epitaxial layer a stressor layer (called stressor layef) made of nickel and then applying a thermal release adhesive film to the stress layer. The stack consisting of the adhesive film, the nickel layer and the epitaxial layer can then be exfoliated from the growth substrate following a detachment caused at the level of the 2D material layer by the supply of mechanical energy.

[0005] As reported in the article cited above, this sequence of steps has a certain number of drawbacks.

[0006] First, the deposition of a nickel layer induces contamination both at the level of the epitaxial layer which is in contact with the nickel layer and at the level of the growth substrate which is loaded into a metal deposition equipment. Additional protective layers can be deposited to limit contacts and interactions, and then be removed. Thus, several additional steps must be implemented to resolve this contamination problem, which affects the cost of the process, not to mention the impact of these additional steps on the quality of the epitaxial layer and its exfoliation.

[0007] Then, the deposition of the nickel layer is generally carried out by sputtering. The epitaxial layer therefore undergoes ion bombardment which degrades its quality over a few nanometers or even a few tens of nanometers of thickness. Consequently, particularly when the epitaxial layer has a small thickness and damage of a few tens of nanometers is then to be avoided, deposition of a protective layer may prove necessary to protect the epitaxial layer. Again, additional steps must be implemented, which impacts both the cost and the yield of the process.

[0008] In addition, stresses are applied to cause detachment at the 2D material layer. These stresses must be uniform throughout the detachment process and across the interface formed by the 2D material layer because small variations can result in fracture of the epitaxial layer in the event that these stresses exceed the mechanical failure limit of the epitaxial layer. The nickel layer helps, due to its thickness, to avoid such fracture during detachment but is not a panacea.

[0009] Finally, during this detachment, the epitaxial layer is subjected to flexing which is likely to cause cracks. The subsequent handling of this layer with a view to its transfer to a target substrate is also carried out by means of the adhesive film which is flexible. This also results in a risk of cracks or fracture of the epitaxial layer. Statement of the invention

[0010] The invention aims to propose a remote epitaxy technique which can overcome the aforementioned drawbacks and thus preserve the integrity of the epitaxial layer.

[0011] To this end, the invention proposes a double layer transfer method, comprising the steps of: • providing a hetero structure comprising a growth substrate, an interlayer of two-dimensional material on the growth substrate and at least one epitaxial layer of semiconductor material formed on the interlayer; • provision of a rigid substrate comprising a weakening plane formed by ion implantation through a first face of the rigid substrate, the weakening plane separating a thin layer from a solid portion of the substrate rigid ; • production of a first assembly by bonding the rigid substrate with the heterostructure, the first face of the rigid substrate and the at least one epitaxial layer of the heterostructure being at the bonding interface of the rigid substrate and the heterostructure; • separation of the first assembly at the level of the intermediate layer of two-dimensional material so as to obtain a second assembly resulting from the transfer of the at least one epitaxial layer of the heterostructure to the rigid substrate; • producing a third assembly by bonding the second assembly with a target substrate, the at least one epitaxial layer being at the bonding interface of the second assembly with the target substrate; • separation of the third assembly along the weakening plane of the rigid substrate so as to obtain a fourth assembly resulting from the transfer of the at least one epitaxial layer and the thin layer of the third assembly to the target substrate.

[0012] Some preferred but non-limiting aspects of this method are as follows: - the bonding of the rigid substrate with the heterostructure for the production of the first assembly is a bonding with surface activation; - the bonding of the rigid substrate with the heterostructure for the production of the first assembly is bonding by atomic diffusion; - the separation of the first assembly at the level of the intermediate layer of two-dimensional material comprises an input of mechanical and / or thermal energy; - the supply of thermal energy is carried out at a temperature lower than a separation temperature of the rigid substrate at the level of the weakening plane; - the growth substrate and the rigid substrate have thermal expansion coefficients that differ by at least 0.3 ppm / K; - the second assembly is subjected to one or more technological stages of manufacturing semiconductor structures, each carried out at a temperature lower than a separation temperature of the rigid substrate at the level of the embrittlement plane; - it further includes the removal of the thin layer of the fourth assembly; - it also includes, after removal of the thin layer, epitaxy of the semiconductor material on the at least one epitaxial layer; - the at least one epitaxial layer of semiconductor material comprises a layer of polar material, for example a layer of GaN; - the target substrate is a polycrystalline SiC substrate, a polycrystalline AlN substrate, a high electrical resistivity Si substrate or a substrate carrying a semi-insulating SiC layer; - the growth substrate is a silicon substrate of (111) orientation. Brief description of the drawings

[0013] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which Figures 1 to 12 represent a possible embodiment of a method according to the invention.

[0014] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0015] The invention relates to a dual layer transfer method which combines the transfer of a semiconductor layer from a growth substrate to a rigid substrate using the two-dimensional (2D) material-based transfer technique and then the transfer of the semiconductor layer from the rigid substrate to a target substrate using the Smart Cut™ transfer technique.

[0016] In the context of this double transfer, the use of the rigid substrate makes it possible to carry out the first transfer by detachment at the level of the two-dimensional material without generating cracks in the semiconductor layer and without requiring a metal stress layer. This use also allows the manipulation of the semiconductor layer in order to transfer it onto the target substrate without cracks or fractures in the semiconductor layer.

[0017] The method according to the invention comprises a step of providing a heterostructure comprising a growth substrate, an interlayer of two-dimensional material on the growth substrate and one (or more) epitaxial layer(s) of semiconductor material formed on the interlayer.

[0018] This provision may be the consequence of the manufacture of the heterostructure within the framework of a possible embodiment of the method according to the invention.

[0019] With reference to [Fig. 1], in this embodiment the method comprises providing the growth substrate 1, which is for example a substrate of Si (of orientation (111) in particular), sapphire or GaN.

[0020] With reference to [Fig. 2], in this embodiment the method then comprises the formation of the interlayer of two-dimensional material 2 on the growth substrate 1. This formation can be carried out after planarization of the surface of the growth substrate, for example by means of chemical-mechanical polishing. Cleaning of the surface of the growth substrate can also be carried out. This formation can comprise the deposition of the two-dimensional material 2 on the growth substrate 1. growth 1. In a non-exhaustive manner, this deposition can be carried out by means of molecular beam epitaxy (MBE for “Molecular Beam Epitaxy”), chemical vapor deposition (CVD for “Chemical Vapor Deposition”) or atomic layer epitaxy (ALD for “Atomic Layer Epitaxy”).

[0021] The two-dimensional material may be hexagonal boron nitride h-BN, graphene or more generally any 2D “Van der Waals” material allowing remote epitaxy to be carried out. The layer of two-dimensional material is thus made up of monoatomic sheets having weak interactions between them and the number of which is limited to allow remote epitaxy of the layer of semiconductor material. In one possible embodiment, the number of sheets may be less than three.

[0022] With reference to [Fig. 3], in this embodiment the method further comprises the growth of the epitaxial layer of semiconductor material 3 on the interlayer 2. This growth is generally carried out in two main steps: nucleation on the layer of two-dimensional material and standard growth of the epitaxial layer of semiconductor material. These two steps can be carried out at different growth temperatures, the nucleation being able to be carried out at a lower temperature than the standard growth.

[0023] The thickness of the epitaxial layer 3 is typically between 100 nm and a few microns, preferably between 500 nm and 2 microns, particularly in the case of a GaN epitaxial layer. The epitaxial layer of semiconductor material may be a layer of polar material, for example a layer of GaN, AIN or SiC. Taking the case of a GaN or AIN layer, it has, by its polar character, the characteristic of having, on one face, a surface consisting mainly of nitrogen atoms (so-called N-type surface) and, on the other face, a surface consisting mainly of gallium atoms (so-called Ga-type surface) or aluminum atoms (Al-type surface). In this case, the Ga-type or Al-type surface is found at the interface with the layer of two-dimensional material 2 while the N-type surface forms a free surface.The same is true for a SiC layer where we find a Si-type surface at the interface with the two-dimensional material layer 2 while a C-type surface forms a free surface.

[0024] In one possible embodiment, the method comprises the growth of several epitaxial layers forming a stack of crystalline layers. In the following, the example of a single epitaxial layer will be taken, it being understood that the invention is not limited to this scenario.

[0025] The method according to the invention further comprises a step of providing a rigid substrate which comprises a weakening plane formed by ion implantation through a first face of the rigid substrate. This weakening plane separates a layer thin part of a massive part of the rigid substrate.

[0026] This provision may be the consequence of the preparation of the rigid substrate within the framework of a possible embodiment of the method according to the invention.

[0027] With reference to [Fig.4], in this embodiment the method comprises providing the rigid substrate 4, preferably an inexpensive substrate, for example a silicon substrate, in particular a silicon substrate of (111) crystal orientation.

[0028] Then with reference to [Fig. 5], in this embodiment the method comprises the implantation of ionic species through a face F of the rigid substrate 4 so as to form there a weakening plane 5 separating a thin layer 6 from a massive part of the rigid substrate. The implanted species typically comprise hydrogen and / or helium. A person skilled in the art is able to define the required implantation energy and dose.

[0029] Once the heterostructure and the implanted rigid substrate have been provided, the method according to the invention comprises, with reference to [Fig. 6], the production of a first assembly by bonding the rigid substrate 4 with the heterostructure. This bonding is carried out so that the first face of the rigid substrate 4 and the epitaxial layer 3 of the heterostructure are at the bonding interface of the rigid substrate and the heterostructure.

[0030] The bonding is carried out in such a way as to obtain a binding energy at the bonding interface of the rigid substrate and the heterostructure greater than the binding energy of the Van der Waals interface between the two-dimensional material and the epitaxial layer.

[0031] The bonding can be carried out at room temperature. In one possible embodiment, it is carried out under reduced pressure. A heat treatment to strengthen the bonding can also be implemented, at a temperature lower than that of a heat treatment which would lead to the separation of the rigid substrate at the level of the weakening plane.

[0032] In a preferred embodiment making it possible to obtain a highly resistant bonding interface, the bonding of the rigid substrate with the heterostructure for producing the first assembly is a bonding with surface activation (bonding known as SAB for “Surface Activated Bonding”), a bonding by atomic diffusion (bonding known as ADP for “Atomic Diffusion Bonding”) or even a hydrophilic bonding accompanied by annealing to strengthen the bonding.

[0033] With reference to [Fig.7], the method then comprises the separation of the first assembly at the level of the interlayer of two-dimensional material 2 so as to obtain, as shown in [Fig.8], a second assembly resulting from the transfer of the epitaxial layer 3 of the heterostructure to the rigid substrate 4.

[0034] This separation of the epitaxial layer 3 from the growth substrate 1 can be carried out by means of a supply of mechanical and / or thermal energy at the level of the layer of two-dimensional material 2. When carried out by means of a supply of thermal energy in conjunction or not with a supply of mechanical energy, the separation exploits a stress induced during heating or subsequent cooling due to a difference in the coefficient of thermal expansion between the growth substrate 1 and the rigid substrate 4. To do this, the growth substrate and the rigid substrate preferably have coefficients of thermal expansion which differ by at least 0.3 ppm / K. The supply of thermal energy is carried out at a temperature lower than that of a heat treatment which would lead to the separation of the rigid substrate at the level of the embrittlement plane. As an example of an embodiment, it is possible to use a growth substrate 1 made of GaN (which has a coefficient of thermal expansion of 5.6 ppm / K) and a rigid substrate 4 made of Si (which has a coefficient of thermal expansion of 2.6ppm / K), perform the first assembly by bonding at room temperature and then implement heating to induce a compressive stress in the GaN substrate.

[0035] It will be noted that it is advantageous to carry out the implantation in the rigid substrate before the bonding and detachment illustrated in FIGS. 6 and 7. This in fact makes it possible to preserve the integrity of the epitaxial layer 3 compared to a solution which would consist of carrying out the implantation in the rigid substrate after the detachment of the [Fig.7] in the epitaxial layer 3 and through it.

[0036] In a possible embodiment, after the detachment of [Fig.7], the second assembly illustrated by [Fig.8], and more particularly the epitaxial layer 3 transferred onto the rigid substrate 4, is subjected to one or more technological steps for manufacturing semiconductor structures. These steps may in particular consist of cleaning, polishing, deposition or etching. Each of these steps is carried out at a temperature lower than that of a heat treatment which would lead to the separation of the rigid substrate at the level of the embrittlement plane.

[0037] Following the obtaining of the second assembly illustrated by [Fig.8], the method comprises, with reference to [Fig.9], the production of a third assembly by bonding the second assembly with a target substrate 7, the epitaxial layer 3 being at the bonding interface of the second assembly with the target substrate. This bonding may be a hydrophilic bond, possibly accompanied by annealing to strengthen the bonding.

[0038] Then with reference to [Fig. 10], the method comprises the separation of the third assembly along the weakening plane 5 of the rigid substrate 4. As shown in [Fig. 11], this separation leads to obtaining a fourth assembly resulting from the transfer of the epitaxial layer 3 and the thin layer 6 of the third assembly to the target substrate 7. This separation is typically obtained by implementing a heat separation treatment at a temperature which can be between 200°C and 600°C for silicon.

[0039] It should be noted that the method according to the invention makes it possible to recycle the substrate of growth and the rigid substrate for their reuse in an identical process or for another purpose.

[0040] As shown in [Fig. 12], the method may then comprise removing the thin layer 6 from the fourth assembly, for example by etching, so as to retain only the epitaxial layer 3 on the target substrate 7.

[0041] After removal of the thin layer 6, the method may also comprise a resumption of epitaxy on the epitaxial layer. It will be noted that when the epitaxial layer is a layer of polar material, the double transfer carried out by the invention advantageously makes it possible to expose the surface (for example of the Ga, Al or Si type) of the epitaxial layer allowing such a resumption of epitaxy of the semiconductor material on the epitaxial layer.

[0042] The target substrate 7 may be a polycrystalline SiC substrate or a polycrystalline AlN substrate. Or, the target substrate 7 may be a Si substrate with high electrical resistivity. Or, the target substrate may be a substrate carrying a semi-insulating SiC layer, for example a Si substrate, possibly with high electrical resistivity, carrying such a semi-insulating SiC layer. The epitaxial layer 3 transferred onto a target substrate according to these examples may be a GaN layer. By semi-insulating material, we mean a material typically having an electrical resistivity greater than or equal to 105 Q / cm. By high electrical resistivity material, we mean a material typically having an electrical resistivity greater than or equal to 100 Q / cm.

Claims

Claims

1. A double layer transfer method, comprising the steps of: • providing a heterostructure comprising a growth substrate (1), an interlayer of two-dimensional material (2) on the growth substrate and at least one epitaxial layer of semiconductor material (3) formed on the interlayer; • providing a rigid substrate (4) comprising a weakening plane (5) formed by ion implantation through a first face (F) of the rigid substrate, the weakening plane separating a thin layer (6) from a solid portion of the rigid substrate; • producing a first assembly by bonding the rigid substrate with the heterostructure, the first face (F) of the rigid substrate and the at least one epitaxial layer (3) of the heterostructure being at the bonding interface of the rigid substrate and the heterostructure;• separation of the first assembly at the level of the interlayer of two-dimensional material (2) so as to obtain a second assembly resulting from the transfer of the at least one epitaxial layer (3) of the heterostructure to the rigid substrate (4); • production of a third assembly by bonding the second assembly with a target substrate (7), the at least one epitaxial layer (3) being at the bonding interface of the second assembly with the target substrate; • separation of the third assembly along the weakening plane (5) of the rigid substrate (4) so ​​as to obtain a fourth assembly resulting from the transfer of the at least one epitaxial layer (3) and the thin layer (6) of the third assembly to the target substrate (7).;

2. Method according to claim 1, in which the bonding of the rigid substrate with the heterostructure for the production of the first assembly is a bonding with surface activation.

3. The method of claim 1, wherein bonding the substrate rigid with the heterostructure for the realization of the first assembly is a bonding by atomic diffusion.

4. Method according to one of claims 1 to 3, in which the separation of the first assembly at the level of the intermediate layer of two-dimensional material comprises an input of mechanical and / or thermal energy.

5. The method of claim 4, wherein the supply of thermal energy is carried out at a temperature below a separation temperature of the rigid substrate at the embrittlement plane.

6. The method of claim 5, wherein the growth substrate and the rigid substrate have coefficients of thermal expansion that differ by at least 0.3 ppm / K.

7. Method according to one of claims 1 to 6, in which the second assembly is subjected to one or more technological steps of manufacturing semiconductor structures, each carried out at a temperature lower than a separation temperature of the rigid substrate at the level of the weakening plane.

8. A method according to one of claims 1 to 7, further comprising removing the thin layer (6) from the fourth assembly.

9. The method of claim 8, further comprising after removal of the thin layer, epitaxy of the semiconductor material on at least one epitaxial layer.

10. Method according to one of claims 1 to 9, in which the at least one epitaxial layer of semiconductor material comprises a layer of polar material, for example a layer of GaN.

11. The method of one of claims 1 to 10, wherein the target substrate is a polycrystalline SiC substrate, a polycrystalline AlN substrate, a high electrical resistivity Si substrate, or a substrate carrying a semi-insulating SiC layer.

12. A method according to one of claims 1 to 11, wherein the growth substrate is a (111) orientation silicon substrate.

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