Microelectronic device and its fabrication process

Abstract

Title: Microelectronic Device and its Manufacturing Method The invention relates to a heterojunction bipolar transistor (HBT) comprising, on a silicon substrate (1): a layer (3) of a first III-V material, a first mesa structure (45M) on said layer (3), comprising: a collector layer (4), based on a second III-V material having an N conductivity, and a base layer (5), based on the second III-V material having a P+ conductivity, a second mesa structure (6M) comprising an emitter layer (6) based on the first III-V material having an N conductivity, said transistor (HBT) comprising collector (30), base (50), and emitter (60) contacts of a conductive material suitable for the metallurgy of the metal levels of a CMOS transistor-based integrated circuit, said transistor (HBT) comprising an encapsulation layer of a dielectric material,covering the first and second mesa structures (45M, 6M), and the collector, base and emitter contacts (30, 50, 60), in a dielectric material suitable for insulating the metal levels of a CMOS transistor-based integrated circuit. Figure for the abstract: Fig. 34,

Description

Title of the invention: Microelectronic device and its manufacturing process technical field

[0001] The present invention relates generally to microelectronic devices. Its particularly advantageous application lies in the fabrication of HBT heterojunction bipolar transistors for radio frequency (RF) components. PRIOR TECHNOLOGY

[0002] In the field of telecommunications and very high-speed data transmission, typically for data flows exceeding 100 Gbits / s, it is necessary to have RF components operating at high working frequencies, typically at frequencies between 250 GHz and 325 GHz.

[0003] For such RF components, effective power amplification with a cutoff frequency three to five times higher than the component's operating frequency is required. Bipolar heterojunction HBT transistors, based on IILV heterojunctions, perform best for power amplification at frequencies above 250 GHz.

[0004] Such HBT transistors are currently developed on small-format substrates, typically less than 100 mm in diameter, and employ architectures that are difficult to integrate industrially, based, for example, on submicron air bridges or materials with limited compatibility. Current HBT transistor technologies do not allow for continuous scaling, i.e., a reduction in size sufficient to achieve the performance increases targeted by the next generations of RF components. Furthermore, the compatibility of these technologies with so-called "back end of line" (BEOL) interconnection methods is poor. This limits the possibilities for integrating HBT transistors into integrated circuits based on CMOS (complementary metal-oxide-semiconductor) transistor technology.

[0005] The document “AD Carter et al., Si / InP Heterogeneous Integration Techniques from the Wafer-Scale (Hybrid Wafer Bonding) to the Discrete Transistor (Micro-Transfer Printing), 2018 IEEE SOL3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 2018, pp. 1-4” discloses an InP-based HBT transistor integration solution comprising an interconnection portion in BCB (Benzocyclobutan) connected by a hybrid bonding interface to a CMOS interconnection portion. This architecture remains difficult to implement. The assembly between the CMOS portion and the HBT portion must be This is done at the end of the process, after all interconnection levels have been implemented. Such an integration architecture limits application possibilities. HBT transistors cannot be integrated within the CMOS section, for example, between different CMOS interconnection levels. Transmission losses between the various electronic functions of the integrated circuit, typically between the power amplification provided by the HBT transistors and the antennas or passive elements of the BEOL metal levels, are not optimized. High-frequency operation is therefore limited.

[0006] Another solution disclosed in the paper "TE Kazior et al., Progress and challenges in the direct monolithic integration of III-V devices and Si CMOS on Silicon substrates, 2009 IEEE International Conference on Indium Phosphide & Related Materials, Newport Beach, CA, 2009, pp. 100-104" consists of co-integrating portions of IILV components by local epitaxy within the CMOS stack, maintaining a separation space around these IILV component portions. This solution limits the component density of such a cointegrated circuit. Selective growth and stress management during growth further complicate the process.

[0007] There is therefore a need to improve the integration of IILV HBT transistors in a CMOS integrated circuit.

[0008] An object of the present invention is to meet this need, in particular by proposing a more versatile and compact HBT transistor architecture and integration system.

[0009] Another object of the present invention is to propose a method for making such an HBT transistor, and an integration method.

[0010] The other objects, features and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0011] To achieve this objective, according to one embodiment, a heterojunction bipolar transistor is provided comprising, stacked along a z-direction on a silicon-based substrate: - a first layer made of a first IILV material exhibiting a first type of conductivity with a first level of N+ doping, - a first mesa-like structure on the first layer, comprising: • a so-called collector layer, based on a second IILV material exhibiting the first type of conductivity with a second level of N doping, and • a so-called base layer, based on a third material IILV exhibiting a second type of conductivity with a first level of P+ doping, - a second mesa structure on the first mesa structure, comprising an emitter layer based on a fourth III-V material exhibiting the first type of conductivity with a third N-type doping level.

[0012] The transistor further comprises a collector contact on the first layer, at the edge of the first mesa structure, a base contact on the base layer, at the edge of the second mesa structure, and an emitter contact on the emitter layer. Advantageously, the collector, base, and emitter contacts are based on a conductive material suitable for the metal-layer metallurgy of a metal-oxide-semiconductor (CMOS) complementary transistor integrated circuit. According to one possibility, the conductive material is taken from W, Ti, TiN, Ni and its alloys NiSi, NiPt, and Cu.

[0013] The transistor further comprises an encapsulation layer based on a dielectric encapsulation material, said encapsulation layer covering the first layer, the first and second mesa structures, and the collector, base, and emitter contacts. Advantageously, the encapsulation layer is based on a dielectric material suitable for insulating the metal layers of a metal-oxide-semiconductor (CMOS) complementary transistor integrated circuit. According to one possibility, the dielectric material is taken from SiO2 or SiNx.

[0014] Thus, the HBT transistor can be easily and directly integrated into a CMOS transistor-based integrated circuit. During the development of the present invention, simulations of the expected performance of the HBT transistor showed that the choice of materials suitable for BEOL integration made it possible to achieve a cutoff frequency on the order of THz, which is compatible with the target operating frequencies in the 220 GHz to 325 GHz range.Contrary to the prevailing assumptions of the prior art which advocate the use of BCB for the intermetallic dielectric and noble metals for the contacts to obtain the required performance, it has been shown in the context of the present invention that an HBT transistor architecture based on conductive and dielectric materials suitable for BEOL type integration is sufficient to obtain the required performance, with a performance level of around 80% to 85% of the reference performance level established for HBT transistors using BCB and noble metals.

[0015] The invention also relates to a method for making a heterojunction bipolar transistor comprising at least the following steps: - a supply of a stack comprising, along a direction z, a substrate silicon-based, a first layer in a first III-V material exhibiting a first type of conductivity with a first level of N+ doping, - formation by epitaxy on the first layer of a so-called collector layer, based on a second III-V material exhibiting the first type of conductivity with a second level of N doping, and - the formation by epitaxy on the collector layer of a so-called base layer, based on a third III-V material exhibiting a second type of conductivity with a first level of P+ doping, - formation by epitaxy on the base layer of a so-called emitter layer, based on a fourth III-V material exhibiting the first type of conductivity with a third level of N doping, - a first structuring in the form of a mesa of the collector and base layers, configured to form a first mesa structure having a dimension L1 along a y direction perpendicular to the z direction, - a second mesa-shaped structure of the emitter layer, configured to form a second mesa-shaped structure with a dimension L2 smaller than the dimension L1 along the y direction, - the formation of a collector contact on the first layer, preferably at the edge of the first mesa structure, - the formation of a basal contact on the base layer, at the edge of the second mesa-like structure, - the formation of an emitter contact on the emitter layer, said collector, base and emitter contacts being formed from an electrically conductive material suitable for a metal-oxide-semiconductor (CMOS) complementary transistor-based integrated circuit, - a formation of at least one encapsulation layer covering the first layer, the first and second mesa structures, the collector, base and emitter contacts, said encapsulation layer being formed from a dielectric material suitable for insulating the metallic levels of a metal-oxide-semiconductor (CMOS) complementary transistor-based integrated circuit.

[0016] The invention also relates to an integration system and a method for integrating such an HBT transistor.

[0017] The integration system for at least one heterojunction bipolar transistor according to the invention typically comprises, stacked along a z-direction: - a first silicon-based substrate, - a layer comprising complementary metal-oxide-semiconductor CMOS transistors and initial levels of metallic interconnections linked to said CMOS transistors, - a bonding layer comprising a hybrid bonding type interface, including electrical connections with the first levels of metallic interconnects linked to the CMOS transistors, - a layer comprising at least one heterojunction bipolar transistor, and second levels of metallic interconnections interposed between the bonding layer and the layer comprising at least one heterojunction bipolar transistor, said second levels of metallic interconnections being electrically connected to the bonding layer and to at least one heterojunction bipolar transistor.

[0018] The method for integrating at least one heterojunction bipolar transistor according to the invention typically comprises: - a supply of a first stack comprising, along a direction z: • a first silicon-based substrate, • a layer comprising complementary metal-oxide-semiconductor CMOS transistors and initial levels of metallic interconnections linked to said CMOS transistors, • a first part of a bonding layer comprising a hybrid bonding type interface, including electrical connections with the first levels of metallic interconnections linked to the CMOS transistors, - a supply of a second stack comprising, along a z-direction: • a second silicon-based substrate, • a layer comprising at least one heterojunction bipolar transistor according to the invention, and second levels of metallic interconnections connected to said heterojunction bipolar transistor, • a second part of a bonding layer comprising a hybrid bonding type interface, including electrical connections with said second levels of metallic interconnections connected to the heterojunction bipolar transistor, - a hybrid bonding of the second part of the bonding layer onto the first part of the bonding layer, - a removal of the second silicon-based substrate, - a formation, on the layer comprising at least one heterojunction bipolar transistor, of at least a third level of interconnections. According to a Possibly, at least a third level of interconnections includes a so-called thick metal layer with a thickness at least twice that of the various metal thicknesses of the first and second levels of metallic interconnections located below the layer containing at least one heterojunction bipolar transistor. The thick metal layer typically has a thickness greater than or equal to 1 pm, for example, on the order of 3 pm.

[0019] Thus, the integration of the HBT transistor(s) is performed as close as possible to the BEOL metal levels. HBT transistor-based amplification circuits can therefore be interconnected with the components and passive elements of CMOS circuits with reduced connection distances. Such an integration system offers improved compactness. This helps to limit transmission losses associated with excessively long HBT / CMOS interconnections. An RF system based on such an architecture can advantageously operate at higher frequencies. Energy efficiency, in particular the electrical efficiency of the system, is also improved.

[0020] The HBT transistor and the integration system of this HBT transistor advantageously allow for the realization of compact and optimized RF circuit architectures, exhibiting improved RF performance. BRIEF DESCRIPTION OF THE FIGURES

[0021] The aims, objects, features and advantages of the invention will become clearer from the detailed description of embodiments thereof, which are illustrated by the following accompanying drawings in which:

[0022] [Fig.l][Fig.2][Fig.3][Fig.4][Fig.5][Fig.6][Fig.7][Fig.8][Fig.9][Fig.l0][Fig.ll][Fig.l2 ][Fig.13][Fig.14][Fig.15][Fig.16][Fig.17][Fig.18][Fig.19][Fig.20][Fig.21][Fig.22][Fig.23][Fig.24][Fig.25][Fig.26][Fig.27][Fig.28][Fig.29][Fig.30][Fig.31][Fig.32][Fig.33][Fig.34] Figures 1 to 34 schematically illustrate steps in a process for manufacturing an HBT transistor according to an embodiment of the present invention.

[0023] [Fig.35][Fig.36] Figures 35 and 36 schematically illustrate steps of a process for making an HBT transistor according to another embodiment of the present invention.

[0024] [Fig. 37][Fig. 38][Fig. 39] Figures 37 to 39 schematically illustrate a process integration and an integration system of an HBT transistor in a CMOS integrated circuit according to another embodiment of the present invention.

[0025] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, on the schematic diagrams, the thicknesses of the different layers and portions, and the dimensions of the patterns and structures are not representative of reality. DETAILED DESCRIPTION

[0026] Before proceeding to a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0027] According to one example, the heterojunction bipolar transistor comprises, stacked along a z-direction on a silicon-based substrate: - a first layer made of a first III-V material exhibiting a first type of conductivity with a first level of N+ doping, - a first mesa-like structure on the first layer, comprising: • a so-called collector layer, based on a second III-V material exhibiting the first type of conductivity with a second level of N doping, and • a so-called base layer, based on a third III-V material exhibiting a second type of conductivity with a first level of P+ doping, - a second mesa structure on the first mesa structure, comprising an emitter layer based on a fourth III-V material exhibiting the first type of conductivity with a third N-type doping level. - a collector contact on the first layer, at the edge of the first mesa structure, a base contact on the base layer, at the edge of the second mesa structure, an emitter contact on the emitter layer, the collector, base and emitter contacts being based on a conductive material, typically based on a conductive material taken from among W, Ti, TiN, Cu, Ni and its alloys NiPt, NiSi, - an encapsulation layer based on a dielectric encapsulation material, said encapsulation layer covering the first layer, the first and second mesa structures, and the collector, base and emitter contacts, the encapsulation layer being based on a dielectric material, typically based on a dielectric material taken from SiO2, SiN, Al2O3, SiCO, HfO2.

[0028] According to one example, the dielectric material is taken from among SiO2, SiN, A12O3, SiCO, HfO2. These materials are advantageously perfectly compatible with BEOL processes in CMOS technology.

[0029] According to one example, the conductive material is taken from W, Ti, TiN, Cu, Nb, Ni and Its NiPt and NiSi alloys. These materials are advantageously perfectly compatible with BEOL processes in CMOS technology.

[0030] According to one example, the first and fourth III-V materials are based on InP, and the second and third III-V materials are based on InGaAs.

[0031] According to another example, the second III-V material is based on InP, and the third III-V material is based on GaAsSb, and the fourth III-V material is based on InGaP and / or InP.

[0032] According to one example, the first layer of a first III-V material is directly on the silicon-based substrate. According to another example, an intercalated layer, typically a bonding layer based on a dielectric or metallic material, is intercalated between the first layer of a first III-V material and the silicon-based substrate.

[0033] According to one example, the base contact has a central portion and a peripheral portion surrounding the central portion such that the peripheral portion is thinner than the central portion. The thickness of the peripheral portion of the base contact decreases with distance from the central portion. This typically reduces parasitic capacitance between the base contact and the emitter contact.

[0034] According to one example, the collector contact has a central portion and a peripheral portion surrounding the central portion such that the peripheral portion is thinner than the central portion. The thickness of the peripheral portion of the collector contact decreases with distance from the central portion. This typically reduces parasitic capacitance between the collector contact and the base contact and / or the emitter contact.

[0035] According to one example, the process for making a heterojunction bipolar transistor comprises at least the following steps: - a supply of a stack comprising, along a z-direction, a silicon-based substrate, a dielectric layer, a first layer of a first III-V material exhibiting a first type of conductivity with a first N+ doping level, - formation by epitaxy on the first layer of a so-called collector layer, based on a second III-V material exhibiting the first type of conductivity with a second level of N doping, and - the formation by epitaxy on the collector layer of a so-called base layer, based on a third III-V material exhibiting a second type of conductivity with a first level of P+ doping, - formation by epitaxy on the base layer of a so-called emitter layer, based on a fourth III-V material exhibiting the first type conductivity with a third level of N doping, - a first mesa-like structuring of the collector and base layers, configured to form a first mesa-like structure with dimension L1 along a y-direction perpendicular to the z-direction, - a second mesa-like structuring of the emitter layer, configured to form a second mesa-like structure with dimension L2 smaller than dimension L1 along the y-direction, - the formation of a collector contact on the first layer, preferably at the edge of the first mesa structure, - the formation of a basal contact on the base layer, at the edge of the second mesa-like structure, - the formation of an emitter contact on the emitter layer, said collector, base and emitter contacts being formed from an electrically conductive material, typically from an electrically conductive material taken from W, Ti, TiN, Cu, - a formation of at least one encapsulation layer covering the first layer, the first and second mesa structures, the collector, base and emitter contacts, said encapsulation layer being formed from a dielectric material, typically from a dielectric material taken from SiO2, SiN.

[0036] According to one example, the formation of the first and second mesa structures is achieved respectively by a first etching along the z-axis of the collector and base layers, and by a second etching along the z-axis of the emitter layer. Such a fabrication process is generally called "top-down." This allows for better control of the crystalline quality of the different layers and the dimensions of the different structures.

[0037] According to one example, the first and second etchings each comprise a wet isotropic etching step, such that the first and second mesa structures each have inclined flanks, overhanging respectively the first layer and the base layer. This reduces parasitic capacitances (particularly under the collector). This allows for self-aligned contacts.

[0038] According to another example, the first and second etchings each comprise a mixed dry and wet etching step.

[0039] According to an example, the following steps are carried out in the following chronological order: formation of the emitter contact, then formation of the second mesa structure, then formation of the base contact, then formation of the first mesa structure, then formation of the collector contact.

[0040] According to an example, the following steps are carried out in chronological order The next step is the formation of the second mesa structure, followed by the formation of the base contact, then the emitter contact, then the formation of the first mesa structure, and finally the collector contact. Forming the base contact before the emitter contact allows for a simpler, thinner base contact with a limited number of steps, typically achieved through chemical-mechanical polishing (CMP) without etching the base contact. The base contact can then have a top surface that is essentially in the same plane as a bottom surface of the emitter contact. This also limits the presence of metal during the etching of the semiconductor layers that constitute the emitter, thus preventing metallic contamination of the substrate or wafer.

[0041] According to one example, the collector contact formation comprises a first nitrogen plasma-assisted deposition of tungsten, intended to form a peripheral portion of the collector contact. The collector contact formation further comprises thinning the peripheral portion of the collector contact by preferentially etching the peripheral portion of the collector contact relative to a central portion of the collector contact. This makes it possible to move the peripheral portion of the collector contact further away from the base contact. The parasitic capacitance between the collector contact and the base contact is reduced. This also makes it possible to move the peripheral portion of the collector contact further away from the emitter contact. The parasitic capacitance between the collector contact and the emitter contact is reduced.

[0042] According to one example, the formation of the base contact comprises a first nitrogen plasma-assisted deposition of tungsten, intended to form a peripheral portion of the base contact. The formation of the base contact further comprises thinning the peripheral portion of the base contact by preferentially etching the peripheral portion of the base contact relative to a central portion of the base contact. This makes it possible to move the peripheral portion of the base contact further away from the emitter contact. The parasitic capacitance between the base contact and the emitter contact is reduced.

[0043] According to one example, the integration system further comprises, on the layer comprising at least one heterojunction bipolar transistor, at least one third level of interconnections. The layer comprising at least one HBT transistor is thus located between the first CMOS interconnection levels and at least one third level of interconnections. The third level of interconnections is typically a CMOS interconnection level.

[0044] According to one example, the third level of interconnections comprises a layer of so-called thick metal having a thickness at least twice greater than the different metal thicknesses of the first and second levels of metallic interconnections located below the layer comprising at least one heterojunction bipolar transistor. Such a thick metal layer includes, for example, patterns of passive components, such as transmission lines, antennas, etc.

[0045] According to one example, the thick metal layer is connected to the first layer of a first III-V material of the heterojunction bipolar transistor by a heat dissipation electrical connection, said heat dissipation electrical connection acting as a collector contact for the heterojunction bipolar transistor. Such an electrical connection on the rear side of the HBT, for the collector, allows for better management of heating and heat dissipation of the HBT. The significant thickness of the thick metal layer typically allows it to form a heat sink for the collector of the HBT.

[0046] According to one example, the first layer of a first III-V material of the layer comprising at least one heterojunction bipolar transistor is continuous and, in projection along the z-direction, completely covers the first silicon-based substrate. The first layer of a first III-V material and the first silicon-based substrate are typically the same size in the plane normal to the z-direction. This typically corresponds to the use of InPoSi (acronym for "InP on Silicon") substrates, which can advantageously reach large dimensions, for example, a diameter of 200 mm or even 300 mm. The possibility of designing large-scale HBT integration systems on CMOS improves the industrial implementation of this technology (less material waste and reduced cost).

[0047] According to one example, the first levels of metallic interconnections linked to the CMOS transistors comprise between three and five layers of metal.

[0048] Except where incompatibility exists, it is understood that all the above optional features can be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features of one aspect of the invention, for example the HBT transistor or the integration system, can be adapted mutatis mutandis to another aspect of the invention, for example the methods of implementation or integration.

[0049] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0050] A layer may also be composed of several sub-layers of the same different materials. The collector layer typically comprises several N-type layers with different doping levels and / or chemical compositions. For example, the collector layer includes several InP layers with decreasing doping levels (N+, N-, along the z-direction) in contact with an InGaAs layer with an N- doping level.

[0051] The emitter layer typically comprises different N-type layers, exhibiting different dopings and / or chemical compositions. The emitter layer comprises, for example, several InP layers with increasing doping levels (N-, N+, along the z-direction), and possibly a heavily N+-doped InGaAs layer at the emitter contact.

[0052] The base layer typically comprises a heavily doped P++ type InGaAs layer, for example sandwiched between the N- InGaAs layer of the collector layer and the N- InP layer of the emitter layer.

[0053] A substrate, stack, or layer "based" on a material A is understood to mean a substrate, stack, or layer comprising only that material A or that material A and possibly other materials, for example, alloying elements and / or dopant elements. Thus, an InP-based layer is understood, for example, to be an InP layer, an N-doped InP layer, an N+ doped InP layer, etc. An InGaAs-based layer may comprise an N-InGaAs sublayer and one or more InP sublayers.

[0054] The doping ranges associated with the different types of doping indicated in this application are as follows: - P++ or N++ doping: greater than 5 x 10¹⁹ cm³ - P+ or N+ doping: 1 x 10¹⁸ cm³ to 5 x 10¹⁹ cm³ - P or N doping: 1 x 10¹⁷ cm³ to 1 x 10¹⁸ cm³ - Intrinsic doping: 1 x 10¹⁵ cm³ to 1 x 10¹⁷ cm³

[0055] A material "suitable for" metallurgy or insulation of the interconnect levels of a CMOS integrated circuit is understood to be a material used or usable for CMOS integration, and in particular in BEOL processes. For example, "suitable for" means "adapted to," "appropriate for," "compatible with," "capable of," or even "intended for." A dielectric material suitable for insulating the interconnect levels of a CMOS integrated circuit may be based on, but not limited to: SiO2, SiN, SiON, SiOC, SiOCH, SiCN Al12O3, HfO2. An electrically conductive material suitable for metallurgy of the interconnect levels of a CMOS integrated circuit may be based on, but not limited to: W, Ti, TiN, Cu, Nb, Al, Mo, Ni, NiSi, NiPt, Ni2P, Co...

[0056] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator, typically for the intermetallic layers of BEOL levels. In the present invention, a material dielectric preferably has a dielectric constant less than 7.

[0057] The present invention enables, in particular, the fabrication of at least one HBT III-V transistor or a plurality of HBT III-V transistors on a Si substrate. This substrate may be bulk, or a semiconductor-on-insulator type. The Si substrate may, for example, be part of an InPoSi stack (InP on Silicon).

[0058] Selective etching with respect to or etching with selectivity with respect to means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. It is denoted SA:B. A selectivity SA:B of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.

[0059] A particular application of the invention relates to RF systems, especially RF amplification circuits. The invention can also be implemented more broadly for various microelectronic devices or components, for example in analog circuits or mixed-signal (digital / analog) circuits.

[0060] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.

[0061] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.

[0062] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions from the first step may be repeated later. Thus, the term "step" does not necessarily imply unitary actions that are inseparable in time and in the sequence of phases of the process.

[0063] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures. When only one coordinate system is shown on the same sheet of figures, this coordinate system applies to all the figures on that sheet.

[0064] In the present patent application, the thickness of a layer is taken along a direction normal to the principal extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms "on", "overlies", "under", "subsoil" refer to positions taken along the z direction.

[0065] The terms "vertical" and "vertically" refer to a direction along the z-axis. The terms "horizontal" and "horizontally" refer to a direction in the xy plane. Unless explicitly stated otherwise, thickness, height, and depth are measured along the z-axis.

[0066] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically in the figures.

[0067] The terms "approximately", "around", "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the bounds are inclusive, unless otherwise stated.

[0068] Figures 1 to 32 illustrate a first embodiment of the process for manufacturing the HBT transistor. In this embodiment, the HBT transistor is of the NPN (emitter-base-collector) type, with an InGaAs / InP heterojunction. Other configurations are perfectly feasible. In particular, other III-V materials can be used for the junctions or heterojunctions, in a known manner. The following alloys can notably be used for manufacturing the HBT transistor: InGaAs, InP, InGaP, GaAsSb. Those skilled in the art will be able to adapt the embodiment described below to their specific requirements.

[0069] As illustrated in [Fig. 1], a silicon-based substrate 1 (substrate Si) is first provided. According to one possibility, a stack of layers 3, 4, 5, 6 based on III-V materials, formed separately, can be transferred onto the silicon-based substrate 1, for example by SiO2-SiO2 bonding. The silicon-based substrate 1 then typically comprises a first bonding layer 21 based on SiO2, and the stack typically comprises a second bonding layer 22 based on SiO2. In this case, the silicon-based substrate 1 and the stack based on IILV materials can be assembled by molecular bonding between the first and second bonding layers 21, 22. The first bonding layer 21 can be based on thermal SiO2. It typically has a thickness on the order of 200 nm. The second bonding layer 22 can be formed by chemical vapor deposition (CVD) on the stack of layers based on IILV materials.It typically has a thickness of around 100 nm. In this case of transferring the stacking of layers based on IILV materials onto the Si substrate, said stacking has a lateral dimension, in the xy plane, for example a diameter, typically smaller than the lateral dimension, for example the diameter, of the Si substrate, as illustrated in [Fig. 1].

[0070] According to another possibility, the silicon-based substrate can typically be of the InPoSi type and comprise a "bulk" silicon part 1, a A buried oxide layer 2, called BOX (acronym for "Buried Oxide"), is surmounted by a surface InP layer 31. Such an InPoSi substrate can be obtained by a process known as "smart eut," which is widely recognized by those skilled in the art. In this case, the stacking of layers 3, 4, 5, and 6 based on III-V materials can be formed directly by epitaxy on the InPoSi substrate. Advantageously, the stacking of III-V material-based layers in this case has a lateral dimension in the xy plane, for example, a diameter, substantially equal to the lateral dimension, for example, the diameter, of the InPoSi substrate.

[0071] Regardless of how the stack of layers based on III-V materials is formed, either separately and then transferred by SiO2-SiO2 bonding onto the Si substrate, or directly by epitaxy onto the InPoSi substrate, the stack preferably comprises, along z and starting from the oxide layer 2: - a layer 31 based on InP, which can, depending on the case, be an InP-based bonding layer with the second bonding layer 22 or a surface InP layer of an InPoSi substrate. This layer 31 typically has a thickness of around 50 nm. - a layer 32 based on InGaAs, which serves as a stop layer for the etching process. It is known that etching can be stopped by detecting the end of the etch, by detecting the change in the nature of the materials being etched during etching and / or by taking advantage of the etching selectivity of the materials in the layer to be etched and the stop layer. This layer 32 typically has a thickness of around 20 nm. - a layer 33 based on N+-doped InP, which ensures good electrical conductivity under the collector of the HBT transistor. This layer 33 typically has a thickness of around 350 nm. - A layer 34 based on N+-doped InGaAs, which ensures good electrical conductivity under the collector of the HBT transistor. This layer 34 typically acts as an interface with the collector contact of the HBT transistor. This layer 34 typically has a thickness of approximately 20 nm. Layers 33 and 34 can form a layer 3, known as the sub-collector layer. - a layer 41 based on N+-doped InP, intended to form part of the collector. This layer 41 typically has a thickness of around 50 nm. - a layer 42 based on N-doped InP, intended to form part of the collector. This layer 42 typically has a thickness of around 85 nm. - a second layer 43 based on N-doped InP, intended to form part of the collector. This layer 43 typically has a thickness of the order of 25 nm. - a layer 44 based on N-doped InGaAs, intended to form part of the collector. This layer 44 typically has a thickness less than or equal to 20 nm, for example, on the order of 10 nm or 5 nm. Layers 41, 42, 43, and 44 typically form layer 4 of the collector. These different layers 41, 42, 43, and 44 are preferably configured so that the N-type doping gradually decreases between layer 41 and layer 44. This allows for better accommodation of the variations in conductivity and mechanical stresses within the stack. These layers 41, 42, 43, and 44 are typically dimensioned in terms of thickness and doping to manage the electric field and charge flow in the collector. - A P++-doped InGaAs layer 5, designed to form a first P / N junction with layer 44. This layer 5 typically forms the base of the HBT transistor. It is typically directly connected to the base contact of the HBT transistor. This layer 5 typically has a thickness of approximately 28 nm. Other materials are also possible for this base layer 5, for example, GaAsSb. - a layer 61 based on N-doped InP, intended to form a second P / N junction with layer 5, of the heterojunction type. This layer 61 typically forms part of the emitter. This layer 61 typically has a thickness on the order of 20 nm. - a 62 layer based on N+-doped InP, intended to form part of the emitter. This 62 layer typically has a thickness of around 30 nm. - a layer 63 based on N+-doped InGaAs, intended to form part of the emitter. This layer 63 typically acts as an interface with the emitter contact of the HBT transistor. This layer 63 typically has a thickness of approximately 20 nm. Layers 61, 62, and 63 typically form the emitter layer 6. - a 64-layer InP-based layer, which serves as a stop layer for the etching process. This 64-layer layer typically has a thickness of around 20 nm.

[0072] After formation of the stack of layers based on III-V materials, this stack is structured by different lithography and etching steps, and contacts are formed to realize the HBT transistor.

[0073] As illustrated in [Fig. 2], a planarization step can be carried out first. This step typically includes the deposition of a SiN-based layer 71, intended on the one hand to fill the spaces bordering the stack of III-V material-based layers, and on the other hand to form a mask on the stack of layers based of III-V materials. After deposition, chemical-mechanical polishing (CMP) typically allows the 71 layer to be planarized. The 71 layer above the stack typically has a thickness of around 150 nm after planarization.

[0074] A resin-based masking layer 81 is then formed on the layer 71 and subsequently structured by lithography to form one or more apertures 101 having a dimension L2 along x. The layer 71 is then etched through the aperture 101, typically by plasma-based dry etching or by reactive ion etching (RIE). The layer 64 of the stack is then etched through the aperture 101, typically by wet etching selectively with respect to the underlying layer 63. A top face 630 of the layer 63 is thus exposed after the successive etches through the aperture 101.

[0075] As illustrated in [Fig. 3], the masking layer 81 is then removed in a known manner by a so-called "stripping" step, typically by O2-based plasma. A metallic layer 11 is then deposited so as to fill the opening 101 of the layer 71. This metallic layer 11 may comprise several sub-layers, for example, Ti- and TiN-based tack layers, with thicknesses of 10 nm respectively, and a tungsten W-based main layer, of sufficient thickness to fill the opening of the layer 71. This tungsten W-based main layer has, for example, a thickness of approximately 225 nm.

[0076] As illustrated in [Fig. 4], a chemical-mechanical polishing (CMP) process is performed to remove excess metal deposited on layer 71. The CMP polishing is stopped at layer 71 in order to retain the portion of the metallic layer within the opening of layer 71. The emitter contact 60 is thus formed. Here, it is in contact with the N+-doped InGaAs-based layer 63.

[0077] As illustrated in [Fig.5], part of layer 71 is then removed by engraving, so as to expose an upper face 640 of layer 64.

[0078] As illustrated in [Fig. 6], the stack layers 64, 63, 62, 61 are then etched around the emitter contact 60, so as to expose an upper face 500 of the layer 5. The layers 64, 63, 62, and part of the InP-based layer 61, are typically etched by dry etching, stopping in layer 61. A finishing wet etch then removes the remaining portion of the InP-based layer 61, selectively at the InGaAs P++-based layer 5. A mesa 6M structure of dimension L2 along x is thus obtained under the emitter contact 60. This mesa 6M structure has flanks 601 that may be slightly inclined with respect to the vertical. This is typically due to the isotropic nature of the etches, particularly the wet etch. This also stems from the crystallography of InP and InGaAs, insofar as some crystal planes etch faster than others.

[0079] As illustrated in [Fig. 7], a SiN-based layer 72 is then formed by A conformal coating is deposited at 300°C on the exposed face 500, and on the sides 601 and the emitter contact 60. This layer 72 typically has a thickness of approximately 30 nm. A SiO2-based layer 73 is then formed on the layer 72, for example by deposition at 400°C. This layer 73 typically has a thickness of approximately 400 nm. A planarization step by CMP polishing is then performed on the layer 73.

[0080] As illustrated in [Fig. 8], the CMP polishing of layer 73 is typically stopped at the SiN-based layer 72 at the top of the emitter contact 60. A resin-based masking layer 82 is then formed on layer 73 and on the portion of layer 72 at the top of the emitter contact 60, and subsequently structured by lithography to form apertures 102, for example by e-beam electron lithography. The apertures 102 are formed on either side of the emitter contact 60. A top face 730 of layer 73 is thus exposed through the apertures 102.

[0081] As illustrated in [Fig. 9], layers 73 and 72 are then etched through the openings 102, typically by dry etching. The etching process stops at layer 5, which is based on InGaAs P++. A top surface 500 of layer 5 is thus exposed after etching through the openings 102.

[0082] As illustrated in [Fig. 10], the masking layer 82 is removed by "stripping". A metallic layer 12 is then deposited so as to fill the openings 102 of the layer 73. This metallic layer 12 may comprise several sub-layers, for example, Ti- and TiN-based tack layers, with thicknesses of 10 nm respectively, and a tungsten W-based main layer, of sufficient thickness to fill the openings of the layer 73. This tungsten W-based main layer has, for example, a thickness of approximately 375 nm.

[0083] As illustrated in [Fig. 1 1], a mechano-chemical polishing is first carried out so as to remove the excess metal deposited on the layer 73. The CMP polishing is stopped on the layer 73, in order to retain the portions 50' of metal layer 12 in the openings of the layer 73.

[0084] As illustrated in [Fig. 12], these portions of the metallic layer are then thinned to form the base contacts 50, typically so that the upper faces of the base contacts 50 are located below a plane passing through the lower face of the emitter contact 60. This minimizes the parasitic capacitances between the emitter contact 60 and the base contacts 50. Such thinning typically reduces these parasitic capacitances by 55%, compared to unthinned base contacts 50' with a height substantially equal to the thickness of the layer 73, as illustrated in [Fig. 11].

[0085] The W-shaped metal layer portions can be thinned by wet etching with Potassium Triiodide KII2. The Ti / TiN metal layer portions, at The contact edges of the base 50 can be removed by dry etching. Base 50 contacts are thus formed directly in contact with the P++-doped InGaAs-based layer 5.

[0086] According to one possibility illustrated in [Fig. 13], the thinning is carried out differentially, in order to obtain peripheral portions 50p of the contact 50 that are thinner than the central portion 50c of the contact 50. Such differential thinning can occur when the deposition of the tungsten-based W main layer is performed by CVD assisted by nitrogen-containing N+ plasma. The peripheral portions 50p of the contact 50 are then preferentially etched over the central portion 50c of the contact 50. The peripheral portions 50p typically exhibit a thickness profile decreasing from the central portion 50c. In this case, the parasitic capacitances between the emitter contact 60 and the base contacts 50 are further reduced.Such differential thinning typically reduces these parasitic capacitances by 70%, compared to unthinned basic contacts 50' with a height approximately equal to the thickness of layer 73, as illustrated in [Fig. 11].

[0087] As illustrated in [Fig. 14], a SiN-based layer 74 is then formed by conformal deposition at 400°C on the layer 73, and on the base contacts 50 and the emitter contact 60. This layer 74 typically has a thickness of approximately 60 nm. A resin-based masking layer 83 is then formed and structured, for example by e-beam electron lithography, over the base contacts 50 and the emitter contact 60, while retaining exposed portions of layer 74 around the base contacts 50.

[0088] As illustrated in [Fig. 15], layers 74, 73, and 72 are then etched around the masking layer 83, typically by dry etching. The etching process stops at the InGaAs P++-based layer 5. A top face 500 of layer 5 is thus exposed after etching. The protruding structure of layer 5, comprising the base contacts 50, the mesa structure 6M, the emitter contact 60, and the masking layer 83, typically has an L1 dimension along x. The masking layer 83 is then removed by stripping ([Fig. 16]).

[0089] As illustrated in [Fig.17], the layers 5, 44, 43, 42 and 41 of the stack are then etched around the base contacts 50. The layers 5, 44, 43, 42 and part of the InP-based layer 41 are typically etched by dry etching, with a stop in layer 4L. The partial dry etching of the InP-based layers 43, 42 and 41 can be configured to stop at an etching depth of approximately 140 nm from the interface between layer 43 and layer 44, so as to maintain a residual thickness of layer 41 at the end of the dry etching.

[0090] As illustrated in [Fig. 18], a finishing wet etching then allows the remaining part of the InP-based layer 41, preferably select, to be removed. tively to the InGaAs N+-based layer 34, so as to expose a top face 300 of the layer 34. A 45M mesa structure is thus obtained under the base contacts 50. This 45M mesa structure, with dimension L1 along x, typically exhibits flanks 451 that may be slightly inclined with respect to the vertical. This is typically due to the isotropic nature of the etchings, particularly wet etching.

[0091] As illustrated in [Fig. 19], a SiN-based layer 74 is then formed by conformal deposition at 300°C on the exposed face 300, and on the flanks 451, the base contacts 50, and the emitter contact 60. This layer 74 typically has a thickness of approximately 60 nm. A SiO2-based layer 75 is then formed on the layer 74, for example, by deposition at 400°C. This layer 75 typically has a thickness of approximately 750 nm. A planarization step by CMP polishing is then performed on the layer 75, stopping on the protruding parts of the SiN-based layer 74.

[0092] As illustrated in [Fig.20], a resin-based masking layer 84 is then formed on the layer 75 and on the protruding parts of the layer 74, and then structured by lithography to form openings 103. The openings 103 are formed on either side of the base contacts 50.

[0093] As illustrated in [Fig. 21], layers 75 and 74 are then etched through the openings 103, typically by dry etching. The etching process stops at layer 34, which is based on InGaAs N+. A top surface 300 of layer 34 is thus exposed after etching through the openings 103.

[0094] As illustrated in [Fig. 22], the masking layer 84 is removed by "stripping". A metallic layer 13 is then deposited so as to fill the openings 103 of the layer 75. This metallic layer 13 may comprise several sub-layers, for example, Ti- and TiN-based tack layers, with thicknesses of 10 nm respectively, and a tungsten W-based main layer, of sufficient thickness to fill the openings of the layer 75. This tungsten W-based main layer has, for example, a thickness of approximately 750 nm.

[0095] As illustrated in [Fig. 23], a mechano-chemical polishing is first carried out to remove the excess metal deposited on layer 75. The portions of the metal layer 13 in the openings of layer 75 are then thinned to form the collector contacts 30, typically such that the upper faces of the collector contacts 30 lie below a plane passing through the lower faces of the base contacts 50. This minimizes parasitic capacitances between the collector contacts 30 and the base contacts 50. It also minimizes parasitic capacitances between the collector contacts 30 and the emitter contact 60.

[0096] The portions of the metallic layer 13 in W can be thinned by etching Wet etching using potassium triiodide (KII2), for example, to an etching depth of approximately 270 nm. The portions of the Ti / TiN metallic layer at the flanks of the collector contacts 30 can be removed by dry etching. Collector contacts 30 are thus formed in direct contact with the N+-doped InGaAs layer 34. Alternatively, the collector contacts 30 can be thinned by differential thinning as described above. The collector contacts 30 then have a peripheral portion that is relatively thinner than their central portion.

[0097] As illustrated in [Fig. 24], a SiN-based layer 76 is then formed by conformal deposition at 400°C on the layer 75 and on the collector contacts 30. This layer 76 typically has a thickness of approximately 30 nm. A SiO2-based layer 77 is then formed on the layer 76, for example by deposition at 400°C. This layer 77 typically has a thickness of approximately 400 nm. A planarization step by CMP polishing is then performed on the layer 77.

[0098] A HBT transistor based on III-V materials, on a Si substrate, and encapsulated by SiO2 / SiN dielectric materials, is thus obtained. The following steps aim to form the contact vias on the various emitter, base, and collector contacts of the HBT transistor.

[0099] As illustrated in [Fig. 25], a resin-based masking layer 85 is formed on the layer 77 and structured, typically by e-beam electron lithography. An opening 104 is made above the emitter contact 60, first in the layer 85, then in the stack of dielectric layers up to the emitter contact 60.

[0100] As illustrated in [Fig. 26], after stripping the masking layer 85, a new resin-based masking layer 86 is formed on the layer 77 and structured, typically by electron beam lithography. An opening 105 is made above the base contact 50, first in the layer 86, then in the stack of dielectric layers up to the base contact 50. The opening 104 above the emitter contact 60 is typically filled by the layer 86 at this stage.

[0101] As illustrated in [Fig. 27], after stripping the masking layer 86, a new resin-based masking layer 87 is formed on the layer 77 and structured, typically by electron beam lithography. An opening 106 is made above the collector contact 30, first in the layer 87, then in the stack of dielectric layers up to the collector contact 30. The openings 104, 105 respectively above the emitter contact 60 and the base contact 50 are typically filled by the layer 87 at this stage.

[0102] As illustrated in [Fig. 28], after stripping of the masking layer 87, interconnections 55, 65, 35, also called contact vias, are formed in the or Openings 105, 104, and 106 are formed to connect the base, emitter, and collector contacts, respectively. A metallic layer is first deposited to fill the openings 105, 104, and 106. This metallic layer may, as before, comprise several sub-layers, for example, Ti- and TiN-based adhesion layers, 10 nm thick respectively, and a tungsten W-based main layer, thick enough to fill the openings 105, 104, and 106. This tungsten W-based main layer has, for example, a thickness of approximately 700 nm. A chemical-mechanical polishing process is then performed to remove the excess metal deposited on layer 77. The interconnections 55, 65, and 35 are thus defined.

[0103] The following steps are aimed at isolating the HBT transistor from other components (not shown).

[0104] As illustrated in [Fig. 29], a SiN-based layer 78 can be formed by deposition at 400°C on layer 77 and on the interconnects 55, 65, 35. This layer 78 typically has a thickness of approximately 150 nm. A resin-based masking layer 88 is formed on layer 78 and then structured by lithography. Trench-like openings 107 are made around the HBT transistor, typically around the collector contacts 30, first in layer 88, then in the stack of dielectric layers up to the InGaAs N+-based layer 34.

[0105] As illustrated in [Fig.30], after stripping of the masking layer 88, the engraving of the trenches 107 is extended in the stack of layers based on III-V materials, up to the SiO2-based layer 2.

[0106] As illustrated in [Fig. 31], these trenches 107 are then filled with a dielectric material 79, typically by deposition of TEOS SiO2 at 300°C to a thickness of 2 µm. A mechano-chemical polishing of the SiO2 is then carried out, stopping at the SiN-based layer 78.

[0107] The following steps aim to form the first metal level Ml comprising the metal tracks connecting the various interconnections 55, 65, 35. The interconnections 55, 65, 35 form an interconnection level II.

[0108] As illustrated in [Fig. 32], a resin-based masking layer 89 is formed on layer 78 and structured, typically by e-beam electron lithography. Openings 108 are made above the interconnections 55, 65, 35, first in layer 89, then in layer 78 up to the interconnections 55, 65, 35.

[0109] As illustrated in [Fig. 33], after stripping the masking layer 89, a metallic layer 14 is deposited so as to connect the interconnections 55, 65, 35. This metallic layer 14 may comprise several sub-layers, for example, Ti- and TiN-based tack layers, 10 nm thick respectively, and an AlCu alloy-based main layer, 440 nm thick. for example, and surface layers based on Ti and TiN, with thicknesses of 10 nm respectively.

[0110] As illustrated in [Fig.34], this metallic layer 14 is then structured by lithography and etching so as to form a track 56 connected to via 55, a track 66 connected to via 65, and a track 36 connected to via 35.

[0111] A high-voltage transistor (HBT) comprising 6M, 45M mesa structures formed in a stack of III-V materials on a Si substrate, embedded in SiO2, SiN dielectric materials and connected by W-based interconnects 55, 65, 35 is thus obtained. Such an HBT transistor and its first level of interconnects II, M1 are advantageously integrable into a system comprising CMOS transistors and CMOS interconnects.

[0112] Figures 35, 36 illustrate a variant of the method for making the HBT transistor, in which the base contacts are formed before the emitter contact.

[0113] As illustrated in [Fig. 35], the 6M mesa structure is formed by lithography and etching from the stacking of layers based on III-V materials. Dielectric layers 72, 73 are then formed on this 6M mesa structure and subsequently planarized. The dielectric layers 72, 73 are then opened at the edge of the 6M mesa structure, so as to expose the upper face 500 of layer 5.

[0114] As illustrated in [Fig. 36], the openings are then filled with a metallic layer. CMP polishing then removes the excess metallic layer to form the base 50 contacts. The emitter and collector contacts can then be formed as before. In this case, the top surface of the base 50 contacts lies in a plane that corresponds substantially to the top of the mesa 6M structure. Therefore, it is not necessary to thin the base 50 contacts when they are formed before the emitter contact. This saves a process step.

[0115] Figures 37, 38, 39 illustrate possibilities for integrating the HBT transistor into a system comprising CMOS transistors and CMOS interconnects.

[0116] As illustrated in [Fig. 37], an integrated circuit comprising HBT1, HBT2, HBT3 transistors based on III-V materials on a silicon-based substrate 1b, and integrated via interconnection levels II, 12 and metal levels M1, M2 in a dielectric matrix DI based on SiO2 and / or SiN, can advantageously be obtained. The last metal level M2 of this "HBT" integrated circuit can typically form a first hybrid bonding interface.

[0117] As illustrated in [Fig. 38], a “CMOS” integrated circuit comprising CMOS or BiCMOS transistor-based components, CMOS1, CMOS2... on a silicon-based substrate 1b and integrated via interconnection levels H', 12' and metallic levels M1', M2' in a dielectric matrix D2 based on SiO2 and / or SiN, can be advantageously assembled to the "HBT" integrated circuit. The last metallic layer M2' of the "CMOS" integrated circuit can typically form a second hybrid bonding interface.

[0118] HBT and CMOS integrated circuits can be aligned and assembled by hybrid bonding by aligning the first and second hybrid bonding interfaces. In the case of HBT integrated circuits with small lateral dimensions compared to the CMOS integrated circuit, several HBT integrated circuits can be co-assembled side-by-side on the CMOS integrated circuit. After assembly, the substrate 1b can typically be removed by mechanical trimming and wet etching.

[0119] As illustrated in [Fig. 39], levels II”, 12” and levels Metallic layers M1”, M2”, in a SiO2 and / or SiN-based dielectric matrix D3, can be advantageously formed over HBT1, HBT2, HBT3 transistors based on III-V materials. The interconnection layer II” advantageously connects the HBT1, HBT2, HBT3 transistors, typically at the collector or sub-collector portion of the HBT1, HBT2, HBT3 transistors. Some interconnections 37 of layer II” can be relatively wider and more substantial to form a heat sink for the corresponding HBT3 transistor. This improves the heat dissipation and heat management of such an HBT3 transistor. The metallic layers M1”, M2”, can typically include thick metal traces, forming passive RF components such as antennas or transmission lines.

[0120] Advantageously, the HBT level can be integrated between different interconnection levels, for example between interconnection levels II, II” as illustrated, or between interconnection levels II”, 12”, etc. This allows for greater versatility in integrating HBT transistors within the CMOS stack. Several CMOS metal levels M1', M2', for example up to five levels, can be provided below the HBT level. Several post-processing metal levels M1”, M2”, for example up to five additional levels, can be provided above the HBT level.

[0121] In view of the foregoing, it is clear that the HBT transistor and its integration system can be integrated in a compact and versatile manner within a CMOS integrated circuit. The invention is not limited to the embodiments described above.

Claims

Claims

1. A heterojunction bipolar transistor (HBT) comprising, in a stack along a z direction on a silicon-based substrate (1, 1b): - a first layer (3) made of a first III-V material having a first type of conductivity with a first level of N+ doping, - a first mesa structure (45M) on the first layer (3), comprising: • a layer (4) called a collector, based on a second III-V material having the first type of conductivity with a second level of N doping, and • a so-called base layer (5), based on a third III-V material having a second type of conductivity with a first doping level P+, - a second mesa structure (6M) on the first mesa structure (45M), comprising an emitter layer (6) based on a fourth III-V material having the first type of conductivity with a third doping level N, said transistor (HBT) further comprising a collector contact (30) on the first layer (3), preferably at the edge of the first mesa structure (45M), a base contact (50) on the base layer (5), at the edge of the second mesa structure (6M), an emitter contact (60) on the emitter layer (6), said collector, base and emitter contacts being based on an electrically conductive material suitable for metallurgy of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors, said transistor (HBT) further comprising an encapsulation layer based on a dielectric encapsulation material, said encapsulation layer covering the first layer (3), the first and second mesa structures (45M, 6M), and the collector, base and emitter contacts (30, 50, 60),said encapsulation layer being based on a dielectric material suitable for insulating the metal levels of an integrated circuit based on complementary transistors, metal-oxide-semiconductor (CMOS) components.

2. Transistor according to the preceding claim in which the dielectric material is taken from SiO2, SiN, SiOC, HfO2, A12O3 and the conductive material is taken from W, Ti, TiN, Cu Ni, NiSi, NiPt, Mo, Al.

3. A transistor according to any preceding claim wherein the first and fourth III-V materials are InP-based, and the second and third III-V materials are InGaAs-based.

4. A transistor according to any preceding claim wherein the base contact (50) has a central portion (50c) and a peripheral portion (50p) around the central portion (50c) such that the peripheral portion (50p) has a thickness less than that of the central portion (50c) and which decreases away from the central portion (50c), so as to reduce a parasitic capacitance between the base contact (50) and the emitter contact (60).

5. A transistor according to any preceding claim wherein the collector contact (30) has a central portion and a peripheral portion around the central portion such that the peripheral portion has a thickness less than that of the central portion and which decreases away from the central portion, so as to reduce a parasitic capacitance between the collector contact (30) and the base contact (50) and / or the emitter contact (60).

6. A method for producing a heterojunction bipolar transistor (HBT) comprising at least the following steps: - A supply of a stack comprising, in a z direction, a silicon-based substrate (1), a first layer (3) made of a first III-V material having a first conductivity type with a first doping level N+, - a formation by epitaxy on the first layer of a layer (4) called the collector layer, based on a second III-V material having the first conductivity type with a second doping level N, and - a formation by epitaxy on the collector layer (4) of a layer (5) called the base layer, based on a third III-V material having a second conductivity type with a first doping level P+, - a formation by epitaxy on the base layer (5) of a layer (6) called the emitter layer, based on a fourth III-V material V having the first conductivity type with a third doping level N, - A first mesa-shaped structuring of the collector and base layers (4, 5), configured to form a first mesa structure (45M) having a dimension L1 in a y direction perpendicular to the z direction, - A second mesa-shaped structuring of the emitter layer (6), configured to form a second mesa structure (6M) having a dimension L2 smaller than the dimension L1 in the y direction, - A formation of a collector contact (30) on the first layer (3), preferably at the edge of the first mesa structure (45M), - A formation of a base contact (50) on the base layer (5), at the edge of the second mesa structure (6M), - A formation of an emitter contact (60) on the emitter layer (6), said collector contacts,base and emitter contacts being formed from an electrically conductive material suitable for metallurgy of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors, - A formation of at least one encapsulation layer covering the first layer (3), the first and second mesa structures (45M, 6M), the collector, base and emitter contacts (30, 50, 60), said encapsulation layer being formed from a dielectric material suitable for isolation of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors.,

7. Method according to the preceding claim in which the formations of the first and second mesa structures (45M, 6M) are carried out respectively by a first etching along z of the collector and base layers (4, 5), and by a second etching along z of the emitter layer (6).

8. Method according to the preceding claim in which the first and second etchings each comprise an isotropic etching step. wet method, so that the first and second mesa structures (45M, 6M) each have inclined sides (451, 601), overhanging respectively the first layer (3) and the base layer (5).

9. A method according to any one of claims 6 to 8 wherein the following steps are performed in the following chronological order: forming the emitter contact (60), then forming the second mesa structure (6M), then forming the base contact (50), then forming the first mesa structure (45M), then forming the collector contact (30).

10. A method according to any one of claims 6 to 8 wherein the following steps are performed in the following chronological order: forming the second mesa structure (6M), then forming the base contact (50), then forming the emitter contact (60), then forming the first mesa structure (45M), then forming the collector contact (30).

11. A method according to any one of claims 6 to 10 wherein the formation of the collector contact (30) and / or the formation of the base contact (50) comprises a first nitrogen plasma-assisted deposition of tungsten, intended to form a peripheral portion of the collector contact and / or the base contact respectively, said formation further comprising a thinning of the peripheral portion of the contact in question by preferential etching of the peripheral portion of the contact in question with respect to a central portion of said contact.

12. System for integrating at least one heterojunction bipolar transistor (HBT) comprising, stacked in a z direction: - A first silicon-based substrate (la), - A layer (CMOS) comprising complementary CMOS metal-oxide-semiconductor transistors and first levels of metal interconnections (II', Ml') connected to said CMOS transistors, - A bonding layer comprising an interface (M2, M2') of hybrid bonding type, comprising electrical connections (12') with the first levels of metal interconnections (II', Ml') connected to the CMOS transistors, - A layer (HBT) comprising at least one heterojunction bipolar transistor according to any one of the claims dications 1 to 5, and second levels of metallic interconnections (II, Ml) interposed between the bonding layer and the layer (HBT) comprising the at least one heterojunction bipolar transistor, said second levels of metallic interconnections (II, Ml) being electrically connected to the bonding layer and to the at least one heterojunction bipolar transistor.

13. Integration system according to the preceding claim further comprising, on the layer (HBT) comprising the at least one heterojunction bipolar transistor, at least one third level of interconnections (II”, Ml”) comprising a layer (Ml”) of so-called thick metal having a thickness at least twice greater than the different thicknesses of metal (Ml, Ml') of the first and second levels of metal interconnections located under the layer (HBT) comprising the at least one heterojunction bipolar transistor.

14. Integration system according to the preceding claim wherein the layer (Ml”) of thick metal is connected to the first layer (3) of a first III-V material of the heterojunction bipolar transistor by an electrical connection (37) for heat dissipation, said electrical connection (37) for heat dissipation acting as a collector contact for the heterojunction bipolar transistor.

15. Integration system according to any one of claims 12 to 14 in which the first layer (3) made of a first III-V material of the layer comprising the at least one heterojunction bipolar transistor is continuous and completely covers, in projection along the z direction, the first silicon-based substrate (la).

16. Integration system according to any one of claims 12 to 15 in which the first levels of metal interconnections (II', Ml') connected to the CMOS transistors comprise between three and five layers (Ml', M2') of metal.

17. Method for integrating at least one heterojunction bipolar transistor comprising the following steps: - A provision of a first stack comprising in a direction z: • a first substrate (la) based on silicon, • a layer (CMOS) comprising transistors complementary metal-oxide-semiconductor CMOS and first levels of metal interconnections (II', Ml') connected to said CMOS transistors, • a first part (M2') of a bonding layer comprising a hybrid bonding type interface, comprising electrical connections (12') with the first levels of metal interconnections (II', Ml') connected to the CMOS transistors, A supply of a second stack comprising in a z direction: • a second substrate (1b) based on silicon, • a layer (HBT) comprising at least one heterojunction bipolar transistor according to any one of claims 1 to 5, and second levels of metallic interconnections (II, Ml) connected to said heterojunction bipolar transistor, • a second part (M2) of a bonding layer comprising a hybrid bonding type interface, comprising electrical connections (12) with said second levels of metal interconnections (II, Ml) connected to the heterojunction bipolar transistor, a hybrid bonding of the second part (M2) of the bonding layer onto the first part (M2') of the bonding layer, a removal of the second silicon-based substrate (1b), a formation, on the layer (HBT) comprising the at least one heterojunction bipolar transistor, of at least one third level of interconnections (II”, Ml”), said at least one third level of interconnections (II”, Ml”) preferably comprising a layer (Ml”) of so-called thick metal having a thickness at least twice greater than the different metal thicknesses (Ml, Ml') of the first and second levels of metal interconnections located (II, Ml, II', Ml') under the layer (HBT) comprising the at least one heterojunction bipolar transistor.

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