PROGRAMMABLE VOLTAGE-TIME CONVERTER

Abstract

Programmable Voltage-to-Time Converter The invention relates to a programmable voltage-to-time converter (10), comprising: - a latching frequency generator (12) configured to generate a latching frequency; - a current generator (14) configured to generate a biasing current; - a relaxation oscillator (18) configured to be powered by the biasing current and to generate an output voltage signal from the latching frequency, a gain control word, and an input voltage signal; - a phase shifter (20) configured to determine a phase shift between a first signal corresponding to the output voltage signal and a second signal determined based on the latching frequency. The relaxation oscillator (18) includes a component having a linearly controllable characteristic.The voltage-time converter (10) has a linearly or dB-linear controllable gain based on the gain control word by linear control of said characteristic of said component. Figure 1.

Description

Title of the invention: PROGRAMMABLE VOLTAGE-TIME CONVERTER FIELD OF THE INVENTION

[0001] The invention relates to a programmable voltage-to-time converter, also called VTC. The voltage-to-time converter according to the invention has a programmable gain and / or signal bandwidth.

[0002] CONTEXT OF THE INVENTION

[0003] The current trend in smart, battery-powered wearable devices requires sensors with many low-power integrated circuits such as, an amplifier, an analog-to-digital converter (ADC), and a classifier to provide intelligent data collection. Designers are considering a digital-oriented design of these systems to accommodate technology scaling trends, and a lower supply voltage for power reduction.

[0004] For these reasons, highly efficient analog-to-information architectures are beginning to process the signal in the time domain by duty cycling the analog quantity using a voltage-to-time converter (VTC) block. This time-coded signal is not limited by voltage margin, and is considerably more robust than the analog signal during process, power supply, and temperature variations. It also benefits from higher frequency resolution given the scaling of the technology.

[0005] However, highly efficient conversion requires real-time signal conditioning to handle a wide range of signal strengths. However, VTC architectures have low conversion gain and are typically preceded by a preamplifier stage or automatic gain control for signal conditioning.

[0006] Therefore, there is an interest in providing a voltage-to-time converter (VTC) with an adjustable gain.

[0007] In the art, existing VTC topologies are mainly divided into two categories: variable slope (VS) VTCs and constant slope (CS) VTCs.

[0008] As with variable slope VTCs, some such architectures may provide gain control but with only one degree of freedom that could be used. In other such architectures, the gain may be more easily adjusted via the injection current. However, the output excursion of this architecture is highly distorted around the [0, ir] limits.

[0009] As for the constant slope VTC, as in the previous case, some such architectures may provide a single degree of freedom for gain control which may be difficult to adjust. Some other architectures provide more degrees of freedom for gain control but their adjustment may be difficult to perform in practice. Summary of the invention

[0010] An objective of the present invention is to provide a programmable voltage-time converter with an adjustable gain, which is capable of solving the disadvantages of the art mentioned above.

[0011] For this purpose, the invention relates to a programmable voltage-time converter, comprising a lock frequency generator configured to generate a lock frequency, a current generator configured to generate a bias current, a relaxation oscillator configured to be powered by the bias current and to generate an output voltage signal from the lock frequency, a gain control word and an input voltage signal, a phase shift block configured to determine a phase shift between a first signal corresponding to the output voltage signal and a second signal determined on the basis of the lock frequency,the relaxation oscillator comprising a component having a linearly controllable characteristic and the voltage-to-time converter having a linearly or dB-linearly controllable gain based on the gain control word by linearly controlling said characteristic of said component.

[0012] Alternatively, the programmable voltage-to-time converter includes a phase shift block configured to determine at least one phase based on the difference between the output voltage signal output from the relaxation oscillator and the lock frequency.

[0013] With these features, the invention ensures precise and easy gain control of the voltage-to-time converter, without a preamplifier stage (e.g., comprising an LNA "low noise amplifier") or automatic gain control for signal conditioning. Therefore, the VTC according to the invention is more compact and free from the disadvantages of the preamplifier stage or other additional components. This is achieved by means of a relaxation oscillator having a capacitive injection locked oscillator structure, called C-ILO. This relaxation oscillator is provided with a component having a linearly controllable characteristic. Therefore, the gain of the overall system can be finely controlled by controlling this characteristic with an adjustable range and step size. The range and step can be easily adapted to each application.

[0014] Compared to the conventional architecture, the VTC according to the invention can amplify and convert the input voltage in one step, resulting in reduced complexity and power consumption.

[0015] The present invention can operate precisely using a supply voltage of only a few hundred millivolts while maintaining low distortion and rail-to-rail conversion. In addition, it is compatible with single-ended or differential input.

[0016] The proposed VTC can be interfaced with all types of sensors, especially analog-to-information architecture which generally requires high SNR ("signal to noise ratio") for better efficiency. It can advantageously be used for low power applications such as biomedical applications, loT ("Internet of Things"), wake-up sensors, and low power and low distortion based ADC.

[0017] Furthermore, the invention eliminates the need for large passive components (such as capacitors, for example) for low-pass filtering since the bandwidth is a function of the ratio of the load and injection capacitances. This ratio can be chosen accordingly.

[0018] According to certain embodiments, said component is an input inverter block controlled at least partially by the input voltage signal and connected to an output of the relaxation oscillator; the input inverter block having a gain linearly controllable on the basis of the gain control word; said characteristic corresponding to the gain of the input inverter block.

[0019] According to certain embodiments, the input inverter block comprises M inverters connected in parallel and first selection means configured to control the gain of the input inverter block by selecting from among these M inverters m inverters to be controlled by the input voltage signal and at least Mm-1 inverters to be controlled by a voltage signal different from the input voltage signal, the number m being defined on the basis of the gain control word.

[0020] According to certain embodiments, the input inverter block further comprises K additional inverters configured to be controlled by the input voltage signal, K being a constant factor; the first selection means being configured to control the gain of the input inverter block by selecting from among M+K inverters m inverters to be controlled by the input voltage signal and Mm inverters to be controlled by said voltage signal different from the input voltage signal.

[0021] According to certain embodiments, said component is a charging capacitor block having a linearly controllable capacitance based on the gain control word; said characteristic corresponding to the capacitance of the charging capacitor block.

[0022] According to some embodiments, the relaxation oscillator further comprises a switched injection branch configured to inject a voltage defined by the lock frequency and comprising a capacitor block defining an injection capacitance.

[0023] According to certain embodiments, the injection capacitance is chosen so as to be constant for linear control of the gain of the voltage-time converter.

[0024] According to certain embodiments, the capacitor block comprises second selection means configured to control the injection capacitance in a manner complementary to said characteristic of said component, for dB-linear control of the gain of the voltage-time converter.

[0025] According to certain embodiments, the second selection means are configured to control the injection capacity in a linear manner, based on the gain control word.

[0026] According to some embodiments, the current generator is configured to generate the bias current based on a bandwidth control word, for linear control of the bandwidth of the voltage-to-time converter.

[0027] According to some embodiments, the current generator includes a control block configured to linearly control the bias current based on the bandwidth control word.

[0028] According to certain embodiments, the current generator further comprises a compensation block connected to an input of the control block and configured to generate, on the basis of the gain control word, a current compensating for variations in the injection capacitance.

[0029] According to certain embodiments, the lock frequency generator is formed from one of the following elements:

[0030] - a normal clock to provide a constant locking frequency;

[0031] - an adaptive clock for providing an adaptive locking frequency;

[0032] - a non-controlled relaxation oscillator powered by the bias current and comprising a load capacitor defining a capacitance adapted to provide an adaptive lock frequency.

[0033] According to some embodiments, the frequency lock generator is formed from the relaxation oscillator and an additional relaxation oscillator connected to said relaxation oscillator to form a self-oscillating system.

[0034] According to some embodiments, the input voltage signal is a differential voltage signal having two components, the programmable voltage-to-time converter comprising a relaxation oscillator for each component of the input voltage signal.

[0035] According to some embodiments, the first and second signals for the block of phase shift correspond to output voltage signals emitted from different relaxation oscillators.

[0036] According to some embodiments, the second signal for the phase shift block is provided by the lock frequency. Brief description of the drawings

[0037] The invention and its advantages will appear more clearly on reading the description given below, which is presented solely by way of non-limiting example and which is given with reference to the appended drawings, in which:

[0038] - [Fig.l] [Fig.l] is a schematic view of a voltage-time converter according to a first embodiment of the invention;

[0039] - [Fig.2][Fig.3][Fig.4][Fig.5][Fig.6][Fig.7][Fig.8] Figures 2 to 8 represent particular examples of implementation of different components of the voltage-time converter of [Fig.l];

[0040] - [Fig.9] [Fig.9] is a schematic view of a voltage-time converter according to a second embodiment of the invention;

[0041] - [Fig. 10] [Fig. 10] represents the operation of a component of the converter voltage-time of [Fig.9];

[0042] - [Fig. 11] [Fig. 11] is a schematic view of a voltage-time converter according to a third embodiment of the invention;

[0043] - [Fig. 12] [Fig. 12] is a schematic view of a voltage-time converter according to a fourth embodiment of the invention; and

[0044] - [Fig. 13] [Fig. 13] is a schematic view of a component of a converter voltage-time according to a fifth embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0045] FIRST EMBODIMENT

[0046] [Fig.l] represents a programmable voltage-time converter 10, also called VTC 10, according to a first embodiment of the invention.

[0047] The VTC 10 is, for example, usable in an analog-to-digital converter (ADC) and is capable of providing a phase or delay or time value from an input voltage signal. The input voltage signal corresponds, for example, to a measurement signal. Therefore, for example, the VTC 10 can be used as a component of a sensor system providing digital values ​​of a measured physical parameter. The VTC 10 provides a phase gain normalized by a probe frequency of g / V.

[0048] The VTC 10 has an adjustable gain and a signal bandwidth depending on the given gain. The gain control is performed by means of a gain control word m and the bandwidth control is performed by means of a band control word bandwidth h. In other words, m and h present control commands usable for adjusting the gain and signal bandwidth of the VTC 10 respectively. As will be apparent from the description given below, the gain control and the signal bandwidth control of the VTC 10 are independent of each other.

[0049] Additionally, the VTC 10 may be controlled linearly to moderate input signal excursion (e.g., less than 10 dB) and linearly in decibels (a method called dB-linear) for large input signal excursion (e.g., greater than 20 dB). Each type of these controls is described in more detail below.

[0050] As described in FIG. 1, the VTC 10 comprises a lock frequency generator 12 configured to generate a lock frequency f lk, a current generator 14 configured to generate a bias current 1$, and a relaxation oscillator 18 configured to be powered by the bias current Ip and to generate an output voltage signal Vout in particular from the lock frequency / and the input voltage signal V

[0051] The VTC 10 further comprises a phase shift block 20 configured to determine a phase shift between a first signal corresponding to the output voltage signal Vm{t and a second signal corresponding in this embodiment to the locking frequency f This phase shift block 20 can be implemented in the form of a simple circuit implementing XOR logic between two signals.

[0052] The relaxation oscillator 18 is based on a capacitive injection locked oscillator structure, called C-ILO. This structure has a high excursion capacity, good stability against process and temperature variations, and reduced space consumption compared to an analog implementation. It is described in more detail with reference to [Fig.2].

[0053] Therefore, as described in Figure 2, the relaxation oscillator 18 comprises two symmetrical parts 25-1, 25-2 powered by the bias current and an RS flip-flop 26 (reset-set flip-flop) connected between the parts 25-1, 25-2. Each part 25-1, 25-2 comprises an input inverter block 27 controlled by the input voltage signal V^, a load capacitor and a switched injection branch 28 with a capacitor block 29 having an injection capacitance C2. Each inverter block 27 is connected between the corresponding switched injection branch 28 and the load capacitor on the one hand and the RS flip-flop 26 on the other hand. In addition, each inverter block 27 is at least partially controlled by the input voltage signal Vvj? and has a programmable gain G}NV(m) based on the gain control word m, as described below in more detail. Each load capacitor C1 is connected between the switched injection branch 28 cor corresponding and the inverter block 27. The output voltage signal Vmtt is output from one of the parts 25-1, 25-2 (part 25-1 in the example of [Fig.2]).

[0054] The lock frequency generator 12 is configured to generate the lock frequency f lk such that the equilibrium phase shift of the VTC 10 in the absence of an input signal is equal to 7F / 2. In this way, the VTC 10 has a completely symmetrical output excursion of ± 7T [2. In fact, the output excursion in terms of the modulated natural frequency y ^y . ) is given by: ^¢ = 0 = ^-77 / 2 / 7“ = fd 1 + ) ¢ = 77 = 0., + æ / 2 'f 0 cik \ CL / * T 0 /

[0055] where , / 0 is a natural frequency of the global VTC 10, i.e. a frequency in the absence of the input voltage signal Vsig-

[0056] Advantageously, an optimal value of the locking frequency f lk is when j 2, so that it can be determined by the following expression: _ „ 0.5+Cj / Cj clk “ JQ 1+Ct / C2 ■

[0057] Different examples of implementation of the relaxation oscillator 18, the current generator 14 and the lock frequency generator 12 can be used to obtain different types of control of the VTC 10. In particular, four different types of control of the VTC 10 which can be combined with each other can be obtained:

[0058] - linear gain control;

[0059] - dB-linear gain control;

[0060] - linear bandwidth control with linear gain control; and

[0061] - linear bandwidth control with dB-linear gain control.

[0062] An example implementation for each of the types of each of the oscillator relaxation generator 18, current generator 14 and lock frequency generator 12 is described below.

[0063] LINEAR GAIN CONTROL

[0064] Relaxation oscillator 18

[0065] According to the invention, a linear control of the GVTC gain of the VTC 10 can be obtained by adjusting the gain GiNV(m) of the inverter block 27 included in the relaxation oscillator 18, in a linear manner. In particular, the following expression can be used to control the gain G1NV(m) of the inverter block 27: Gmv(m) = G^NV x ( m + 1),

[0066] where G^y is a reference gain of the inverter block 27.

[0067] A possible embodiment of the inverter block 27 with an adjustable gain G1NV(m) for linear control purposes is described in Figure 3. According to this figure, the inverter block 27 comprises M inverters 30 connected in parallel and first selection means 31. Among these M inverters 30, one inverter 30 is always controlled by the input voltage signal Vsi? and M1 inverters 30 can be controlled either by the input voltage VSjg or by a voltage Vo different from the voltage Vsig. The voltage Vo is the voltage of the VTC 10 in the absence of the input voltage signal. In other words, Vo is a bias voltage of the inverter block 27.

[0068] In particular, the selection means 31 representing for example a switch for each of M1 inverters 30 are capable of selecting for each of said inverters 30 the voltage or the voltage Vo, as described in [Fig.3].

[0069] Assuming that all of the inverters 30 are substantially identical and designating by G^v 'c 8a'n the maximum that the inverter block 27 is capable of providing, the gain G1NV(m) can be adjusted on the basis of the gain control word m in the following way: 100701

[0071] To obtain this expression, the first selection means 31 are controlled so as to control m inverters 30 under the voltage Vs7i, and Mlm inverters 30 under the voltage Vo.

[0072] The reference gain G®NV can be obtained when m = 0 by G®NV = G™^ / M-

[0073] In this example, the capacitor block 29 can consist of a single capacitor having a constant capacitance C2.

[0074] Current generator 14

[0075] According to this type of control, the current generator 14 can represent any suitable generator providing a constant bias current.

[0076] Locking Frequency Generator 12

[0077] Furthermore, according to this type of control, the locking frequency f lk is not affected by the control of the inversion gain GINV. Therefore, the locking frequency generator 12 can represent a simple clock generator capable of providing a constant locking frequency, having for example the optimal value f}k as defined above.

[0078] LINEAR GAIN CONTROL IN dB

[0079] Relaxation oscillator 18

[0080] According to the invention, a dB-linear control of the GVTC gain of the VTC 10 can be obtained by complementary control of the gain Gf^y^m) of the inverter block 27 and the injection capacity defined by the capacitor block 29. In particular, in this case, the Gvtc gain can be controlled based on the gain control word m according to the following expression:

[0081] x, i G™v(m+K)

[0082] where:

[0083] G®nv is a reference gain of the inverter block 27;

[0084] is the inversion level of the inverter block 27 at the common mode voltage input Vq;

[0085] Cj is a reference capacitance of the capacitor block 29;

[0086] K is a constant factor responsible for defining the adjustment range and the control step.

[0087] In other words, as in the previous case, the inverter gain GINV of the inverter block 27 can still be controlled linearly but using the factor m + K instead of m+ 1, i.e. GiNV(m) = G^NV(m + K)•

[0088] A possible embodiment of the inverter block 27 with an adjustable gain GjNV(m) for dB-linear control purposes is described in Figure 4. According to this figure, the inverter block 27 comprises M+K inverters 30 connected in parallel and first selection means 31. Among these M+K inverters 30, K inverters 30 are always controlled by the input voltage signal Vsj„ and M inverters 30 can be controlled either by the input voltage or by the voltage different from the voltage V^. In particular, the selection means 31 representing, for example, a switch for each of M inverters 30 are capable of selecting for each of said inverters 30 the voltage Vsjg or the voltage Vo, as described in [Fig.4],

[0089] Assuming that all of the inverters 30 are substantially identical and designating by G^y the maximum gain that the block 27 is capable of providing, the gain can be adjusted on the basis of the gain control word m in the following way: 100901 GINV(m)=^^m + KY

[0091] To obtain this expression, the first selection means 31 are controlled so as to control m inverters 30 under the voltage Vsj„ and Mm inverters 30 under the voltage Vq.

[0092] Unlike the previous case, in this example, the reference gain G{]NV is obtained by the following expression:

[0093] rfxv = C^vl(M + K\

[0094] As mentioned above, the capacitor block 29 is adjusted in a complementary manner mentary to obtain the dB-linear control of the gain GVTC(m) ■ In other words, the capacitance C2 is linearly controlled according to the following expression:

[0095] C2 ^d^ Mm + K').

[0096] For this purpose, a possible embodiment of the capacitor block 29 is described in Figure 5. According to this embodiment, the capacitor block 29 comprises a plurality of capacitors 40 connected in parallel and second selection means 42. Among the capacitors 40, one or a plurality of capacitors having their total capacity equal to are always controlled by the voltage Vcik. Each of the other capacitors 40 is either connected or disconnected from the circuit by the second selection means 42 to ensure their total capacity equal to C?( M - m ).

[0097] Current generator 14

[0098] According to this type of control, the current generator 14 can represent any suitable generator providing a constant bias current I b.

[0099] Locking Frequency Generator 12

[0100] In the case of dB-linear gain control, the injection capacitance C2 is adjusted to lead to a variation of the required optimal value of f lk. In this case, an adaptive lock frequency generator 12 providing a variable lock frequency f as a function of the injection capacitance C2 can be used.

[0101] LINEAR BANDWIDTH CONTROL WITH LINEAR GAIN CONTROL

[0102] Relaxation oscillator 18

[0103] The architecture of the relaxation oscillator 18 is not affected by linear bandwidth control. Therefore, any of the previously described may be used for the relaxation oscillator 18 based on the desired gain control.

[0104] Current generator 14

[0105] For linear bandwidth control, the bias current 1 b emitted from the current generator 14 is linearly controlled by means of the bandwidth control word h. In particular, in this case, the bandwidth f BW of the VTC 10 is expressed as follows:

[0106] £ / i \ 1 / 2.7T jJlÀ

[0107] Assuming that the bias current / g is linearly controlled so that:

[0108] lB(h) = ^x( / z+l)

[0109] where is a reference current value, it is possible to linearly control the bandwidth f. For this purpose, the current generator 14 comprises a block control 49 guaranteeing this type of polarization current control

[0110] A possible embodiment of the control block 49 is described in Figure 6. According to this embodiment, the control block 49 comprises a current source 50 providing the reference current, a plurality of transistors 51 connected in series to multiply the reference current and third selection means 53 configured to connect / disconnect the transistors 51 so as to deliver the resulting current. For this purpose, the third selection means 53 may comprise a switch associated with each transistor 51. To obtain the resulting current (h + 1), the third selection means 53 are capable of connect to circuit h + 1 transistors 51.

[0111] Locking Frequency Generator 12

[0112] In the case of linear bandwidth control via the bias current / g, the required value of f lk is affected by the natural frequency / 0 « IB . In this case, an adaptive lock frequency generator 12 providing a variable lock frequency / Jk as a function of the natural frequency / 0 may be used. Alternatively, the lock frequency generator 12 may comprise a non-locked relaxation oscillator 58 having the same bias current 1B as the relaxation oscillator 18.

[0113] An example of such a relaxation oscillator 58 is depicted in Figure 8. This oscillator is similar to the one depicted in Figure 2 but unlike the latter, is not provided with the injection branches 28. In addition, the load capacitors Cclk of the relaxation oscillator 58 are adapted to deliver the locking frequency f lk to the output defined by its optimal value as described above. For this purpose, the capacitance of each load capacitor Cclk can be defined as follows:

[0114] r _r l+clc2 ^lo.S+q / c /

[0115] LINEAR BANDWIDTH CONTROL WITH LINEAR dB GAIN CONTROL

[0116] Relaxation oscillator 18

[0117] The architecture of the relaxation oscillator 18 is not affected in this case. Therefore, any of the previously described architectures can be used for the relaxation oscillator 18 based on the desired gain control.

[0118] Current generator 14

[0119] As described above, the bandwidth of VTC 10 is a function of the injection capacitance C2. Therefore, its value is likely to change when the gain is adjusted using ( m) where m = M - m + K. To compensate for this variation, an adaptive current bias, namely, IBÇ 1 / m), is used.

[0120] For this purpose, in the case of linear bandwidth control with dB-linear gain control, the current generator 14 further comprises a compensation block 59 connected to the input of the control block 49 as previously described. In other words, in the example of Figure 6, the output of the compensation block 59 is connected as current source 50 of the control block 49. The compensation block 59 operates on the basis of the gain control word m, as described in [Fig. 1]. In the case of linear bandwidth control for linear gain control, the compensation block 59 can be disabled or the current generator 14 can be provided without this compensation block 59.

[0121] A possible embodiment of the compensation block 59 is depicted in Figure 7. According to this embodiment, the compensation block 59 comprises a current source 60 providing the reference current J®, a plurality of transistors 61 connected to the current source 60 in a mutually parallel manner, fourth selection means 64 configured to connect / disconnect the transistors and an output branch 65. Among the transistors, K transistors are permanently connected to the circuit and the fourth selection means 64 are capable of connecting Mm transistors, to divide the reference current J® by the factor m = M - m 4- K. The output branch 65 further comprises K transistors permanently connected to multiply the current divided by K, the resulting current being defined according to the following expression:

[0122] T _ / B~ M-m+K'

[0123] Alternatively, instead of K permanently connected transistors, a single transistor of size K may be used. In this case, the current required to maintain the required bandwidth at maximum gain (m=M) is equal to which can be easily defined by the designer.

[0124] Locking Frequency Generator 12

[0125] As in the case of dB-linear gain control, in the present example, the injection capacitance C2 is adjusted so as to lead to a variation of the required optimal value of f lk. In this case, an adaptive lock frequency generator 12 providing a variable lock frequency f as a function of the injection capacitance C2 and the bias current Ig can be used.

[0126] SECOND EMBODIMENT

[0127] A VTC 110 according to a second embodiment is schematically described in [Fig.9]. The VTC 110 according to this embodiment is similar to that of the first embodiment, described with reference to [Fig.l]. In particular, this VTC 110 comprises a current generator 14, a relaxation oscillator 18 and a phase shift block 20 which are similar to those described above are not described in reference to this embodiment.

[0128] The VTC 110 according to the second embodiment further comprises a lock frequency generator 112 having a structure different from that described above.

[0129] In particular, according to this embodiment, the lock frequency generator 112 is formed by a pair of self-locking injection oscillators. One of these oscillators is the relaxation oscillator 18 as previously described. The other oscillator, designated in [Fig.9] by the reference 119, is similar to the relaxation oscillator 18. However, the output of this oscillator 119 is connected to the input of the oscillator 18 and the output of the oscillator 18 is connected to the input of the oscillator 119.

[0130] Assuming that the two oscillators 18, 119 are connected in series and both operate at the frequency f Jk, consequently, each of them creates a phase shift of 77 / 2 between its input and output, with a total phase shift of 77. According to this hypothesis, the system formed by these oscillators 18, 119 can self-oscillate by compensating for the total phase shift 77 and closing the loop, providing the optimal value of the locking frequency f lk as previously described. This principle is schematically described in [Fig. 10].

[0131] The lock frequency generator 112 is particularly advantageous when precise control of the lock frequency f is required and / or its control is not simple. This is particularly the case for dB-linear gain control. It should be noted that according to this embodiment, no adaptive clock is necessary since the system formed by the oscillators 18, 119 is self-oscillating.

[0132] THIRD EMBODIMENT

[0133] A VTC 210 according to a third embodiment is schematically described in [Fig. 11]. The VTC 210 according to this embodiment is similar to the VTC 10 according to the first embodiment, described with reference to [Fig.l]. In particular, this VTC 210 comprises a current generator 14, a lock frequency generator 12 and a phase shift block 20 which are similar to those described above and are not described with reference to this embodiment.

[0134] Unlike the first embodiment, the input voltage signal Vsis of the VTC 210 according to the third embodiment has a differential signal defining a component and a component In this embodiment, the VTC 210 comprises a relaxation oscillator 218, 219 for each component of the differential signal As described in [Fig. 11], the relaxation oscillators 218, 219 are connected in parallel between the lock frequency generator 12 and the phase shift block 20.

[0135] In particular, each relaxation oscillator 218, 219 is similar to the relaxation oscillator 18 described with reference to the first embodiment and is configured to output an output voltage signal from the corresponding component of the differential input signal VŸJ? and the same locking frequency f lk provided by the locking frequency generator 12. The phase shift block 20 is configured to determine a phase shift 0 between a first signal corresponding to the output voltage signal of the relaxation oscillator 218 and a second signal corresponding in this embodiment to the output voltage signal of the relaxation oscillator 219. As described in FIG. 11, the phase shift block 20 is configured to apply XOR logic between the received signals.The application of XOR logic in this case is equivalent to a sum of two phases, each phase corresponding to the result of a subtraction for each relaxation oscillator between its output voltage signal and the locking frequency f lk. In other words, the application of XOR logic includes a determination of a phase based on the difference between the output voltage signal of at least one relaxation oscillator and the locking frequency f lk.

[0136] The lock frequency generator 12 may be embodied in accordance with any of the preceding examples. In the example of [Fig. 11], the lock frequency generator 12 has a non-locked relaxation oscillator similar to that described with reference to [Fig. 8]. Therefore, in this example, the VTC 210 is particularly suitable for linear control of the gain and / or bandwidth.

[0137] FOURTH EMBODIMENT

[0138] A VTC 310 according to a fourth embodiment is schematically depicted in Figure 12. The VTC 310 according to this embodiment is similar to the VTC 110 according to the second embodiment (described with reference to Figure 9) but is adapted to operate with a differential input signal as described with reference to the previous embodiment.

[0139] In particular, this VTC 310 comprises a locking frequency generator 312 which is formed by a pair of self-locking injection oscillators 318, 319. These oscillators 318, 319 are similar to the oscillators 218, 219 described with reference to the previous embodiment. In particular, each of these oscillators 318, 319 is controlled by the respective component Vsig+, Vs[g- of the differential input signal. In addition, the output of oscillator 319 providing the locking frequency f lk as described above is connected to the input of oscillator 318 and to the phase shift block 20. The output of oscillator 318 is connected to the input of oscillator 319 and to the phase shift block 20. The phase shift block 20 is configured to determine a phase shift 0 between a first signal corresponding to the output voltage signal of the oscillator relaxation oscillator 318 and a second signal corresponding to the locking frequency f emitted by the relaxation oscillator 319. As described in [Fig. 11], the phase shift block 20 is configured to apply XOR logic between the received signals.

[0140] According to this embodiment, the VTC 310 can be used to control the bandwidth linearly and the gain linearly or dB-linearly.

[0141] FIFTH EMBODIMENT

[0142] The structure of a VTC according to a fifth embodiment may be similar to any of those described with reference to the previous embodiments. The only difference of the VTC according to this embodiment is the structure of a relaxation oscillator 418 which is described below in more detail with reference to [Fig.13].

[0143] As in the previous embodiments, the relaxation oscillator 418 is based on a capacitive injection locked oscillator structure, called C-ILO. Furthermore, as in the previous embodiments, the oscillator 418 comprises two symmetrical parts 425-1, 425-2 powered by the bias current / g and an RS flip-flop 26 (“reset-set” flip-flop) connected between the parts 425-1, 425-2. Also as in the previous cases, each part 425-1, 425-2 comprises a switched injection branch 28 comprising a capacitor block 29 having an injection capacitance C2 which can be finally controlled by means of the gain control word m as previously described.

[0144] Unlike the previously described examples, instead of an input inverter block, each part 425-1, 425-2 of the relaxation oscillator 418 comprises a comparator 426 connected to the input voltage signal VsiQ via a DC decoupling unit. The reference inversion level can in this case be defined directly by decoupling the input of the comparator 426 from the signal of interest. This decoupling further contributes to reducing the input offset.

[0145] In this case, the inversion gain GINV as previously explained is substantially equal to 1 and the gain of the overall VTC can be obtained by means of the following expression:

[0146] GvTC(m}x^

[0147] Therefore, linear gain control can be achieved by adjusting the capacitance while dB-linear gain control can be achieved by timing Ci and C2 in a complementary manner.

[0148] For this purpose, instead of a simple charging capacitor as previously described, each part 425-1, 425-2 of the relaxation oscillator 418 comprises a charging capacitor block 427 having a linearly controllable capacitance C} on the basis of the gain control word m. This control can be carried out by means of a structure similar to that described and explained with reference to Figure As5. In particular, as in the case of [Fig.5], the charging capacitor block 427 may comprise a plurality of capacitors configured to be connected in parallel by selection means in order to linearly control the resulting capacitance.

Claims

Claims

1. Programmable voltage-to-time converter (10; 110; 210; 310), comprising: - a lock frequency generator (12; 112; 312) configured to generate a lock frequency; - a current generator (14) configured to generate a bias current; - a relaxation oscillator (18; 218; 318; 418) configured to be powered by the bias current and to generate an output voltage signal from the lock frequency, a gain control word and an input voltage signal; - a phase shift block (20) configured to determine a phase shift between a first signal corresponding to the output voltage signal and a second signal determined on the basis of the lock frequency; the relaxation oscillator (18; 218; 318; 418) comprising a component (27; 427) having a linearly controllable characteristic; the voltage-time converter (10; 110; 210;310) having a linearly or dB-linearly controllable gain based on the gain control word by linearly controlling said characteristic of said component (27; 427).;

2. A programmable voltage-to-time converter (10; 110; 210; 310) according to claim 1, wherein said component is an input inverter block (27) controlled at least partially by the input voltage signal and connected to an output of the relaxation oscillator (18; 218; 318); the input inverter block (27) having a gain linearly controllable based on the gain control word; said characteristic corresponding to the gain of the input inverter block (27).

3. A programmable voltage-to-time converter (10; 110; 210; 310) according to claim 2, wherein the input inverter block (27) comprises M inverters (30) connected in parallel and first selection means (31) configured to control the gain of the input inverter block (27) by selecting from among these M inverters (30) m inverters (30) to be controlled by the input voltage signal and at least one of the input voltage signals. less Mm-1 inverters (30) to be controlled by a voltage signal different from the input voltage signal, the number m being defined on the basis of the gain control word.

4. Programmable voltage-time converter (10; 110; 210; 310) according to claim 3, wherein the input inverter block (27) further comprises K additional inverters (30) configured to be controlled by the input voltage signal, K being a constant factor; the first selection means (31) being configured to control the gain of the input inverter block (27) by selecting from among M+K inverters (30) m inverters (30) to be controlled by the input voltage signal and Mm inverters (30) to be controlled by said voltage signal different from the input voltage signal.

5. A programmable voltage-to-time converter (10; 110; 210; 310) according to claim 1, wherein said component is a load capacitor block (427) having a linearly controllable capacitance based on the gain control word; said characteristic corresponding to the capacitance of the load capacitor block (427).

6. A programmable voltage-to-time converter (10; 110; 210; 310) according to any preceding claim, wherein the relaxation oscillator (18; 218; 318; 418) further comprises a switched injection branch (28) configured to inject a voltage defined by the lock frequency and comprising a capacitor block (29) defining an injection capacitance.

7. Programmable voltage-to-time converter (10; 110; 210; 310) according to claim 6, wherein the injection capacitance is chosen to be constant for linear control of the gain of the voltage-to-time converter (10; 110; 210; 310).

8. Programmable voltage-time converter (10; 110; 210; 310) according to claim 6, wherein the capacitor block (29) comprises second selection means (42) configured to control the injection capacitance in a manner complementary to said characteristic of said component (27; 427), for dB-linear control of the gain of the voltage-time converter (10; 110; 210; 310).

9. Programmable voltage-time converter (10; 110; 210; 310) according to claim 8, wherein the second selection means (42) are configured to control the injection capacity linearly, based on the gain control word.

10. A programmable voltage-to-time converter (10; 110; 210; 310) according to any preceding claim, wherein the current generator (14) is configured to generate the bias current based on a bandwidth control word, for linear control of the bandwidth of the voltage-to-time converter (10; 110; 210; 310).

11. The programmable voltage-to-time converter (10; 110; 210; 310) of claim 10, wherein the current generator (14) comprises a control block (49) configured to linearly control the bias current based on the bandwidth control word.

12. Programmable voltage-time converter (10; 110; 210; 310) according to claim 11 in combination with claim 8 or 9, wherein the current generator (14) further comprises a compensation block (59) connected to an input of the control block (49) and configured to generate, on the basis of the gain control word, a current compensating for variations in the injection capacitance.

13. Programmable voltage-to-time converter (10; 210) according to any one of the preceding claims, wherein the lock frequency generator (12) is formed by one of the following elements: - a normal clock for providing a constant lock frequency; - an adaptive clock for providing an adaptive lock frequency; - a non-controlled relaxation oscillator (58) powered by the bias current and comprising a load capacitor defining a capacitance adapted to provide an adaptive lock frequency.

14. A programmable voltage-to-time converter (110; 310) according to any one of claims 1 to 12, wherein the lock frequency generator (12) is formed of the relaxation oscillator (18; 318; 418) and an additional relaxation oscillator (119; 319) connected to said relaxation oscillator (18; 318; 418) to form a self-oscillating system.

15. A programmable voltage-to-time converter (210; 310) according to any preceding claim, wherein the input voltage signal is a differential voltage signal having two components; the programmable voltage-to-time converter (210; 310) comprising a relaxation oscillator (218, 219; 318, 319) for each component of the input voltage signal.

16. The programmable voltage-to-time converter (210) of claim 15, wherein the first and second signals for the phase shift block (20) correspond to output voltage signals output from different relaxation oscillators.

17. A programmable voltage-to-time converter (10; 110; 310) according to any one of claims 1 to 15, wherein the second signal for the phase shift block (20) is provided by the lock frequency.

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