OxRAM-type resistive memory cell and associated manufacturing process

Abstract

The invention relates to a resistive OxRAM-type memory cell (1) comprising a first electrode (2), a second electrode (3), and an active layer (4) extending between the first electrode (2) and the second electrode (3). The active layer (4) comprises a dielectric oxide layer (12) and an active material layer (10), the dielectric oxide layer (12) being disposed on the active material layer (10). The second electrode (3) comprises a first conductive layer (20), in contact with the active layer (4) and selected to create oxygen vacancies in the active material layer (10), and a second conductive layer (22) disposed on the first conductive layer (20). The active layer (4) is partially doped with a dopant. A method for manufacturing such a memory cell (1) is also described. Figure to be published with the abstract: Fig. 1

Description

Title of the invention: OxRAM type resistive memory cell and associated manufacturing method Technical field

[0001] The present invention relates generally to the field of microelectronics. It relates more particularly to the field of non-volatile resistive memories of the filamentary type.

[0002] In particular, the present invention relates to a resistive memory cell of the OxRAM type. It also relates to a method of manufacturing such a resistive memory cell of the OxRAM type. STATE OF THE ART

[0003] Resistive memories, in particular oxide-based resistive memories (or OxRAM, for "Oxide-based Random Access Memories" according to the commonly used acronym), are non-volatile memories intended to replace Flash-type memories. In addition to a high integration density, they have a high operating speed, high endurance and good compatibility with the manufacturing processes currently used in the microelectric industry, in particular with the end-of-line (BEOL, for "Back-End Of Line" according to the commonly used acronym) process of CMOS technology (for "Complementary Metal Oxide Semi-conductor" according to the commonly used acronym).

[0004] OxRAM resistive memories comprise a multitude of memory cells, also called memory points. Each OxRAM memory cell consists of a MIM (Metal-Insulator-Metal) capacitor comprising an active material of variable electrical resistance, generally a transition metal oxide (e.g. HfO2, Ta2O 5, TiO2, etc.), arranged between two metal electrodes. The memory cell switches reversibly between two resistance states, which correspond to logic values ​​"0" and "1" used to encode a bit of information. In some cases, more than two resistance states can be generated, which makes it possible to store several bits of information in a single memory cell.

[0005] The information is written into the memory cell by switching it from a highly resistive state (or HRS, for "High Resistance State" according to the commonly used acronym of Anglo-Saxon origin), also called "OFF" state, to a weakly resistive state (or LRS, for "Low Resistance State"), or "ON" state. Conversely, to erase the information from the memory cell, it is switched from the weakly resistive state ("OFF") to the highly resistive state ("ON").

[0006] The change in resistance of the memory cell is governed by the formation and rupture of a conductive filament of nanometric section between the two electrodes. This conductive filament is created thanks to the presence of oxygen vacancies present in the active layer of the memory cell. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus modify the electrical conduction between the two electrodes. In the active layer, the electrically conductive filament is either broken, or on the contrary reformed to vary the resistance level of the memory cell, during write cycles then resetting of this cell (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations resulting in the HRS state, when the filament is broken again by respective application of a SET, VSEt or RESET, VRESEt voltage to the terminals of the electrodes).

[0007] Immediately after its manufacture, the resistive memory cell is in a virgin state characterized by a very high (so-called initial) resistance. This initial resistance is much higher than the resistance of the cell when it is in the highly resistive state. The oxide layer is in fact insulating in its initial state. In order for the memory cell to be used, it is necessary to carry out a so-called “forming” step. This step consists of a partially reversible breakdown of the oxide in order to generate the conductive filament for the first time (and therefore to place the memory cell in the low-resistive state). After this breakdown, the initially insulating oxide layer becomes active and the cell can switch between the low-resistive state and the high-resistive state by erasing and writing operations.

[0008] The forming step is accomplished by applying between the two electrodes of the memory cell a voltage (called "forming" voltage) of a value much higher than the nominal operating voltage of the memory cell (used during the following write-erase cycles), for example a voltage of the order of 2.5 V for a nominal voltage of the order of 1.5 V.

[0009] However, it is observed that the use of the MIM (Metal-Insulator-Metal) structure for each memory cell is not optimal for enabling the switching of the memory cell (between the “OFF” state and the “ON” state and vice versa).

[0010] To solve this problem, it is known, for example, from the articles “Ultra-Scaled AIOx Diffusion Barriers for Multibit HfOx RRAM Operation” by K. -M. Persson, MS Ram and L. -E. Wernersson, IEEE Journal of the Electron Devices Society, vol. 9, pp. 564-569, 2021, doi: 10.1109 / JEDS.2021.3079398 and “Ultralow sub-500nA operating current high-performance TiN\M2O3\HfO2\Hf\TiN bipolar RRAM achieved through understanding-based stack-engineering”, by L. Goux et al., 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, USA, 2012, pp. 159-160, doi: 10.1109 / VLSIT.2012.6242510, to add a layer comprising an aluminum oxide AIOx on the layer comprising the active material. This layer comprising the aluminum oxide is therefore positioned between the layer comprising the active material and the upper metal layer. This layer then acts as a diffusion barrier for oxygen vacancies (with respect to the filament) and thus improves the switching properties of the memory cell. In particular, this configuration makes it possible to improve the implementation of write and erase cycles.

[0011] However, the addition of this layer of aluminum oxide makes it more difficult to carry out the forming step because the addition of this layer leads to an increase in the forming voltage necessary to form the conductive filament. Summary of the invention

[0012] The present invention therefore aims to improve resistive memory cells of the OxRAM type, in particular by improving their switching and retention properties and their stability (in particular temporal stability and temperature stability).

[0013] The invention then relates to a resistive memory cell of the OxRAM type comprising a first electrode, a second electrode and an active layer which extends between the first electrode and the second electrode, the active layer comprising a dielectric oxide layer and an active material layer, the dielectric oxide layer being disposed on the active material layer, the second electrode comprising a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the layer of active material, and a second conductive layer arranged on the first conductive layer, the active layer being partly doped with a doping element.

[0014] Thus, advantageously according to the invention, the use of a doped active layer makes it possible to improve the switching properties of the memory cell. In particular, the active layer doped by the doping element makes it possible to improve the implementation of the write and erase cycles of the memory cell.

[0015] In addition, the use of a doped active layer makes it possible to improve the retention properties of the memory cell.

[0016] Finally, the doped active layer makes it possible to improve the temperature stability of the memory cell (which is particularly advantageous in the context of certain applications such as the automotive sector in which the memory cell is subjected to temperatures of the order of 150°Celsius (°C)). The temporal stability at room temperature is also improved. For example, during normal use, the memory cell can withstand temperatures of the order of 150°C for a ten years without its properties being degraded. The doped active layer also allows the properties of the memory cell to be preserved when it is subjected to higher temperatures of around 260°C for around ten minutes, as is the case, for example, when soldering the memory cell onto a printed circuit board (in the case of implementing surface mounting techniques or SMT for "Surface Mount Technology" according to the commonly used acronym of Anglo-Saxon origin).

[0017] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the memory cell according to one aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: - the active material layer is doped by the doping element, the dielectric oxide layer not being doped by the doping element; - the doping element is chosen from silicon, tin, germanium or carbon; - the active material layer is based on hafnium dioxide; - the layer of active material has a thickness of between 3 and 10 nanometers; - the dielectric oxide layer comprises aluminum oxide or silicon dioxide; - the dielectric oxide layer has a thickness of between 0.3 and 1.5 nanometers; - the second conductive layer is formed from a conductive material comprising a transition metal; - the conductive material of the second conductive layer is chosen from titanium nitride, tantalum nitride or tungsten; - the material of the first conductive layer is chosen from titanium, tantalum or hafnium; - the first conductive layer has a thickness of between 3 and 20 nanometers; - the second conductive layer has a thickness of between 10 and 200 nanometers; and - the second conductive layer is formed from a plurality of conductive layers.

[0018] The invention also relates to a method for manufacturing a resistive memory cell of the OxRAM type, comprising the following steps: - formation of a first electrode, - deposition of a layer of active material on the first electrode, - implantation of a doping element in the layer of active material so as to dope the active material layer with the doping element, - depositing a dielectric oxide layer on the doped active material layer, so as to form an active layer comprising the dielectric oxide layer and the active material layer, and - depositing a second electrode on the active layer, the second electrode comprising a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the layer of active material, and a second conductive layer arranged on the first conductive layer.

[0019] Thus, thanks to the invention, the implantation of the layer of active material makes it possible to improve the switching of the memory cell between the two states. The implantation of the layer of active material also makes it possible to improve the retention properties of the memory cell.

[0020] Finally, the implantation of the active material layer (but not of the dielectric oxide layer) makes it possible to improve the temperature stability of the memory cell (which is particularly advantageous in the context of certain applications such as the automotive field in which the memory cell is subjected to temperatures above 150°Celsius). The temporal stability at room temperature is also improved.

[0021] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the manufacturing method according to another aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations: - the implantation step is carried out at an implantation acceleration voltage of between 1 and 5 kilovolts, preferably between 1.5 and 2.5 kilovolts; - the doping element is silicon implanted in the layer of active material, an implantation dose of silicon in the layer of active material being between 0.5.10 15 cm 2 and 5.1015 cm2; - the first electrode and the second electrode are deposited by cathode sputtering; - the first electrode is formed by chemical vapor deposition; - the layer of active material is deposited by an atomic layer deposition method; - the layer of active material is deposited by cathode sputtering; - the layer of active material is deposited by a physical vapor deposition method; - the dielectric oxide layer is deposited by cathode sputtering; - the dielectric oxide layer is deposited by an atomic layer deposition method; - the dielectric oxide layer is deposited by a physical vapor deposition method; - the doping element is chosen from silicon, tin, germanium or carbon; - the active material layer is based on hafnium dioxide; - the layer of active material has a thickness of between 3 and 10 nanometers; - the dielectric oxide layer comprises aluminum oxide or silicon dioxide; - the dielectric oxide layer has a thickness of between 0.3 and 1.5 nanometers; - the second conductive layer is formed from a conductive material comprising a transition metal; - the conductive material of the second conductive layer is chosen from titanium nitride, tantalum nitride or tungsten; - the first conductive layer has a thickness of between 3 and 20 nanometers; and - the second conductive layer has a thickness between 10 and 200 nanometers. BRIEF DESCRIPTION OF THE FIGURES

[0022] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which:

[0023] [Fig.l] represents, in schematic form, an example of a memory cell according to the invention,

[0024] [Fig.2] is a graph representing an error rate as a function of a filing time between the different layers of the memory cell of [Fig.l],

[0025] [Fig.3a], [Fig.3b], [Fig.3c] and [Fig.3d] represent the distributions of the cells resistance-dependent memories for LRS and HRS states for two sets of memory cells considered in the present invention,

[0026] [Fig.4a], [Fig.4b], [Fig.4c] and [Fig.4d] respectively represent an enlargement of part of figures 3a to 3d,

[0027] [Fig.5] represents, in the form of a flowchart, an example of a method of fa construction of a memory cell according to the invention, and

[0028] [Fig.6a] and [Fig.6b] represent the evolution of the distributions representing the states LRS and HRS in the case of two implantation acceleration voltages.

[0029] For clarity, identical or similar elements are identified by identical reference signs throughout the figures.

[0030] DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT

[0031] The present invention aims to improve the manufacture of resistive memory cells of the OxRAM type, so as to give them optimized operation. In particular, the present invention relates to a resistive memory cell in which the switching and retention properties are improved. In addition, the resistive memory cells according to the invention have improved stability (in particular temporal stability and temperature stability) compared to known resistive memory cells.

[0032] [Fig.l] represents an example of a resistive memory cell 1 (also called “memory cell 1” hereinafter) according to the invention.

[0033] The memory cell 1 comprises a first electrode 2, a second electrode 3 and an active layer 4 arranged between the first electrode 2 and the second electrode 3.

[0034] As can be seen in [Fig.l], the memory cell 1 is in the form of a stack of layers which extends along a z axis. The first electrode 2, the active layer 4 and the second electrode 3 form the different layers of this stack. The different layers extend parallel to each other (and parallel to a substrate, not shown, on which the memory cell 1 rests). The z axis is here perpendicular to the plane of the different layers of the stack forming the memory cell 1.

[0035] Each of the layers forming the memory cell 1 is now described.

[0036] The first electrode 2 forms a lower electrode of the memory cell 1.

[0037] By convention, the terms “lower” and “upper” are used in relation to the substrate on which the memory cell 1 is manufactured. Thus, a lower layer of the memory cell will designate a layer close to the substrate, while an upper layer will designate a layer opposite and far from the substrate.

[0038] The first electrode 2 is formed from a conductive and inert material. This conductive material is in particular neutral with respect to oxygen atoms. The first electrode 2 comprises, for example, a metallic material. Here, it comprises titanium nitride (TiN). Alternatively, the conductive material may be tantalum nitride (TaN) or tungsten (W). As a further variant, other conductive materials may be used (and in particular, metal nitride more generally).

[0039] The first electrode 2 has, for example, a thickness of between 10 and 200 nanometers (nm).

[0040] The active layer 4 is arranged on the first electrode 2. It is presented here as the form of a bilayer structure. It comprises a dielectric oxide layer 12 and an active material layer 10. As can be seen in [Fig.l], the dielectric oxide layer 12 is arranged on the active material layer 10.

[0041] The dielectric oxide layer 12 is adapted to serve as a support for the formation of an electrically conductive filament, which passes through the active layer from one side to the other to electrically connect the first electrode 2 to the second electrode 3. This electrically conductive filament can be broken and then formed again several times successively during the successive write and erase (RESET) cycles, i.e. resetting, of the memory cell. In practice, this conductive filament is produced a first time during a sort of controlled electrical breakdown of the active layer (according to a usual operation called “forming”).

[0042] The dielectric oxide layer 12 comprises, for example, a metal oxide or a semiconductor oxide. Preferably, it is an aluminum oxide A12O3. Alternatively, it may also be silicon dioxide SiO2.

[0043] The dielectric oxide layer 12 here has a thickness of between 0.3 and 1.5 nm.

[0044] The active material layer 10 is arranged between the first electrode 2 and the dielectric oxide layer 12. The active material layer 10 also comprises a metal oxide or a semiconductor oxide. Preferably here, the active material layer 4 is based on amorphous hafnium dioxide HfO2. In the present description, the expression "based on" is understood to mean that the layer concerned comprises more than 50% of the element mentioned after this expression (for example here, this means that the active material layer 4 comprises more than 50% of hafnium dioxide).

[0045] Alternatively, the layer of active material may comprise tantalum(V) oxide Ta 2O5.

[0046] The layer of active material 10 here has a thickness of between 3 and 10 nm.

[0047] Advantageously according to the invention, the active layer 4 is partly doped by a doping element. The implantation of doping elements in the active layer of the memory cell makes it possible to improve the performance of the memory cell, and in particular the switching properties during the write cycles then reset of the memory cell (SET operation, when the filament is reformed resulting in the LRS state, and RESET resulting in the HRS state, when the filament is broken again by respective application of a SET, VSEt or RESET, VRESEt voltage to the terminals of the electrodes).

[0048] Furthermore, as is also described below, the implantation of the doping elements in the active layer makes it possible, during the manufacture of the memory cell, to avoid constraints on the time taken to deposit the successive layers of the memory cell.

[0049] To illustrate this, an indicator, the error rate (or BER for "Bit Error Rate" according to the commonly used acronym of Anglo-Saxon origin) on a set of memory cells is evaluated. By definition, this error rate corresponds to the percentage of memory cells of the set of memory cells considered which will not present satisfactory properties.

[0050] In practice, this error rate is evaluated by representing the distributions of the memory cells of the set considered as a function of the resistance R (in Ohm Q) for the LRS and HRS states (as represented for example in FIGS. 3a to 3d, 4a to 4d, 6a and 6b). The distributions of the memory cells are here considered in a cumulative manner (this is a cumulative distribution function or CDF for “Cumulative Distribution Function” according to the commonly used acronym of Anglo-Saxon origin). The error rate then corresponds to the point of intersection of the distributions representing the LRS and HRS states.

[0051] As can be seen in [Fig.2], in the case where the active layer is not doped by the doping element (symbols in the form of circles in [Fig.2]), the error rate associated with memory cells (in which the active layer is not doped) increases significantly (ratio 1 to 100) when the time between the deposition of the active layer 4 and the second electrode 3 increases from 20 hours to 120 hours.

[0052] On the contrary, in the case where the active layer 4 is doped by the doping element (symbols in the form of triangles in [Fig.2]), the delay between the deposition of the second electrode 3 and the active layer 4 has no influence on the error rate (which remains constant and very low because it is less than 0.1%). Thus, the implantation of doping elements in the active layer makes it possible to make the manufacture of the memory cell according to the present invention insensitive to the delay between the deposition of the different layers of the memory cell 1.

[0053] Preferably, the active material layer 10 is doped by the doping element, while the dielectric oxide layer is devoid of doping elements. In other words, according to a preferred embodiment, only the active material layer 10 of the active layer 4 is doped by the doping element. The dielectric oxide layer 12 is therefore not doped by the doping element here.

[0054] The implantation of doping elements in the layer of active material, without the dielectric oxide layer being doped, then makes it possible to improve the stability of the memory cell, in particular following the various write and reset cycles of the memory cell.

[0055] This characteristic is notably highlighted by subjecting the memory cells (in which only the active material layer is doped or in which the doping element is also present in the dielectric oxide layer) to different heating cycles and by evaluating the error rate following each of the heating cycles.

[0056] Here, a heating cycle of a few minutes (for example 3 minutes) at more than 200°C is considered (preferably at 260°C). The memory cells are subjected to several heating cycles (for example here four). The error rate is evaluated following each of the heating cycles.

[0057] Figures 3a to 3d represent the distributions of the memory cells as a function of the resistance for the LRS and HRS states for two sets of memory cells: a first set in which, for each memory cell, the active material layer is doped by the doping element (corresponding to the curve with the “square” symbol) and a second set in which, for each memory cell, the doping element is present in the active material layer and in the dielectric oxide layer (corresponding to the curve with the “circle” symbol). Figures 3a to 3d therefore relate to the same distributions of memory cells, considered after several successive heating cycles (as described previously).

[0058] Figures 4a to 4d correspond respectively to an enlargement of a part of Figures 3a to 3d.

[0059] For each set of memory cells, the dashed line curve corresponds to the distribution (as a function of the resistance) of the memory cells for the LRS state and the solid line curve corresponds to the distribution (as a function of the resistance) of the memory cells for the HRS state.

[0060] Figures 3a and 4a correspond to the distributions obtained before a first heating cycle. Figures 3b and 4b correspond to the distributions obtained after one heating cycle. Figures 3c and 4c correspond to the distributions obtained after two heating cycles. Figures 3d and 4d correspond to the distributions obtained after three heating cycles.

[0061] As defined previously, the error rate is evaluated by the intersection of the distributions representing the LRS and HRS states. As can be seen in Figures 3a to 3d, in the case where the doping element is present only in the active material layer, the error rate remains lower than 103 (regardless of the number of heating cycles applied), i.e., in the first set of memory cells, there is less than one memory cell whose operation is not reliable.

[0062] In the case where the doping element is present in the active material layer and in the dielectric oxide layer, the curves representing the distributions associated with the LRS and HRS states intersect from the first heating cycle. Furthermore, as can be seen more clearly in Figures 4b to 4d, the error rate is higher for the second set of memory cells than for the first set.

[0063] The degradations (due to temperature) of the memory cell of the first set, following these different heating cycles, are thus limited. Memory cells in which the active material layer is doped by the doping element (but not the dielectric oxide layer) therefore have better temperature stability.

[0064] Similar results are obtained to observe the temporal stability, at room temperature, of memory cells in which the layer of active material is doped by the doping element (but not the dielectric oxide layer).

[0065] The doping element is preferably silicon Si. The use of silicon as a doping element makes it possible to reinforce the effect of insensitivity to the time delay between the deposition of the different layers of the memory cell. Furthermore, the use of silicon as a doping element also makes it possible to improve the retention properties of the memory cells, i.e. the stored information has little risk of being altered.

[0066] In the case of silicon, the layer of active material 10 is for example exposed to a dose of dopant of between 0.5.1015 cm 2 and 5.1015 cm2 in order to obtain a presence of between 0.7 to 7% of silicon atoms in the layer of active material 10 (having a thickness of between 3 and 10 nm).

[0067] Alternatively, other doping elements may be used such as tin Sn, germanium Ge or carbon C. These other doping elements also make it possible to improve the switching properties of the memory cell 1.

[0068] As shown in [Fig.l], the second electrode 3 (or upper electrode) is arranged on the active layer 4. It is here in the form of a bilayer structure. It comprises a first conductive layer 20 and a second conductive layer 22.

[0069] The second conductive layer 22 is arranged on the first conductive layer 20. The second conductive layer 22 is formed from a conductive material comprising a transition metal. This conductive material is for example titanium nitride TiN. Alternatively, it may be other conductive materials such as tantalum nitride TaN or tungsten W.

[0070] The second conductive layer 22 has a thickness of between 10 and 200 nm.

[0071] The second conductive layer 22 comprises for example a plurality of conductive layers.

[0072] The second conductive layer 22 plays both the role of a protective layer (in particular preventing total oxidation of the first conductive layer), and the role of a contact layer allowing the memory cell 1 to be electrically connected to its electronic control and reading circuit.

[0073] The first conductive layer 20 is arranged on the active layer 4. It is in direct contact with the active layer 4. More particularly, it is in direct contact with the dielectric oxide layer 12 of the active layer 4.

[0074] The first conductive layer 20 has the particularity of being a layer suitable for creating oxygen vacancies in the active layer 4 when this first conductive layer 20 is in contact with the active layer 4. According to the commonly used Anglo-Saxon term, the first conductive layer 20 is a layer of the “Oxygen scavenging layer” type. Since the mechanism for forming the conductive filament in the dielectric oxide layer 12 generally involves a reorganization of the oxygen vacancies within the dielectric oxide, the first conductive layer 20 makes it possible to facilitate the exchange of oxygen with the active layer 4.

[0075] The first conductive layer comprises a metallic conductive material. Preferably, it comprises titanium Ti, tantalum Ta or hafnium Hf.

[0076] For example, when the second conductive layer 22 comprises titanium nitride, the first conductive layer 20 is formed from a conductive material chosen from titanium Ti or hafnium Hf.

[0077] Alternatively, when the second conductive layer 22 comprises tantalum nitride, the first conductive layer 20 is formed from a conductive material chosen from tantalum Ta or hafnium Hf.

[0078] As a further variant, when the second conductive layer 22 comprises tungsten, the first conductive layer 20 is formed from a conductive material chosen from titanium Ti, tantalum Ta or hafnium Hf.

[0079] Here, the thickness of the first conductive layer 20 is between 3 and 20 nm.

[0080] As indicated above, advantageously, the memory cell according to the invention has improved switching properties (between the LRS and HRS states) and retention properties. In addition, they also have improved temperature stability compared to known resistive memory cells.

[0081] The present invention also relates to a method of manufacturing a memory cell 1. [Fig. 5] represents, in the form of a flowchart, an example of a manufacturing method in accordance with the invention.

[0082] As this figure shows, the method begins with a step of forming the first electrode 2. This step therefore aims to form the first electrode 2, for example on a substrate (substrate not shown in the figures).

[0083] In practice, the first electrode 2 is for example formed by cathode sputtering in a vacuum deposition chamber. In the case where the first electrode 2 is formed from titanium nitride, this is reactive cathode sputtering.

[0084] Alternatively, the first electrode may be formed by chemical vapor deposition (e.g., titanium nitride TiN). Alternatively, the first electrode may be formed in a damascene structure.

[0085] Then, the method continues with a step of depositing the layer of active material 10 (step E4). This layer of active material 10 is formed on the first electrode 2. The deposition of the layer of active material 10 is carried out in such a way that this layer has a thickness that is substantially constant at all points. In this description, the term “substantially constant” means a thickness that does not vary by more than 20%, preferably by more than 10%, and more preferably by more than 5%.

[0086] In practice, the layer of active material 10 is deposited by an atomic layer deposition method (or ALD for “Atomic Layer Deposition” according to the commonly used acronym of Anglo-Saxon origin).

[0087] Alternatively, the layer of active material may be deposited by sputtering. Alternatively, the layer of active material may be deposited by a physical vapor deposition (PVD) method. Alternatively, the layer of active material may be deposited by an ion beam deposition (IBD) method.

[0088] As shown in [Fig.5], the method continues with step E6 of implanting the doping element in the active material layer 10 formed in step E4. The doping element is implanted, in the active material layer 10, according to a determined profile. This step then makes it possible to dope the active material layer 10 with the doping element.

[0089] In practice, the implantation step is for example implemented in a reactor different from the deposition chamber of the first electrode 2 and the layer of active material 10. This makes it possible to facilitate the manufacturing process by controlling more precisely the parameters for implementing the implantation (in particular concerning the implantation acceleration voltage and the implantation dose as described below).

[0090] Advantageously, the implantation step E6 is implemented at an implantation acceleration voltage of between 1 and 5 kilovolts (kV). More preferably, the implantation acceleration voltage is between 1.5 and 2.5 kV.

[0091] Figures 6a and 6b represent the evolution of the distributions representing the LRS and HRS states in the case of an implantation acceleration voltage of 4 kV ([Fig.6a]) and 1.5 kV ([Fig.6b]), for an implantation dose of the order of 2.1015 cm2.

[0092] As these figures show, the error rate (corresponding, in each figure, to the ordinate of the intersection of the curves associated with the LRS and HRS states) is lower in the case of a lower implantation acceleration voltage (i.e. in the case of [Fig.6b]). An implantation with a low implantation acceleration voltage is therefore more advantageous. It also allows better robustness of the retention properties of the memory cells.

[0093] Here, for example, it is a step of ionic implantation of silicon (which is the doping element) in the active material layer 10. The implantation doses are for example between 0.5.1015 cm 2 and 5.1015 cm 2. In practice, the implantation dose is adjusted according to the programming voltages used for the memory cell (and more particularly according to the forming voltage used).

[0094] Finally, step E6 therefore makes it possible to obtain a layer of active material 10 doped by the doping element.

[0095] The method then continues, in step E8, with the deposition of the dielectric oxide layer 12. This dielectric oxide layer 12 is formed on the doped active material layer 10 (obtained at the end of step E6).

[0096] In practice, the dielectric oxide layer 12 is deposited by an atomic layer deposition (or ALD) method. Alternatively, the dielectric oxide layer 12 may be deposited by cathode sputtering. As a further alternative, the dielectric oxide layer may be deposited by a physical vapor deposition (or PVD) method. As a further alternative, the dielectric oxide layer may be deposited by an ion beam deposition (or IBD) method.

[0097] As described above, the implantation of the layer of active material by the doping element makes it possible to make the manufacturing process insensitive to the delay observed between the deposition of the different layers of the stack of the memory cell 1. This thus makes it possible to carry out the deposition of the first electrode and the layer of active material in a first vacuum deposition chamber, then to carry out the implantation in another reactor (in order to better control the implantation parameters) and finally to deposit the dielectric oxide layer in the first vacuum deposition chamber. The implantation of the layer of active material therefore makes it possible to overcome time constraints for the deposition of the different layers of the stack forming the memory cell 1.

[0098] The method finally ends with a step of depositing the second electrode 3 (step E10). The second electrode 3 is formed on the active layer 4 (formed, as indicated previously, from the active material layer 10 and the dielectric oxide layer 12). More particularly, the second electrode 3 is deposited on the dielectric oxide layer 12.

[0099] As described previously, the second electrode 3 comprises the first conductive layer 20 and the second conductive layer 22. The step of depositing the second electrode 3 therefore here comprises two sub-steps: a first sub-step E 10a of depositing the first conductive layer 20 and a second sub-step E 10b of depositing the second conductive layer 22.

[0100] The first conductive layer 20 is therefore first deposited on the active layer 4 (and in particular on the dielectric oxide layer 12). The first conductive layer 20 is for example formed by cathode sputtering in a chamber vacuum deposition. This is, for example, the same deposition chamber used for the first electrode. Preferably, the deposition of the first conductive layer 20 is carried out in another vacuum deposition chamber.

[0101] Then, the second conductive layer 22 is deposited on the first conductive layer 20 formed. The second conductive layer 22 is for example formed by cathode sputtering in a vacuum deposition chamber. In practice, the second conductive layer 22 is formed in the same deposition chamber as the first conductive layer 20.

[0102] In the case where the second conductive layer is formed from titanium nitride, it is a reactive cathode sputtering.

[0103] Finally, advantageously according to the invention, the implantation of the doping element in the active layer makes it possible to improve the switching properties, and therefore to improve the implementation of successive write and erase cycles.

[0104] In addition, the use of a low implantation acceleration voltage makes it possible to improve the retention properties of the memory cell 1. The risks of alteration of the information stored in the memory cell are therefore limited.

[0105] The use of a low implantation acceleration voltage also makes it possible to make the manufacturing process insensitive to the waiting time observed between the deposition of the different layers of the stack forming the memory cell 1.

[0106] Finally, the implantation in the layer of active material 10 makes it possible to confer better temporal and temperature stability to the memory cell 1.

Claims

Claims

1. A resistive OxRAM memory cell (1) comprising a first electrode (2), a second electrode (3) and an active layer (4) extending between the first electrode (2) and the second electrode (3), the active layer (4) comprising a dielectric oxide layer (12) and an active material layer (10), the dielectric oxide layer (12) being arranged on the active material layer (10), the second electrode (3) comprising a first conductive layer (20), in contact with the active layer (4) and chosen to create oxygen vacancies in the active material layer (10), and a second conductive layer (22) arranged on the first conductive layer (20), the active layer (4) being partly doped with a doping element.

2. The memory cell (1) of claim 1, wherein the active material layer (10) is doped with the doping element, the dielectric oxide layer (12) not being doped with the doping element.

3. Memory cell (1) according to claim 1 or 2, wherein the doping element is selected from silicon, tin, germanium or carbon.

4. Memory cell (1) according to any one of claims 1 to 3, wherein the layer of active material (10) is based on hafnium dioxide.

5. Memory cell (1) according to any one of claims 1 to 4, in which the layer of active material (10) has a thickness of between 3 and 10 nanometers.

6. A memory cell (1) according to any one of claims 1 to 5, wherein the dielectric oxide layer (12) comprises aluminum oxide or silicon dioxide.

7. Memory cell (1) according to any one of claims 1 to 6, wherein the dielectric oxide layer (12) has a thickness of between 0.3 and 1.5 nanometers.

8. Memory cell (1) according to any one of claims 1 to 7, wherein the material of the first conductive layer (20) is selected from titanium, tantalum or hafnium.

9. Memory cell (1) according to any one of claims 1 to 8, wherein the conductive material of the second conductive layer (22) is selected from titanium nitride, tantalum nitride or tungsten.

10. Memory cell (1) according to any one of claims 1 to 9 wherein the first conductive layer (20) has a thickness of between 3 and 10 nanometers and / or the second conductive layer (22) has a thickness of between 10 and 200 nanometers.

11. Method for manufacturing a resistive memory cell (1) of the OxRAM type, comprising the following steps: - formation (E2) of a first electrode (2), - deposition (E4) of a layer of active material (10) on the first electrode (2), - implantation (E6) of a doping element in the layer of active material (10) so as to dope the layer of active material (10) with the doping element, - deposition (E8) of a layer of dielectric oxide (12) on the doped layer of active material (10), so as to form an active layer (4) comprising the layer of dielectric oxide (12) and the layer of active material (10), and - deposition (E10) of a second electrode (3) on the active layer (4), the second electrode (3) comprising a first conductive layer (20), in contact with the active layer (4) and chosen to create oxygen vacancies in the layer of active material (10), and a second conductive layer (22) disposed on the first conductive layer (20).

12. A manufacturing method according to claim 11, wherein the implantation step is carried out at an implantation acceleration voltage of between 1 and 5 kilovolts, preferably between 1.5 and 2.5 kilovolts.

13. A manufacturing method according to claim 11 or 12, wherein the doping element is silicon implanted in the active material layer (10), an implantation dose of the silicon in the active material layer (10) being between 0.5.1015 cm2 and 5.1015 cm2.

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