Microelectronic device comprising an enclosing grid and method for making such a device

Abstract

Title: Microelectronic Device Comprising a Surrounding Gate and Method for Implementing Such a Device. The invention relates to a device comprising transistors (T1, T2, T3), each comprising: • a channel (41) made of a semiconductor material, • a surrounding gate (50) completely enclosing said channel (41), • a source (42) and a drain (43) on either side of the channel (41), and source and drain contacts (60S, 60, 60D), • a gate dielectric layer (30) separating the channel (41) and the surrounding gate (50), • spacers (70) on either side of the gate (50). Advantageously, the gate dielectric layer (30) and the spacers (70) are formed by at least one continuous layer (73) surrounding the surrounding gate (50). The invention also relates to a method for implementing such a device. Figure for the summary: Fig. 12A

Description

Title of the invention: Microelectronic device comprising a wrapping grid and method for producing such a device Technical field

[0001] The invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of advanced FET (Field-Effect Transistor) type devices with a conformal gate and channel based on semiconductor materials, such as two-dimensional (2D) materials or semiconductor oxides. STATE OF THE ART

[0002] The constant increase in transistor performance was first made possible by the reduction in transistor dimensions, for a classic MOSFET (“Metal-Oxide-Semiconductor Field-Effect Transistor”) architecture based on silicon.

[0003] This classic architecture then gave way to other types of architectures better suited to the performances specified in technological nodes below 12 nm. The so-called "finFET" architecture, for example, makes it possible to meet the performances set by the 7 nm and 5nm technological nodes.

[0004] For the next technological nodes, in particular from 3 nm, other architectures offering improved gate confinement are necessary. An architecture envisaged to address the problems of these next technological nodes includes gate-enveloping transistors called GAA transistors (acronym for Gate Ail Around), comprising channels stacked on top of each other surrounded by a common gate.

[0005] Such an architecture typically comprises a plurality of stacked transistors, each transistor comprising: - a channel based on a semiconductor material, - a so-called wrapping gate, completely surrounding said channel, - a source and a drain on either side of the channel, and source and drain contacts drain connected respectively to the source and the drain, - a dielectric gate layer separating the channel and the fully enclosing gate, - spacers on either side of the grid, configured to isolate elec tightly the grid with respect to the source and drain contacts.

[0006] Such an architecture is typically obtained by structuring a stack of two types of alternating layers, where one of the types of layers comprises layers semiconductors intended to form the channels of the transistors, and the other type of layers includes sacrificial layers intended to be replaced by the surrounding gate.

[0007] To reduce the dimensions of the transistors and improve compactness and integration while limiting parasitic capacitances in this device architecture, one solution is to form “internal” spacers. These internal spacers are formed in the sacrificial layers, between the semiconductor layers, as illustrated for example in the document “N. Loubet et al., 2017 Symposium on VLSI Technology Digest of Technical Papers”. A difficulty related to the manufacturing of these architectures concerns the dimensional control of the internal spacers. The partial removal of the sacrificial layers to form the internal spacers remains poorly controlled. A variability in the dimensions of the internal spacers in the stack of layers is observed. It is also difficult to align these internal spacers with respect to the gate patterns defined during the structuring of the stack.

[0008] Controlled industrial manufacturing, meeting the required quality requirements, is an important issue for the development of GAA transistor technologies.

[0009] There is therefore a need for a method of manufacturing GAA transistors having improved reproducibility and limited manufacturing cost.

[0010] One objective of the invention is to propose such a reproducible, controlled manufacturing method that limits the manufacturing cost. Another objective of the invention is to propose a device having an architecture that can be reproduced more easily and with greater control. Another objective of the invention is to overcome at least in part the drawbacks of known methods and devices. SUMMARY

[0011] To achieve these objectives, according to one embodiment, a microelectronic device is provided comprising at least one transistor comprising: - at least two channels stacked along a main direction z, each channel being based on a semiconductor material, - a so-called enveloping grid, completely surrounding at least one of said channels, and preferably several channels, - a source and a drain on either side of each channel, and source and drain contacts connected respectively to the source and the drain, - a dielectric grid layer separating each channel and the surrounding grid, - spacers on either side of the grid, configured to isolate elec tightly the grid with respect to the source and drain contacts,

[0012] Advantageously, the gate dielectric layer and the spacers are formed at least by the same continuous layer surrounding the encapsulating gate.

[0013] Such a device architecture does not require implementing a withdrawal partial use of sacrificial layers to form the spacers, unlike known architectures based on “internal” spacers.

[0014] In this architecture, a single continuous layer forms both the spacers and the gate dielectric layer. Typically, the vertical portions of this continuous layer correspond to the spacers and the horizontal portions of this continuous layer correspond to the gate dielectric layer. The thickness of the continuous layer can advantageously be precisely controlled. It is significantly simpler to obtain precise control over the thickness of a layer, in this case the continuous layer, than to obtain precise control over a partial removal of a layer, as envisaged in the prior art. The dimensional control of the spacers of the device is therefore significantly improved. The spacers are further advantageously self-aligned with respect to the fully enclosing gate.

[0015] Another aspect of the invention relates to a method of manufacturing a microelectronic device, comprising the following steps: - Providing on a substrate a stack in the main direction z comprising a first plurality of first layers in a first material alternating with a second plurality of second layers in a second material, the first and second materials being different from said semiconductor material, - Form in this stack the first openings defining the first patterns, - Form sacrificial grids straddling the first patterns and partly in the first openings, - Form in the first patterns second openings defining second patterns, - Completely remove, from the second openings, the first material of the first layers so as to form the first spaces, - Remove the sacrificial grids so as to form third openings, - Completely remove, from the third openings, the second material of the second layers, so as to form second spaces, - Deposit a continuous layer, based on a dielectric material, around the second layers or in the second spaces, so as to form: • A grid dielectric layer from the horizontal parts of the continuous layer, • Spacers from the vertical parts of the continuous layer, - After forming the continuous layer, deposit a layer based on a semiconductor material in the first spaces, so as to form: • channels based on the semiconductor material, and • sources and drains based on the semiconductor material on either side of the channels, - After forming the continuous layer, fill the second spaces with a material, called gate material, so as to form so-called wrapping gates completely surrounding at least one of the channels of the at least one transistor.

[0016] A principle of the method according to the invention consists in forming a continuous layer comprising both the spacers and the gate dielectric layer. This continuous layer can be formed around the second layers, when the method is typically of the "gate last" type (the replacement of the sacrificial gates by functional gates is done after the formation of the transistor channels). Alternatively, the continuous layer can be formed in the second spaces, when the method is typically of the "gate first" type (the replacement of the sacrificial gates by functional gates is done before the formation of the transistor channels). The advantages mentioned above in the context of the device for the continuous layer apply mutatis mutandis to the method. The continuous layer can in particular be deposited by precisely controlling its thickness, at the level of the vertical parts and at the level of the horizontal parts.The continuous layer can, for example, be deposited in a conformal manner.

[0017] Another principle of the method according to the invention consists in selectively replacing certain layers of the initial stack with a semiconductor material in order to form the transistor channels. The initial stack does not include the semiconductor material. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material. According to a preferred possibility, the semiconductor material is a two-dimensional (2D) material chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S) or selenium (Se).

[0018] Thus, the method according to the invention makes it possible to introduce layers of 2D material after structuring the stack. This advantageously makes it possible to limit the risk of degradation of the 2D material during the process. The 2D material is not exposed at all stages of the manufacturing process. The 2D material is thus preserved.

[0019] Furthermore, the late introduction of the 2D material during the manufacturing process makes it possible to use standard microelectronics technologies for the formation and structuring of the stack. There is no need to modify or adapt the standard technological structuring steps to the constraints of using the 2D material. The costs of the process are thus advantageously limited. The process can also be more easily implemented in existing production lines.

[0020] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits can be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0021] [Fig. 1 A] [Fig.2A] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.6A] [Fig.7A] [Fig.8A] [Fig.9A] [Fig. 10 A][Fig.llA][Fig.l2A] Figures nA (n=1...12) schematically illustrate, along xz cross sections, steps in manufacturing a device with superimposed transistors, according to a first embodiment of the present invention.

[0022] [Fig.lB][Fig.2B][Fig.3B][Fig.4B][Fig.5B][Fig.6B][Fig.7B][Fig.8B][Fig.9B][Fig.l0 B][Fig.llB][Fig.l2B] Figures nB (n=1...12) schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device, according to a first embodiment of the present invention.

[0023] [Fig. 13A] [Fig. 14A] [Fig. 15A] [Fig. 16A] [Fig. 17A] [Fig. 18A] [Fig. 19A][Fig.20A] The Figures nA (n=13...2O) schematically illustrate, along xz cross sections, steps in manufacturing a device with superimposed transistors, according to a second embodiment of the present invention.

[0024] [Fig. 13B] [Fig. 14B] [Fig. 15B] [Fig. 16B] [Fig. 17B] [Fig. 18B] [Fig. 19B] [Fig.20B] The figures nB (n=13...2O) schematically illustrate according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device, according to a second embodiment of the present invention.

[0025] [Fig.21 A] [Fig.22A] [Fig.23 A] [Fig.24A] [Fig.25 A] [Fig.26A] [Fig.27 A] [Fig.28 A] [Fig.2 9A][Fig.30A][Fig.31A] Figures nA (n=21...31) schematically illustrate, along xz cross sections, steps in manufacturing a device with superimposed transistors, according to a third embodiment of the present invention.

[0026] [Fig.2 IB] [Fig.22B] [Fig.23B] [Fig.24B] [Fig.25B] [Fig.26B] [Fig.27B] [Fig.28B] [Fig.29 B][Fig.30B][Fig.31B] Figures nB (n=21...31) schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device, according to a third embodiment of the present invention.

[0027] The first and second embodiments provide for the replacement of the sacrificial gates after formation of the transistor channels. They typically correspond to so-called “gate last” embodiments (the gate is formed last). The third embodiment provides for the replacement of the sacrificial gates before formation of the transistor channels. It typically corresponds to a so-called “gate first” embodiment (the gate is formed first).

[0028] In the cross-sectional figures, section planes are indicated (A-A', B-B', ..., P-P', ..., Z-Z', a- a', ..., e-e') with cross-references to the section planes of the corresponding figures. The drawings are given as examples and are not intended to be reproduced in any form or by any means. of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, not all alphanumeric references are systematically repeated from one figure to another. It is understood that the elements already described and referenced, when they are reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0029] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0030] According to one example, the stack comprises an alternation of a first layer of the first plurality with a second layer of the second plurality. Preferably, said first layer and said second layer are in contact. According to one example, the final device comprises transistor channels formed after selective removal of the first layers of the initial stack. According to one example, the final device comprises conformal gates formed after selective removal of the second layers of the initial stack. The initial stack typically does not comprise the semiconductor material of the transistor channels, nor the material of the conformal gates.

[0031] According to one example, the continuous layer has so-called horizontal parts, extending in a plane perpendicular to the main direction z and so-called vertical parts, extending in planes parallel to the main direction z, and the gate dielectric layer corresponds to the horizontal parts of the continuous layer, and the spacers correspond to the vertical parts of the continuous layer.

[0032] According to one example, the vertical parts of the continuous layer, intended to form the spacers, have a thickness different from that of the horizontal parts of the continuous layer, intended to form the gate dielectric layer.

[0033] According to another example, the deposition of the continuous layer is conformal and the vertical and horizontal parts have substantially the same thickness.

[0034] According to one example, the continuous layer has a substantially constant thickness.

[0035] According to one example, the continuous layer comprises a plurality of continuous layers superimposed on each other.

[0036] According to one example, the fully enclosing grid is common to all the channels of the at least one transistor, said gate having an upper portion flanked by additional spacers without continuity with the gate dielectric layer. These additional spacers are typically in direct contact with the sides of the surrounding gate. These additional spacers make it possible to reduce parasitic capacitances in the device.

[0037] According to one example, the source and the drain are common to all the channels of the at least one transistor.

[0038] According to one example, the deposition of the layer based on the semiconductor material is configured to form vertical portions of the layer based on the semiconductor material on the sides of the second pattern and horizontal portions of the layer based on the semiconductor material in the first spaces. This makes it easier to reconnect the source and drain contacts in the device.

[0039] According to one example, the vertical portions of the layer based on the semiconductor material are thicker than the horizontal portions. Thicker vertical portions make it possible to reduce the contact resistance of the source and drain contacts.

[0040] According to one example, the method comprises forming source and drain contacts in the second openings, after deposition of the layer based on the semiconductor material.

[0041] According to one example, the formation of the encapsulating gates is carried out after the deposition of the layer based on the semiconductor material. This type of process, called "gâte last", where the functional gate is formed at the end of the process in replacement of a sacrificial gate, makes it possible to preserve the dimensional characteristics of the functional gate. The thermal budget linked to the deposition of the semiconductor material does not impact the equivalent thickness of gate oxide at the interface with the gate. The structural and electrical characteristics of the functional gate are better controlled.

[0042] According to one example, the removal of the sacrificial gates and the removal of the second material from the second layers are carried out after deposition of the layer based on the semiconductor material. According to one example, the deposition of the at least one continuous layer is carried out around the second layers.

[0043] According to one example, the removal of the first material of the first layers is carried out selectively to the second material of the second layers.

[0044] According to one example, the method further comprises, before forming the second openings, forming additional spacers on the first patterns and bordering the sacrificial gates.

[0045] According to one example, the method is a “gâte last” type method and comprises the steps below chained in the following order: - Provide on a substrate the stacking according to the main direction z comprising the first plurality of first layers of a first material alternating with the second plurality of second layers of a second material, the first and second materials being different from the semiconductor material, - Form in this stack the first openings defining the first patterns, - Form the sacrificial grids straddling the first patterns and partly in the first openings, - Form in the first patterns the second openings defining the second patterns, - Completely remove, from the second openings, the first material of the first layers so as to form the first spaces, - Deposit the continuous layer, based on a dielectric material, around the second layers, so as to form: • the grid dielectric layer from the horizontal parts of the continuous layer, • the spacers from the vertical parts of the continuous layer, - Deposit the layer based on a semiconductor material on the layer continues, in the first spaces, so as to form: • channels based on the semiconductor material, and • sources and drains based on the semiconductor material on both sides on the other side of the canals, - Remove the sacrificial grids to form the third openings, - Completely remove, from the third openings, the second material of the second layers, so as to form the second spaces, - Filling the second spaces with the gate material, so as to form the surrounding gates completely surrounding at least one channel of the at least one transistor.

[0046] According to one example, the removal of the sacrificial gates and the removal of the second material from the second layers are carried out before deposition of the layer based on the semiconductor material. According to one example, the deposition of the at least one continuous layer is carried out in the second spaces.

[0047] According to one example, the method further comprises, after forming the second openings, depositing at least one retaining layer in said second openings, on exposed sides of the first and second layers.

[0048] According to one example, the method further comprises, after filling the second spaces with the grid material, removing the at least one retaining layer so as to expose the sides of the first layers.

[0049] According to one example, the method is a “gate first” type method and comprises the steps below chained in the following order: - Providing on a substrate the stack in the main direction z comprising the first plurality of first layers in a first material alternating with the second plurality of second layers in a second material, the first and second materials being different from the semiconductor material, - Form in this stack the first openings defining the first patterns, - Form the sacrificial grids straddling the first patterns and partly in the first openings, - Form in the first patterns the second openings defining the second patterns, - Forming the retaining layer in said second openings, on exposed sides of the first and second layers, - Remove the sacrificial grids to form the third openings, - Completely remove, from the third openings, the second material of the second layers, so as to form the second spaces, - Deposit the continuous layer, based on a dielectric material, in the second spaces, so as to form: • the grid dielectric layer from the horizontal parts of the continuous layer, • spacers from the vertical parts of the continuous layer, - Fill the second spaces with the grid material, so as to form the surrounding grids, - Remove the retaining layer so as to expose the sides of the first layers, - Completely remove, from the second openings, the first material of the first layers so as to form the first spaces, - Deposit the layer based on a semiconductor material on the continuous layer, in the first spaces, so as to form: • the channels based on the semiconductor material, and • sources and drains based on the semiconductor material on both sides other channels.

[0050] According to one example, the deposition of the continuous layer is carried out by chemical vapor deposition or by atomic layer deposition. Chemical vapor depositions are easy to implement. Atomic layer depositions make it possible to precisely control the thickness of the continuous layer based on the dielectric material.

[0051] According to one example, the deposition of the layer based on the semiconductor material is carried out by chemical vapor deposition or by atomic layer deposition. Chemical vapor depositions are easy to implement. Atomic layer depositions make it possible to precisely control the thickness of the layer based on the semiconductor material.

[0052] According to one example, the semiconductor material is chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

[0053] According to another example, the semiconductor material is chosen based on a semiconductor oxide, for example based on IGZO (zinc-indium-gallium oxide), In2O3, IWO (indium-doped indium oxide), ITO (tin-indium oxide), IAZO (zinc-indium-aluminium oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide.

[0054] According to one example, the first material is chosen from SiGe and the second material is chosen from Si, or vice versa. These materials can be easily epitaxially grown using conventional microelectronics technological processes. This makes it possible to benefit from existing technological pathways. The cost of the process is reduced.

[0055] According to one example, the formation of the sacrificial gates is carried out such that the sacrificial gates extend over an entire height of the first openings. According to one example, the first openings extend over the entire height of the stack of the first and second layers. The sacrificial gates extend over the entire height of the stack. The sacrificial gates typically rest on the substrate. This makes it possible to provide access to all the layers of the stack via the third openings, when removing the sacrificial gates.

[0056] According to one example, the deposition of the layer based on the semiconductor material is configured so that the layer based on the semiconductor material completely fills the first spaces.

[0057] According to another example, the deposition of the layer based on the semiconductor material is configured so that the layer based on the semiconductor material partially fills the first spaces. According to one example, the method further comprises, after deposition of the layer based on the semiconductor material, a deposition of a dielectric layer configured to fill the first spaces. This makes it possible to form a layer based on the semiconductor material of low thickness, without constraint on the thickness of the first layers of the initial stack. The layer based on the semiconductor material may have a thickness less than that of the first layers of the initial stack.

[0058] According to one example, the substrate is a solid silicon-based substrate.

[0059] According to one example, the stack comprises at least three first layers of the first material alternating with three second layers of the second material.

[0060] According to one example, the stack comprises as many first layers of the first material as second layers of the second material.

[0061] According to one example, the removal of the first material of the first layers selectively to the second material of the second layers is carried out by a first selective etching having a SiO:2o selectivity of at least 5:1, preferably at least 10:1. This first selective etching is typically stopped in time.

[0062] According to one example, the removal of the second material of the second layers selectively to the first material of the first layers is carried out by a second selective etching having a S2o:io selectivity of at least 5:1, preferably at least 10:1.

[0063] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features and advantages of one aspect of the invention, for example the device or the method, may be adapted mutatis mutandis to the other aspect of the invention.

[0064] The invention relates generally to a microelectronic device with GAA transistors and a method of manufacturing this device. Such a microelectronic device may have a “GAA stacked nanosheet” type architecture, i.e. with stacked nanosheets and a fully encapsulating gate. An architecture with stacked nanowires and a fully encapsulating gate is also possible.

[0065] The nanowires or nanosheets typically each comprise a conduction channel of a transistor. These channels are stacked in a z direction. This means that they each occupy a level of given altitude in the z direction. A level can be defined between two planes perpendicular to the z direction.

[0066] Advantageously, the method according to the invention can be implemented for the production of GAA MOS transistors for the 5 nm and sub-5 nm technological nodes.

[0067] A microelectronic device comprising superimposed GAA transistors can be advantageously integrated into logic systems having 3D architectures. These transistors can in particular be associated with other structural or functional elements so as to design complex systems.

[0068] A particular aspect of the invention concerns the implementation of 2D materials to produce the nanowires or nanosheets of the device.

[0069] 2D materials typically correspond to compounds with a lamellar structure consisting of two-dimensional sheets, stacked along the crystallographic axis c. The atomic bonds within each sheet are strong, covalent in nature. The bonds between sheets are much weaker, of the Van der Waals. These two-dimensional sheets are also called monolayers.

[0070] In the context of the present invention, the monolayers are preferably semiconductor monolayers of the MX2 type where M is molybdenum (Mo) or tungsten (W) and X is sulfur (S) or selenium (Se). Each "monolayer" is here composed of a plane of metal cations M inserted between two planes of anions X. A monolayer therefore typically comprises three atomic planes: the atoms of the transition metal (Mo or W) form a plane sandwiched between two planes of chalcogens (S, Se or Te, for example). Each transition metal atom is connected to six chalcogen atoms. These anions are in trigonal prismatic coordination with respect to the metal atoms. The monolayers of MX2 transition metal dichalcogenides have a hexagonal atomic lattice.

[0071] The monolayers of transition metal dichalcogenides MX2 are preferably based on molybdenum disulfide MoS2, MoSe2, MoTe2, WS2, WSe2.

[0072] An alternative possibility concerns the implementation of semiconductor oxides to produce the nanowires or nanosheets of the device. These semiconductor oxides are preferably based on IGZO (indium-gallium zinc oxide), In2O3, IWO (tungsten-doped indium oxide), InGaZnO, InGaO, InZnO, IAZO or ITO (indium-tin oxide). Another possibility concerns the implementation of graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in particular in the form of a monolayer.

[0073] It is specified that, in the context of the present invention, the terms “on”, “overcomes”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0074] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0075] A “continuous” layer is understood to mean a layer having continuity of material. Typically, the continuous layer coats the second layers of the second patterns, or lines the second spaces of the second patterns.

[0076] The word "dielectric" describes a material whose electrical conductivity is sufficient particularly low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 20. In the present invention, the dielectric layer may have ferroelectric properties.

[0077] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0078] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0079] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0080] The term “selective etching with respect to” or “etching exhibiting selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0081] The various patterns formed during the manufacturing steps typically have a structure intended to evolve during the process steps. Thus, the patterns may comprise the sacrificial layers of the initial stack, the layers based on 2D material or semiconductor oxide, the dielectric layers, continuous or discontinuous. The various patterns aim to form, at the end of the process, “transistor patterns” each comprising at least one conduction channel and a gate surrounding said channel, a dielectric barrier separating the gate and the channel, a source and a drain on either side of the channel. The assignment of the first and second layers in the initial stack may be reversed.

[0082] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0083] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken in a direction normal to the main extension plane of the layer or the film. Thus, a surface layer of silicon (topSi) typically has a thickness along z. A grid pattern formed on such a surface layer has a height along z. The relative terms "on", "overlies", "under", "underlying" refer to positions taken along the z direction. The terms "vertical", "vertically" refer to orientations along the z direction. A vertical portion typically extends along a plane including the z direction. The terms "horizontal", "horizontally" refer to orientations perpendicular to the z direction. A horizontal portion typically extends along an xy plane perpendicular to the z direction. A "lateral" dimension corresponds to a dimension along a direction of the xy plane. A "lateral" or "laterally" extension means an extension along one or more directions of the xy plane.

[0084] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0085] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0086] The following description presents examples of implementation of the method according to the invention in a context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0087] Figures 1A, 1B to 12A, 12B schematically illustrate steps of manufacturing a device comprising GAA transistors according to a first embodiment. Figures nA (n=1... 12) correspond to first transverse sections each illustrating a different step of the manufacturing method. Figures nB (n=1... 12) correspond to second transverse sections each illustrating the same step as the corresponding figure nA.

[0088] As illustrated in Figures 1A, 1B, a first step consists of producing a stack E of semiconductor layers 10, 20 on a substrate S. The substrate S may be a substrate of the SOI (Silicon on Insulator), GeOI (Germanium on Insulator) or SGOI (Silicon-Germanium on Insulator) type. These known substrates comprise, according to the terminology common to those skilled in the art, a thick silicon SI layer called “Si bulk”, a silicon oxide S2 layer called “BOX” (Burried Oxide) and a thin surface layer, respectively based on silicon, germanium or silicon-germanium. This thin surface layer may advantageously correspond to the first layer 10 of the stack E.

[0089] Alternatively, the substrate S can be a bulk Si substrate.

[0090] The stack E comprises, according to one example, an alternation of first layers 10 in silicon-germanium (SiGe) and second layers 20 in silicon (Si).

[0091] The concentration of Ge in the SiGe alloy can be 20%, 30% or 45% for example. This concentration of germanium is chosen so as to allow good selectivity of the etching of the SiGe compared to the Si, during the selective etching steps. The higher the concentration of Ge, the greater the selectivity to Si will be during the subsequent removal of the SiGe. This stack E is advantageously formed by epitaxy of the layers of SiGe 10 and Si 20. This step of forming the stack E is inexpensive and well known to those skilled in the art. The thicknesses of the Si and SiGe layers can typically be of the order of 10 nm, and more generally between 5 nm and 20 nm for example. In a known manner in order to avoid the formation of structural defects, the maximum thicknesses permitted for the layers 10 in SiGe depend in particular on the chosen Ge concentration.

[0092] In the example illustrated in figures 1A, 1B four layers 10 of SiGe are alternated with three layers 20 of epitaxially grown Si. A Si / SiGe superlattice is thus obtained. The number of Si and SiGe layers can naturally be increased. This ultimately makes it possible to increase the number of stacked transistors in the final device.

[0093] Generally, the first material of the first layers 10 and the second material of the second layers 20 are chosen so that one can be etched selectively relative to the other. Thus, other pairs of first and second materials are possible. By respecting this condition of selectivity during etching, the first and second materials can be chosen from dielectric materials (oxides and nitrides for example), semiconductor materials, metallic materials.

[0094] As illustrated in Figures 2A, 2B, a conventional lithography / etching step is carried out in order to define first patterns 101M, and first openings 100. The etching is anisotropic and directed along z. It is configured to etch the stack E, here the Si / SiGe superlattice, over its entire height, stopping on the substrate S, here the BOX S2. It can be carried out by plasma using an HBr / 02 etching chemistry. The first patterns 10IM can have a length Li along x of between 10 nm and 500 nm. They preferably have a width li along y of between 10 nm and 120 nm, for example of the order of 40 nm. This first structuring of the E stack in the form of fins or "fins" according to current Anglo-Saxon terminology, makes it possible to define a plurality of superimposed nanowires or nanosheets.

[0095] For the sake of clarity, the following figures iB (i=3... 12) illustrate only one “end” pattern 101M.

[0096] As illustrated in Figures 3A, 3B, sacrificial gates 150 are then formed on the “end” patterns 101M. The formation of these sacrificial gates 150 is typically done by deposition then lithography / etching. The formation of the sacrificial gates 150 is configured so that the sacrificial gates 150 are straddled on the “end” patterns 101M, as illustrated in [Fig.3B]. The sacrificial gates 150 typically comprise an upper portion located on the “end” pattern 101M, and lateral portions located on the lateral flanks of the “end” pattern 101M. The sacrificial gates 150 typically rest on the substrate S. At this stage, the sacrificial gates 150 are typically surmounted by an etching mask 160, called a hard mask, implemented in the structuring of the sacrificial gates 150. The sacrificial gates 150 comprise, for example, in a known manner, a thin oxide layer SiO2 (thickness between 3 nm and 7 nm for example) and a thick layer of polycrystalline silicon.The thin oxide layer SiO2 may form a barrier layer during the etching of the polycrystalline silicon of the sacrificial gates 150. The hard mask 160 may be based on silicon oxide SiO2, silicon nitride SiN, or a SiO2 / SiN bilayer.

[0097] As illustrated in Figures 4A, 4B, after formation of the sacrificial gates 150 by lithography / etching, the anisotropic etching along z is extended in order to define second patterns 102M, and second openings 200. The etching is configured to etch the stack E over its entire height, stopping on the substrate S. It can be carried out by plasma using an HBr / O2 etching chemistry.

[0098] As illustrated in Figures 5A, 5B, a dielectric layer 25, for example based on SiO2, is deposited on and between the second patterns 102M. This dielectric layer 25 is then planarized, typically by chemical mechanical polishing CMP with stopping on the hard masks 160, then opened by etching so as to reform and / or redefine the second openings 200. The second openings 200 are intended to receive the source and drain contacts.

[0099] As illustrated in Figures 6A, 6B, after formation of the second openings 200, the first layers 10 are completely etched selectively to the second layers 20, to the substrate S and to the sacrificial gates 150. The etching of the first material of the first layers 10 typically has a SiO:2o selectivity with respect to the second material of the second layers 20, of at least 5:1, preferably at least 10:1. This first etching aims to form first spaces 11 between the second layers 20 of the second patterns 102M. This total etching can be stopped at the time, possibly after an over-etching time aimed at guaranteeing the total removal of the first material of the first layers 10. This total etching has an isotropic character and can be carried out by a wet or dry method, from the second openings 200.

[0100] As illustrated in Figures 7A, 7B, a continuous layer 73 is then deposited in the second openings 200, around the second layers 20 of the second patterns 102M and around the sacrificial gates 150, in the first spaces 11. The continuous layer 73 typically has a permittivity of between 4 and 25. This continuous layer 73 can thus be based on a dielectric material with high permittivity, for example based on HfO2. The continuous layer 73 is intended to form both the gate dielectric layer 30 between the channels of the GAA transistors and their surrounding gates, and the spacers 70 on the sides of the second layers 20 and the sacrificial gates 150. The horizontal portions of the continuous layer 73 typically form the gate dielectric layer 30. The vertical portions of the continuous layer 73 typically form the spacers 70.The continuous layer 73 may be formed by chemical vapor deposition (CVD), by chemical vapor deposition with organometallic precursors (MOCVD) or by atomic layer deposition (ALD). The continuous layer 73 typically has a thickness of between 1 nm and 5 nm. It may be deposited conformally. It then has a substantially constant thickness. Alternatively, the deposition may be configured so that the vertical portions of the continuous layer 73 have a thickness greater than the horizontal portions of the continuous layer 73.

[0101] According to one possibility, several continuous layers 73 are deposited on top of each other. This makes it possible to adjust the thicknesses of the gate dielectric layer 30 and the spacers 70. This makes it possible to adjust the dielectric properties of the gate dielectric layer 30 and the spacers 70.

[0102] As illustrated in Figures 8A, 8B, a layer 40 based on a semiconductor material is then deposited on the continuous layer 73 in the first spaces 11. The deposition of the semiconductor material is here configured so that the layer 40 completely fills the first spaces 11. The portions of the layer 40 located in the first spaces 11 thus have a perfectly controlled thickness, close to the thickness of the first initial layers. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the sacrificial gates 150 and the second layers 20. This layer 40 is also intended to form the sources 42 and the drains 43 of the GAA transistors directly above the spacers 70.

[0103] The layer 40 is also typically deposited outside the first spaces 11, on (part or all of) the sides of the spacers 70. This makes it possible to improve the contact recovery with the sources 42 and the drains 43 of the GAA transistors. The layer 40 thus has horizontal portions in the first spaces 11, in particular between the second layers, and vertical portions on the sides of the spacers 70, without discontinuity. According to one possibility, the thickness of the vertical portions of the layer 40 is greater than the thickness of the horizontal portions of layer 40. This makes it possible to reduce the contact resistance for the sources 42 and drains 43 of the GAA transistors.

[0104] The semiconductor material of the layer 40 is advantageously a two-dimensional material taken from the transition metal dichalcogenides MX2 with M molybdenum (Mo) or tungsten (W), and X sulfur (S), selenium (Se) or tellurium (Te). Such a 2D material can advantageously be deposited in the form of a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers. The deposition of this 2D material can be done by CVD, MOCVD or ALD. According to another possibility, the semiconductor material of the layer 40 is a semiconductor oxide such as 1TTO (acronym for “Indium Tin Oxide”), 1TGZO (acronym for “Indium Gallium Zinc Oxide”), IWO (meaning “tungsten doped indium oxide”), indium oxide In2O3.Alternatively, the semiconductor material of layer 40 is graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in the form of a monolayer or a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers.

[0105] As illustrated in Figures 9A, 9B, the second openings can then be filled with one or more metal layers 60, for example based on Ti, TiN, W, in order to form the source and drain contacts. Chemical mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M. The hard masks 160 are thus exposed.

[0106] As illustrated in Figures 10A, 10B, the hard masks 160 are first removed, then the sacrificial gates 150 are also removed. One or more oxide plugs may be made on the source and drain contacts before these removals, to protect the metal layers 60 during the removal of the hard masks 160 and the sacrificial gates 150. This removal may be carried out by wet etching with a stop on the continuous layer 73. This wet etching typically has a high selectivity with respect to the continuous layer 73. This wet etching may be based on a solution of ammonia salts TMAH (Tetramethylammonium Hydroxide) or TEAH (Tetraethylammonium Hydroxide). The removal of the sacrificial gates 150 is typically carried out in two stages, with a first etching of the polycrystalline silicon and stopping on the thin oxide layer SiO2, then a second etching of this thin oxide layer SiO2.The removal of the sacrificial grids 150 makes it possible to form a main space 201 and third openings 300 opening onto the second layers 20 ([Fig.10B]).

[0107] As illustrated in Figures 1 1A, 1 1B, the second layers 20 are then completely removed by selective etching with respect to the continuous layer 73, from the third openings 300. This etching aims to form second spaces 21 in place of the second layers 20. This etching has an isotropic character and can be carried out by wet or dry means, from the third openings 300.

[0108] As illustrated in Figures 12A, 12B, the main spaces 201 and the second spaces 21 are then filled with one or more metal layers 50, for example based on TiN, W, in order to form the encapsulating gates of the GAA transistors. According to one possibility, before deposition of the metal layers 50, a dielectric layer 51 based on a high permittivity material, for example based on HfO2, is previously deposited in the main spaces 201 and the second spaces 21. This makes it possible to increase the thickness of the gate dielectric layer between the channels 41 of the GAA transistors and their encapsulating gates 50. This makes it possible to increase the thickness of the spacers between the encapsulating gates 50 and the sources and drains of the GAA transistors. A chemical-mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M.

[0109] A microelectronic device comprising two transistors T1, T2 each comprising four channels 41a, 41b, 41c, 41d stacked along z, with a covering gate 50, is thus advantageously obtained. The channels 41a, 41b, 41c, 41d, the sources 42 and the drains 43 are preferably based on a two-dimensional material. Source and drain contacts 60S, 60, 60D electrically connect these GAA transistors T1, T2.

[0110] Figures 13A, 13B to 20A, 20B schematically illustrate steps of manufacturing a device comprising GAA transistors according to a second embodiment. Figures nA (n=13...20) correspond to first transverse sections each illustrating a different step of the manufacturing method. Figures nB (n=13...20) correspond to second transverse sections each illustrating the same step as the corresponding figure nA.

[0111] Only the different characteristics of this second embodiment with respect to the first embodiment are described below. The other characteristics are deemed identical to those of the first embodiment, with reference to the above.

[0112] As illustrated in Figures 13A, 13B, after formation of the first patterns 101M and the sacrificial grids 150 straddling these patterns 101M, additional spacers 170 are formed on the yz-oriented flanks of the sacrificial grids 150. In general, in projection along z, these spacers form a continuous ring around each sacrificial grid 150, with a closed contour. In transverse section, however, along the xz plane illustrated in [Fig. 13A], the spacer 170 has two facing parts on each of the flanks of the sacrificial grid 150. These two parts are gener- commonly referred to as the spacers 170, even though these may be considered to belong to a single spacer. The spacers 170 typically extend to an upper face of the hard masks 160. The spacers 170 are typically based on silicon nitride SiN or a dielectric material with a low dielectric constant. The spacers 170 typically have a thickness along x of between 2 nm and 7 nm. These spacers 170 may be formed by deposition and anisotropic etching along z.

[0113] As illustrated in Figures 14A, 14B, after formation of the additional spacers 170, the anisotropic etching along z is extended in order to define the second patterns 102M, and the second openings 200, as previously.

[0114] As illustrated in Figures 15A, 15B, a dielectric layer 25, for example based on SiO2, is deposited on and between the second patterns 102M, then planarized and opened, as previously.

[0115] As illustrated in Figures 16A, 16B, after formation of the second openings 200, the first layers 10 are completely etched selectively to the second layers 20 to form the first spaces 11, as previously.

[0116] As illustrated in Figures 17A, 17B, a continuous layer 73 is then deposited in the second openings 200, around the second layers 20 of the second patterns 102M and on the additional spacers 170, in the first spaces 11. This continuous layer 73 is formed as previously. A layer 40 based on the semiconductor material is then deposited on the continuous layer 73 in the first spaces 11 and on the vertical portions of the continuous layer 73. This layer 40 is formed as previously.

[0117] As illustrated in Figures 18A, 18B, the second openings are then filled with one or more metal layers 60 to form the source and drain contacts, as before.

[0118] As illustrated in Figures 19A, 19B, the hard masks 160 are removed, then the sacrificial gates 150 are also removed. This removal can be carried out by wet etching with stop on the continuous layer 73 and on the spacers 170. This wet etching typically has a high selectivity with respect to the continuous layer 73 and the spacers 170. This wet etching can be based on a solution of ammonia salts TMAH (Tetramethylammonium Hydroxide) or TEAH (Tetraethylammonium Hydroxide). The second layers 20 are then completely removed by selective etching with respect to the continuous layer 73, from the third openings 300. A main space 201 and second spaces 21 are thus formed, as previously.

[0119] As illustrated in Figures 20A, 20B, the enclosing grids 50 are then formed in the main spaces 201 and the second spaces 21, as previously. A dielectric layer 51 may be previously deposited in the main spaces 201 and the second spaces 21, as previously. A microelectronic device comprising two transistors T1, T2 each comprising four channels 41a, 41b, 41c, 41d stacked along z, with a conformal gate 50, is thus advantageously obtained. The channels 41a, 41b, 41c are completely coated by the conformal gate 50. The channel 41d is partially coated by the conformal gate 50. The channels 41a, 41b, 41c, 41d, the sources 42 and the drains 43 are preferably based on a two-dimensional material. Source and drain contacts 60S, 60, 60D electrically connect these channels 41a, 41b, 41c, 41d stacked along z. Advantageously, the additional spacers 170 of this second embodiment make it possible to reduce the parasitic capacitances of the device.

[0120] The first and second embodiments are of the “gate last” type. Figures 21A, 21B to 31A, 31B schematically illustrate steps of manufacturing a device comprising GAA transistors according to a third embodiment of the “gate first” type. Figures nA (n=21.. .31) correspond to first transverse sections each illustrating a different step of the manufacturing method. Figures nB (n=21...31) correspond to second transverse sections each illustrating the same step as the corresponding figure nA.

[0121] Only the different characteristics of this third embodiment with respect to the first and second embodiments are described below. The other characteristics are deemed identical to those of the first and / or second embodiment, with reference to the above.

[0122] As illustrated in Figures 21A, 21B, after formation of the second patterns 102M and the second openings 200 as in the first embodiment, a holding layer or liner 80 is deposited on said patterns 102M and in the second openings 200. This holding layer 80 is for example based on SiN. It typically has a thickness of between 3 nm and 7 nm.

[0123] As illustrated in Figures 22A, 22B, a dielectric layer 26, for example based on SiO2, is deposited on the holding layer 80. It typically has a large thickness, for example of the order of 600 nm. This dielectric layer 26 is then planarized, typically by chemical-mechanical polishing CMP with stopping on the hard masks 160.

[0124] As illustrated in Figures 23A, 23B, at this stage the hard masks 160 are removed, then the sacrificial gates 150 are also removed. This removal can be carried out by wet etching with stop on the holding layer 80 and on the first material of the first layers 10. This wet etching typically has a high selectivity with respect to the holding layer 80 and the first material. This wet etching can be based on a solution of ammonia salts TMAH (Ammonium Hydroxide) Tetramethylammonium) or TEAH (Tetraethylammonium Hydroxide). This removal of the sacrificial grids 150 makes it possible to form a main space 201 and third openings 300 opening in particular onto the second layers 20 ([Fig.23B]).

[0125] As illustrated in figures 24A, 24B, the second layers 20 are then completely removed by selective etching with respect to the first material of the first layers 10, from the third openings 300. A main space 201 and second spaces 21 are thus formed, as previously.

[0126] As illustrated in Figures 25A, 25B, a continuous layer 73 is then deposited in the main space 201 and in the second spaces 21, from the third openings 300. This continuous layer 73 is formed as previously. It is intended to form both the gate dielectric layer 30 between the channels of the GAA transistors and their surrounding gates, and the spacers 70. The horizontal portions of the continuous layer 73 typically form the gate dielectric layer 30. The vertical portions of the continuous layer 73 typically form the spacers 70. The spacers 70 here bear on the holding layer 80.

[0127] According to one possibility, several continuous layers 73, for example based on SiO2 and / or HfO2 and / or Al2O3, are deposited on top of each other. This makes it possible to adjust the thicknesses of the gate dielectric layer 30 and the spacers 70. This makes it possible to adjust the dielectric properties of the gate dielectric layer 30 and the spacers 70.

[0128] As illustrated in figures 26A, 26B, the main spaces 201 and the second spaces 21 are then filled with one or more metal layers 50, for example based on TiN, W, in order to form the surrounding gates of the GAA transistors.

[0129] As illustrated in Figures 27A, 27B, the layer 26 is opened by etching so as to form openings 260. This etching typically stops on the liner 80. One or more nitride-based plugs may be produced on the grids 50 before etching the layer 26, to protect the metal layers 50 during the etching of this layer 26.

[0130] As illustrated in Figures 28A, 28B, the liner 80 exposed in the openings 260 is removed, selectively to the continuous layer 73 and to the first material of the first layers 10. This removal can be done by wet etching or by isotropic dry etching. This wet etching can be based on a 50% concentrated phosphoric acid H3PO4 solution, carried out at 100°C for a few tens of minutes, for example 30 min. The second openings 200b are thus reformed. The second openings 200b are intended to accommodate the source and drain contacts. They open onto the first layers 10.

[0131] As illustrated in Figures 29A, 29B, the first layers 10 are then completely removed by selective etching with respect to the continuous layer 73, from the second openings 200b. This etching aims to form first spaces 11 in place of the first layers 10. This etching has an isotropic character and can be carried out by wet or dry means, from the second openings 200b.

[0132] As illustrated in Figures 30A, 30B, the layer 40 based on the semiconductor material is then deposited on the continuous layer 73 in the first spaces 11. The deposition of the semiconductor material is here configured so that the layer 40 completely fills the first spaces 11. The portions of the layer 40 located in the first spaces 11 thus have a perfectly controlled thickness, approximately equal to the thickness of the first initial layers. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the sacrificial gates 150 and the second layers 20. This layer 40 is also intended to form the sources 42 and the drains 43 of the GAA transistors directly above the spacers 70 and preferably on the vertical sides of the spacers 70.

[0133] The layer 40 is also typically deposited outside the first spaces 11, on part or all of the sides of the spacers 70. This makes it possible to improve the contact recovery with the sources 42 and the drains 43 of the GAA transistors. The semiconductor material of the layer 40 is advantageously a 2D material, as previously.

[0134] As illustrated in Figures 31 A, 31B, the second openings 200b can then be filled with one or more metal layers 60, for example based on Ti, TiN, W, in order to form the source and drain contacts. Chemical mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M. The tops of the gates 50 are thus exposed.

[0135] A microelectronic device comprising two transistors T1, T2, each comprising four channels 41a, 41b, 41c, 41d stacked along z, with a covering or partially covering gate 50, is thus advantageously obtained. The channels 41a, 41b, 41c, 41d, the sources 42 and the drains 43 are preferably based on a two-dimensional material. Source and drain contacts 60S, 60, 60D electrically connect the channels 41a, 41b, 41c, 41d of these GAA transistors T1, T2.

[0136] In view of the above description, it appears clearly that the proposed method offers a particularly effective solution for forming GAA transistors based on 2D material. This solution is furthermore advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

[0137] According to a possibility not illustrated, the layer 40 based on the semiconductor material does not completely fill the first spaces 11. In this case, the portions of the layer 40 located in the first spaces 11 can be significantly more thinner than the first initial layers. These horizontal portions may have a thickness corresponding to only a few atomic layers, for example between 1 and 5 atomic layers of semiconductor material. This makes it possible to reduce the dimensions of the channels 41 of the GAA transistors. The performance of the GAA transistors can be improved. A dielectric plug is typically formed between the horizontal portions of the layer 40, in order to fill the first spaces 11. This makes it possible to work with a single monolayer of 2D material, which makes it possible to obtain excellent electrostatic control of the device. The gate length can thus be advantageously reduced. This also makes it possible to improve the mechanical strength of the device and / or to avoid deformations of the channels of the GAA transistors, for example by heating during operation. This dielectric plug can be formed by CVD deposition and etching, in a conventional manner.

[0138] Other embodiments are conceivable. The additional spacers of the second embodiment may, for example, be added within the framework of the third embodiment, to form another embodiment. The compatible characteristics of the different embodiments may be combined with each other to form an embodiment which is not necessarily illustrated or described.

Claims

Claims

1. Microelectronic device comprising at least one transistor (T1, T2) comprising: • At least two channels (41a, 41b, 41c) stacked in a main direction (z), each channel being based on a semiconductor material, • a gate (50) called a wrapping gate, completely surrounding at least one of the channels (41a, 41b, 41c), and preferably several channels (41a, 41b, 41c), • a source (42) and a drain (43) on either side of each channel (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and to the drain (43), • a gate dielectric layer (30) separating each channel (41a, 41b, 41c) and the wrapping gate (50), • spacers (70) on either side of the gate (50), configured to electrically isolate the gate (50) from the source and drain contacts (60S, 60, 60D),the device being characterized in that the grid dielectric layer (30) and the spacers (70) are formed by the same continuous layer (73) surrounding the encapsulating grid (50).,

2. Device according to the preceding claim in which said continuous layer (73) has so-called horizontal parts, extending in a plane perpendicular to the main direction (z) and so-called vertical parts, extending in planes parallel to the main direction (z), and in which the gate dielectric layer (30) corresponds to the horizontal parts of the continuous layer (73), and the spacers (70) correspond to the vertical parts of the continuous layer (73).

3. Device according to any one of the preceding claims in which the continuous layer (73) has a substantially constant thickness.

4. Device according to any one of the preceding claims in which the continuous layer (73) comprises a plurality of continuous layers superimposed on each other.

5. Device according to any one of the preceding claims in in which the surrounding grid (50) is common to all the channels (41a, 41b, 41c), said grid having an upper part flanked by additional spacers (170) without continuity with the grid dielectric layer (30).

6. Device according to any one of the preceding claims in which the source (42) and the drain (43) are common to all the channels (41a, 41b, 41c) of the at least one transistor (T1, T2).

7. Device according to any one of the preceding claims in which the semiconductor material of the channels is taken from: - transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te), or - a semiconductor oxide, for example IGZO (Indium-Gallium Zinc Oxide), In2O3, IWO (Tungsten-Doped Indium Oxide), ITO (Indium-Tin Oxide), IAZO (Indium-Aluminum Zinc Oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide, or - graphene, hexagonal boron nitride or phosphorene.

8. A method of manufacturing a microelectronic device according to any one of the preceding claims, said method comprising the following steps: • Providing on a substrate (S) a stack (E) along the main direction (z) comprising a first plurality of first layers (10) made of a first material alternating with a second plurality of second layers (20) made of a second material, the first and second materials being different from said semiconductor material, • Forming in this stack (E) first openings (100) defining first patterns (101M), • Forming sacrificial gates (150) straddling the first patterns (101M) and partly in the first openings (100), • Forming in the first patterns (101M) second openings (200) defining second patterns (102M), • Removing completely, from the second openings (200, 200b),the first material of the first layers (10) so, to form first spaces (11), Remove the sacrificial grids (150) so as to form third openings (300), Completely removing, from the third openings (300), the second material of the second layers (11), so as to form second spaces (21), Depositing a continuous layer (73), based on a dielectric material, around the second layers (20) or in the second spaces (21), so as to form: • A grid dielectric layer (30) from the horizontal parts of the continuous layer (73), • Spacers (70) from the vertical parts of the continuous layer (73), After forming the continuous layer (73), deposit a layer (40) based on a semiconductor material in the first spaces (11), so as to form: • channels (41a, 41b, 41c) based on the semiconductor material, and • sources (42) and drains (43) based on the semiconductor material on either side of the channels (41), After formation of the continuous layer (73), fill the second spaces (21) with a material, called gate material, so as to form gates (50) called wrapping gates completely surrounding at least one of the channels (41a, 41b, 41c) of the at least one transistor (T1, T2).

9. Method according to the preceding claim in which the removal of the sacrificial gates (150) and the removal of the second material from the second layers (20) are carried out after deposition of the layer (40) based on the semiconductor material, and in which the deposition of the continuous layer (73) is carried out around the second layers (20).

10. Method according to the preceding claim in which the removal of the first material of the first layers (10) is carried out selectively to the second material of the second layers (20).

11. A method according to any one of claims 8 to 9 further comprising, before forming the second openings (200), forming additional spacers (170) on the first patterns (101M) and bordering the sacrificial grids (150).

12. A method of manufacturing a microelectronic device according to any one of claims 8 to 11, said method comprising the steps below chained in the following order: • Providing on a substrate (S) the stack (E) in the main direction (z) comprising the first plurality of first layers (10) in a first material alternating with the second plurality of second layers (20) in a second material, the first and second materials being different from the semiconductor material, • Form in this stack (E) the first openings (100) defining the first patterns (101M), • Form the sacrificial grids (150) straddling the first patterns (101M) and partly in the first openings (100), • Form in the first patterns (101M) the second openings (200) defining the second patterns (102M), • Completely remove, from the second openings (200), the first material of the first layers (10) so as to form the first spaces (11), • Deposit the continuous layer (73), based on a dielectric material, around the second layers (20), so as to form: • the grid dielectric layer (30) from the horizontal parts of the continuous layer (73), • the spacers (70) from the vertical parts of the continuous layer (73), • Deposit the layer (40) based on a semiconductor material on the continuous layer (73), in the first spaces (11), so as to form: • the channels (41a, 41b, 41c) based on the semiconductor material, and • the sources (42) and drains (43) based on the semiconductor material on either side of the channels (41), • Remove the sacrificial grids (150) so as to form the third openings (300), • Completely remove, from the third openings (300), the second material of the second layers (11), so as to form the second spaces (21), • Filling the second spaces (21) with the gate material, so as to form the surrounding gates (50) completely surrounding at least one channel (41a, 41b, 41c) of the at least one transistor (Tl, T2).

13. Method according to claim 8 in which the removal of the sacrificial gates (150) and the removal of the second material from the second layers (20) are carried out before deposition of the layer (40) based on the semiconductor material, and in which the deposition of the at least one continuous layer (73) is carried out in the second spaces (21).

14. Method according to the preceding claim further comprising, after formation of the second openings (200), a deposition of at least one retaining layer (80) in said second openings (200), on exposed sides of the first and second layers (10, 20).

15. Method according to the preceding claim further comprising, after filling the second spaces (21) with the grid material, a removal of the at least one retaining layer (80) so as to expose the sides of the first layers (10).

16. Method for manufacturing a microelectronic device according to the preceding claim, said method comprising the steps below linked in the following order: • Providing on a substrate (S) the stack (E) in the main direction (z) comprising the first plurality of first layers (10) in a first material alternating with the second plurality of second layers (20) in a second material, the first and second materials being different from the semiconductor material, • Forming in this stack (E) the first openings (100) defining the first patterns (101M), • Forming the sacrificial gates (150) straddling the first patterns (101M) and partly in the first openings (100), • Forming in the first patterns (101M) the second openings (200, 200b) defining the second patterns (102M), • Forming the holding layer (80) in said second

17.

18. openings (200), on exposed flanks of the first and second layers (10, 20), • Remove the sacrificial grids (150) so as to form the third openings (300), • Completely remove, from the third openings (300), the second material of the second layers (11), so as to form the second spaces (21), • Deposit the continuous layer (73), based on a dielectric material, in the second spaces (21), so as to form: • the grid dielectric layer (30) from the horizontal parts of the continuous layer (73), • the spacers (70) from the vertical parts of the continuous layer (73), • Fill the second spaces (21) with the grid material, so as to form the surrounding grids (50), • Remove the retaining layer (80) so as to expose the sides of the first layers (10), • Completely remove, from the second openings (200b), the first material of the first layers (10) so as to form the first spaces (11), • Deposit the layer (40) based on a semiconductor material on the continuous layer (73), in the first spaces (11), so as to form: • the channels (41a, 41b, 41c) based on the semiconductor material, and • the sources (42) and drains (43) based on the semiconductor material on either side of the channels (41). Method according to any one of claims 8 to 16 in which the deposition of the layer (40) based on the semiconductor material is carried out by chemical vapor deposition or by atomic layer deposition. Method according to any one of claims 8 to 17 in which the semiconductor material is a two-dimensional (2D) material chosen from the dichalcogenides of transition metals MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

19. A method according to any one of claims 8 to 18 wherein the formation of the sacrificial grids (150) is carried out in such a way that the sacrificial grids (150) extend over an entire height of the first openings (100).

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