NFC demodulation circuit

Abstract

NFC Demodulation Circuit This description relates to an amplification circuit comprising an amplifier circuit (210) including an operational amplifier (212) configured to amplify a signal to be demodulated and comprising a feedback loop (214) whose resistance value varies discretely as a function of the level of an output node (NVAOP) of said amplifier circuit (210) relative to one or more thresholds (VREFP1, VREFN1, VREFP2, VREFN2) defining one or more non-saturation operating ranges of the amplifier circuit (210). Figure for the abbreviation: Fig. 4

Description

Title of the invention: NFC demodulation circuit Technical field

[0001] This description relates generally to demodulation circuits, in particular demodulation circuits for near field communication such as the NFC (Near Field Communication) protocol. Prior art

[0002] In wireless communication devices, particularly near-field communication devices, various types of modulation consist of amplitude modulation of the radio frequency signal. Two types of demodulation chains are commonly used: level detectors and rising or falling edge detectors, both types including amplifiers. In near-field communication devices, variations in signal amplitude can be significant and lead to saturation of these demodulation chains. This results, for example, inaccuracies in determining certain parameters of the communication protocol used. Summary

[0003] There is a need to limit the saturation of the demodulation chains and to improve the detection of certain communication protocol parameters.

[0004] An embodiment overcomes all or part of the drawbacks of known demodulation circuits.

[0005] An embodiment provides for an amplification circuit comprising an amplifier circuit including an operational amplifier and configured to amplify a signal to be demodulated and comprising a feedback loop whose resistance value varies discretely as a function of a level of an output node of said amplifier circuit relative to one or more thresholds defining one or more non-saturation operating ranges of the amplifier circuit.

[0006] One embodiment provides a demodulation circuit comprising an amplification circuit as described above.

[0007] According to one embodiment, the resistance value of the feedback loop of the amplifier circuit takes a first value when said level is greater than a first threshold or when said level is less than a second threshold less than the first threshold.

[0008] According to one embodiment, the resistance value of the feedback loop of the amplifier circuit takes a second value when said level is between the first and second threshold.

[0009] According to one embodiment, the resistance value of the feedback loop of the amplifier circuit takes a third value when said level is greater than a third threshold greater than the first threshold or when said level is less than a fourth threshold less than the second threshold.

[0010] According to one embodiment, the operational amplifier comprises an inverting input connected: - to an input node of the amplifier circuit, and - to the output node of the amplifier circuit via the feedback loop.

[0011] According to one embodiment, said feedback loop comprises: - a first branch connecting the inverting input of the operational amplifier to the output node and formed of a resistive element having the first resistance value; - N additional branches, in parallel with the first branch, each formed of a resistive element in series with a switch controlled by a respective control signal, said respective control signal being dependent on a comparison between the level of the output node of said amplifier circuit and a respective operating range among N non-saturation operating ranges of the amplifier circuit, each operating range being defined by thresholds, N being a positive integer; and - N comparison circuits configured to generate the respective control signal for each of the N additional branches so as to make the respective switch: - passing when the output node level of the amplifier circuit is within the respective operating range; and - not passing when the level of the output node of the amplifier circuit is outside said respective operating range.

[0012] According to one embodiment the non-saturation operating range of rank N=1 is defined as being between the first threshold and the second threshold; and the branch of rank N=1 is formed of a resistive element having a fourth resistance value.

[0013] According to one embodiment, the non-saturation operating range of rank N=2 is defined between the third and fourth thresholds; and the branch of rank N=2 is formed of a resistive element having a fifth resistance value.

[0014] According to one embodiment, a first comparison circuit among the N comparison circuits comprises: - a first comparison branch comprising a comparator circuit having a non-inverting input connected to the output node and an inverting input connected to a node configured to receive a voltage representing the first threshold; - a second comparison branch comprising a comparator circuit, having a non-inverting input connected to the output node and an inverting input connected to a node configured to receive a voltage representing the second threshold, in series with an inverting circuit; and - a logic block configured to perform an OR function from a signal present on an output node of the comparator circuit of the first branch of the first comparison circuit and another signal present on an output node of the inverter circuit of the second branch of the first comparison circuit; an output of the logic block being the control signal of the switch of the branch of the feedback loop of rank N=l.

[0015] According to one embodiment, a second comparison circuit among the N comparison circuits comprises: - a third comparison branch comprising a comparator circuit having a non-inverting input connected to the output node and an inverting input connected to a node configured to receive a voltage representative of the third threshold; - a fourth comparison branch comprising a comparator circuit, having a non-inverting input connected to the output node and an inverting input connected to a node configured to receive a voltage representing the fourth threshold, in series with another inverting circuit; and - another logic block configured to perform an OR function from a signal present on an output node of the comparator circuit of the third branch of the second comparator circuit and another signal present at the output of the inverter circuit of the fourth branch of the second comparator circuit; an output of said logic block being the control signal of the switch of the branch of the feedback loop of rank N=2.

[0016] According to one embodiment, the amplification circuit or the demodulation circuit further comprises a flip-flop of which: - an initialization input is connected to the output node of the comparator circuit of the first branch of the first comparison circuit; - a reset input is connected to the output node of the inverter circuit of the second branch of the first comparator circuit; and - an output is connected to an output node of the amplification circuit via an inverter circuit.

[0017] According to one embodiment, the inverting input of the operational amplifier is connected to the input node of the amplifier circuit via a capacitor in series with an input resistance.

[0018] According to one embodiment, the demodulation circuit is of the NFC type.

[0019] One embodiment provides for a near-field communication device including the demodulation circuit as described above. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following non-limiting description of particular embodiments in relation to the accompanying figures, among which:

[0021] the [Fig.1] a schematic view of a communication system comprising a first and a second near field communication devices;

[0022] [Fig.2] schematically represents an example of a demodulation circuit of a device of [Fig.1];

[0023] [Fig.3] represents a timing diagram of the operation of the circuit of [Fig.2];

[0024] [Fig.4] schematically represents an example of a demodulation circuit of a device of [Fig.1] according to one embodiment;

[0025] [Fig.5] represents a timing diagram of the operation of the circuit of [Fig.4];

[0026] [Fig.6] schematically represents an example of a demodulation circuit for the device of [Fig.1] according to another embodiment;

[0027] [Fig.7] represents a timing diagram of the operation of the circuit of [Fig.6]. Description of the embodiments

[0028] The same elements have been designated by the same thresholds in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same thresholds and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0030] Unless otherwise specified, when a threshold is set for two elements connected together, this means directly connected without intermediate elements other than conductors, and when a threshold is set for two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected via one or more other elements.

[0031] In the following description, when thresholds are applied to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., a threshold is applied unless otherwise specified in the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0033] Fig. 1 represents a schematic view of a communication system comprising a first 102 (Terminal) and a second 104 (Smart card) near field communication devices.

[0034] In the following description, a near-field communication device is defined as an electronic device incorporating at least one near-field communication circuit implementing protocols from the NFC forum (“Near-Field Communication” - NFC) or protocols for contactless systems complying with the ISO 14443 standard. Near field is understood to mean an electromagnetic field of limited range from a few centimeters to about 2 meters depending on the protocols used.

[0035] The first device 102 is, for example, in card reader mode and the second device 104 in card mode. The first device 102 is, for example, configured to activate the second device 104 by emitting a modulated magnetic field with the return reading of another modulated radio frequency signal containing information from the card.

[0036] The first and second devices 102, 104 each include, for example, a demodulation circuit 106, 108 for demodulating signals from the other device.

[0037] The type of modulation used by these devices to communicate via radio frequency is, for example, 1-bit amplitude modulation. Various encodings, such as modified Miller, Manchester, or NRZ, can also be used, as well as a modulation rate, for example, from a few percent to 100%. The exchanged signals can also take different forms to facilitate the detection of rising or falling edges. The amplitude of the radio frequency field received by the second device 104 can vary significantly, for example, depending on the distance separating them or on the output level of the first device 102.

[0038] The demodulation circuits 106, 108 are for example of the level detection or edge detection type.

[0039] Level detectors compare the signal with a threshold. When the signal exceeds the threshold, a high level is detected, and when the signal falls below the threshold, a low level is detected.

[0040] Front detectors use, for example, the comparison of the derivative of the signal with respect to two high and low thresholds.

[0041] Fig. 2 schematically represents an example of a demodulation circuit 206 of a device 102, 104 of Fig. 1.

[0042] In the example shown, the demodulation circuit 206 includes at its input a high-pass radio frequency filter composed of a capacitor Cl in series with a resistor RL. This filter allows, for example, a derivative of the incoming signal RF_IN. The filter connects an input node (NI) of the circuit to an input node (NVIN) of an amplifier circuit 210. The input node NI is configured to receive a The RF_IN radio frequency signal is to be demodulated. The amplifier circuit 210 includes an operational amplifier 212 with an inverting input (labeled -) connected, preferably connected, to the input node NVIN. A non-inverting input (labeled +) is configured to be connected, preferably connected, to a supply rail with a voltage Vcm. The input node NVIN is connected, preferably connected, to an output node (NVAOP) of the amplifier circuit 210 via a feedback loop 214. The feedback loop 214 comprises a first branch and a second branch in parallel, both connecting the output node NVAOP to the input node NVIN. The first branch includes a switch 216 controlled by a first gain control signal (GainCtrll). The second branch includes a resistor (R2). The ratio between the resistances R2 and RI sets the gain of the amplifier circuit 210.

[0043] In the example shown, the demodulation circuit 206 further includes a first signal level comparison circuit 250. The first comparison circuit 250 includes a first branch connecting the NVAOP node to a node N2 and a second branch connecting the NVAOP node to another node N3. The first branch includes a voltage comparator circuit 220. The comparator circuit 220 includes an operational amplifier 222, an inverting input of which (denoted -) is configured to be connected, preferably connected, to a voltage rail VREFP1 defining a first threshold. The operational amplifier 222 includes a non-inverting input (denoted +) configured to be connected, preferably connected, to the NVAOP node. An output of the amplifier 222 is connected, preferably connected, to the node N2. When the signal level at the NVAOP node is greater than VREFP1, then the amplifier 222 returns a high-level signal to the node N2.Otherwise, a low-level signal is sent back to node N2.

[0044] In the example shown, the second branch of the first comparator circuit 250 includes a voltage comparator circuit 230. The comparator circuit 230 includes an operational amplifier 232, an inverting input of which (noted -) is configured to be connected, preferably connected, to a voltage rail VREFN1 defining a second threshold. The operational amplifier 232 further includes a non-inverting input (noted +) configured to be connected, preferably connected, to the NVAOP node. An output of the amplifier 232 is connected to the N3 node via an inverting circuit 240. When the signal level at the NVAOP node is greater than VREFN1, the amplifier 232 returns a high-level signal, which becomes low at the N3 node after inversion. Otherwise, a high-level signal is returned to the N3 node.

[0045] The two thresholds VREFP1 and VREFN1 define a zone between them where the amplifier circuit 210 is not saturated. Above VREFP1 and below VREFN1, the For example, the amplifier circuit is in saturation.

[0046] In the example shown, the demodulation circuit 206 further includes a logic circuit 280 configured to perform an "OR" operation on the signals present at nodes N2 and N3. The resulting signal is the GainCtrll control signal. When the signal at node NVAOP is greater than VREFP1 and VREFN1, then the GainCtrll signal is high. When the signal at node NVAOP is less than VREFP1 but greater than VREFN1, then the GainCtrll signal is low. And when the signal at node NVAOP is less than VREFP1 and less than VREFN1, then the GainCtrll signal is high. When the GainCtrll signal is high, this implies, for example, that switch 216 is conducting, and when the GainCtrll signal is low, this implies, for example, that switch 216 is not conducting.When switch 216 is not conducting, this implies that the gain of amplifier circuit 210 is R2 / R1, and when switch 216 is conducting, this implies that the gain of amplifier circuit 210 is zero, i.e., that node NVIN is directly connected to node NVAOP.

[0047] In the example shown, the demodulation circuit 206 further includes a flip-flop 260 of which an initialization input (S) is connected to node N2, a reset input (R) is connected to node N3; and an output (Q) is connected to an output node (NVOUT) of the demodulation circuit via an inverter circuit 270.

[0048] The circuit in [Fig.2] allows automatic control of the signal amplification gain (AGC, Automatic Gain Control) by automatically and discreetly varying the gain from a zero value (case where switch 216 is closed, i.e. conducting) to a value R2 / R1 (case where switch 216 is open, i.e. not conducting) and this as a function of the signal level of the NVAOP node with respect to the references VREFP1 and VREFN1.

[0049] Figure 3 represents a timing diagram of the operation of the circuit of Figure 2. More specifically, Figure 3 represents the input signal RF_IN, the voltage VAOP at the NVAOP node, as well as the GainControl and VOUT signals.

[0050] Between a time tl and a time t2 later than tl, the received RF_IN signal increases linearly.

[0051] Between time t2 and a time t3 later than t2, the RF_IN signal stabilizes at a high level. The VAOP signal is located between the voltage levels NVREFP1 and NVREFN1, which implies that the GainCtrll signal is at a low level, for example 0, and the gain is in this case high (Strong gain) and proportional to R2 / R1. During this time period, the VOUT signal remains stable since there is no change in the RF_IN signal.

[0052] Between time t3 and a time t4 later than t3, the RF_IN signal decreases linearly. Just after time t3, the VAOP signal rises abruptly and exceeds the voltage The VREFP1 threshold is reached. The GainCtrll signal then goes high, automatically setting the gain to zero (Gain=0) and causing the VOUT signal to go low. Amplifier 212 is then short-circuited, and the output voltage tends towards the common mode between VREFP1 and VREFNL. The VAOP signal then decreases linearly until it falls below the VREFPL threshold voltage. At this point, the GainCtrll signal returns to a low level. As the RF_IN signal continues to decrease, the VAOP signal, which is again amplified with the ratio R2 / R1, rises linearly until it again exceeds the VREFPL threshold. When this threshold is exceeded, the GainCtrll signal goes high, causing VAOP to decrease again, and so on. The VAOP signal therefore oscillates in a sawtooth pattern around the VREFP1 threshold value, and the GainCtrll signal alternates between high and low levels accordingly.

[0053] Between time t4 and a time t6 later than t4, the RF_IN signal rises linearly. The VOUT signal remains at a low level as long as the VAOP signal does not fall below the VREFNL threshold

[0054] Between time t4 and a time t5 located between time t4 and time t6, the VAOP signal crosses above the VREFP1 threshold one last time before falling below the VREFP1 threshold between time t5 and time t6, while remaining above VREFNL.

[0055] Between time t5 and time t6, the GainCtrll signal goes low and remains low until the VAOP signal falls below the VREFN1 threshold at time t6. The VOUT signal then goes from low to high. The variations of the RF_IN signal are thus digitized.

[0056] The period (Signal Delay) between time t5 and time t6 corresponds to a detection delay in the signal variation. This is due to the fact that the variations in the VAOP signal are not visible when amplifier 212 is short-circuited. The determination of the frame delay time (FDT), which is a fundamental parameter of the NFC and ISO 14443 protocols, is therefore impaired. Another drawback of the example in [Fig. 2] stems from the fact that when amplifier 212 is short-circuited, it generates a signal discontinuity and the stability of the circuit is affected.

[0057] The described embodiments propose an NFC demodulation circuit comprising an amplifier circuit configured to amplify a signal to be demodulated with a gain, other than zero, the value of which varies discretely as a function of a level of the output node of the amplifier circuit relative to one or more thresholds defining one or more non-saturation operating ranges of the amplifier.

[0058] Fig. 4 schematically represents an example of a demodulation circuit 406 of one of the devices 102, 104 of Fig. 1 according to one embodiment.

[0059] In the example shown, the demodulation circuit 406 is similar to the circuit of Demodulation 206 of [Fig. 2] except that an additional resistor R2b is added to the first branch of the feedback loop 214 so as to connect switch 216 with the NVAOP node or so as to connect switch 216 with the NVIN node. Resistor R2b allows a different non-zero gain level for the amplifier circuit 210 than that obtained with the branch containing resistor R2.

[0060] Unlike the example in [Fig. 2], the amplifier 210 is not short-circuited when the switch 216 is controlled to be conductive. The gain of the amplifier circuit 210 thus varies discretely between R2 / R1 when the NVAOP signal is between VREFP1 and VREFN1, and (R2b.R2) / (R1(R2+R2b)) when the NVAOP signal is above VREFP1 or below VREFN1.

[0061] In the example of [Fig.4], the gain area defined between VREFP1 and VREFN1 is an off-saturation area of ​​the amplifier 212 corresponding to a high gain and the areas above VREFP1 and below VREFN1 are off-saturation areas of the amplifier 212 corresponding to a lower but non-zero gain.

[0062] Fig. 5 represents a timing diagram of the operation of the circuit of Fig. 4.

[0063] In particular, [Fig.5] represents RF_IN, VAOP, GainCtrll and VOUT.

[0064] Before a time t' 1, the RF_IN signal is at a high level, the VAOP signal is stable and located between VREFP1 and VREFN1, Gaintrll is in a low state (G=high) and the output VOUT is in a high state.

[0065] From a time t'1, the RF_IN signal decreases with a first slope up to a time t'2. The RF_IN signal then decreases up to a time t'3 with a lower slope.

[0066] Between times t'1 and t'2, the VAOP signal passes above the VREFP1 threshold, which places GainCtrll at a high level (G=low) and VOUT goes to a low level.

[0067] Between times t'2 and t'3, the VAOP signal remains above the VREFP1 threshold, which places GainCtrll at a high level (G=low), and VOUT remains at a low level.

[0068] At time t'3 and up to a time t'5, the RF_IN signal changes direction and increases li negligence.

[0069] Between time t'3 and a time t'4, the VAOP signal drops until it falls below the VREFP1 threshold, which causes the GainCtrll signal to go low.

[0070] Between time t'4 and time t'5, the VAOP signal continues to decrease and the GainCtrll signal remains in a low state.

[0071] At time t'5, the VAOP signal passes below the VREFN1 threshold, which causes the GainCtrll and VOUT signals to switch to a high state.

[0072] After time t'5, the RF_IN signal stabilizes at a high state, the VAOP signal rises and passes above VREFN1 at a time t'6 which causes GainCtrll to go low.

[0073] The example in [Fig.4] allows for the formation of a hysteresis where the output signal VOUT changes state only after the two thresholds VREFP1 and VREFN1 have been crossed in one direction or the other.

[0074] When the GainCtrll signal is at a low level, the gain is high (High Gain) to increase sensitivity. When the GainCtrll signal is at a high level, the gain is low (Low Gain) to limit the output dynamic range and prevent saturation of amplifier 212 while maintaining a certain level of gain to allow detection of signal variations. In other words, using a non-zero gain in the region where GainCtrll is at a high level prevents saturation while increasing the accuracy of signal variation detection.

[0075] In the example of [Fig.5], the thresholds VREFP1 and VREFN1 define an off-saturation operating range of the amplifier 212, but values ​​slightly above VREFP1 and slightly below VREFN1 also define off-saturation operation thanks to the action of the non-zero gain.

[0076] Fig. 6 schematically represents an example of a demodulation circuit for the device of Fig. 1 according to another embodiment.

[0077] The demodulation circuit 606 of [Fig. 6] is similar to that of [Fig. 4] except that the feedback loop 214 of the amplifier circuit 210 includes a third branch comprising a switch 616, controlled by a signal (GainCtrl2), in series with a resistor (R2c). The third branch connects the NVIN node to the NVAOP node. The resistor R2c provides a different gain level than the gains obtained with the branches comprising resistors R2 and R2b when they are respectively activated.

[0078] The demodulation circuit 606 of [Fig. 6] also differs from that of [Fig. 4] in that the demodulation circuit 206 further includes a second signal level comparator circuit 650. The second comparator circuit 650 includes a third branch connecting the NVAOP node to an input of a logic circuit 680 configured to perform the "OR" function. The second comparator circuit 650 includes a fourth branch connecting the NVAOP node to another input of the logic circuit 680. The third branch includes a voltage comparator circuit 620. The comparator circuit 620 includes an operational amplifier 622, an inverting input of which (denoted -) is configured to be connected, preferably connected, to a voltage rail VREFP2 higher than VREFP1 and defining a third threshold. The 622 operational amplifier further includes a non-inverting input (noted +) configured to be connected, preferably connected, to the NVAOP node.An output of the 622 amplifier is connected, preferably connected, to one of the inputs of the 680 logic circuit. When the signal level on the NVAOP node is greater than VREFP2 then the 622 amplifier returns a high-level signal on . this input of the 680 logic circuit. Otherwise, a low-level signal is returned.

[0079] In the example shown, the fourth branch of the second comparator circuit 650 includes a voltage comparator circuit 630. The comparator circuit 630 includes an operational amplifier 632, an inverting input of which (noted -) is configured to be connected, preferably connected, to a voltage rail VREFN2, lower than VREFN1 and defining a fourth threshold. The operational amplifier 632 further includes a non-inverting input (noted +) configured to be connected, preferably connected, to the NVAOP node. An output of the amplifier 632 is connected to another of the inputs of the logic circuit 680 via an inverter circuit 640. When the signal level at the NVAOP node is below the threshold VREFN2, the amplifier 632 returns a high-level signal, which becomes low at the input of the logic circuit 680 after inversion. Otherwise, a low-level signal is returned.The output of the 680 logic circuit is the GainCtrl2 control signal.

[0080] Fig. 7 represents a timing diagram of the operation of the circuit of Fig. 6.

[0081] The operation of the circuit in [Fig. 6] is similar to that of [Fig. 4] except that, when the VAOP signal exceeds the thresholds VREFP1 and VREFP2, or falls below the thresholds VREFN1 and VREFN2, switch 616 is activated by the GainCtrl2 signal and the gain of the amplifier circuit 210 becomes equal to (R2b.R2.R2c) / (Rl((R2.R2c)+(R2b.R2c)+(R2b.R2))). As the VAOP signal crosses successive thresholds, its slope is attenuated by the discrete reduction of the gain of the amplifier circuit 210 in order to remain in a non-saturation operating range.

[0082] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, although the examples in Figures 4 and 6 notably represent a feedback loop 214 with two and three branches respectively, it is possible for those skilled in the art to implement more branches in parallel, each comprising a switch and a resistor. The switch of each of these additional branches will be controlled by a signal resulting from the comparison of the VAOP signal with one or more thresholds. In this case, other supplementary comparator circuits, such as circuits 220, 230, 620, and 630, can be implemented and associated with one or more logic circuits such as circuits 280 or 680.

[0083] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, with regard to the 260 type of rocker switch or other types of Flip-flops can be used instead of flip-flop 260. A person skilled in the art can also implement comparator circuits 220, 230, 620, and 630, depending on their knowledge. Furthermore, a person skilled in the art can implement the feedback loop 214 in a different way, provided that its resistance varies discretely, while remaining non-zero, according to thresholds.

[0084] A person skilled in the art will be able to implement the demodulation circuits described for types of radio frequency communications other than NFC type.

Claims

Claims

1. Amplification circuit comprising an amplifier circuit (210) comprising an operational amplifier (212) and configured to amplify a signal to be demodulated and comprising a feedback loop (214) of which a resistance value varies discretely as a function of a level of an output node (NVAOP) of said amplifier circuit (210) with respect to one or more thresholds (VREFP1, VREFN1, VREFP2, VREFN2) defining one or more operating ranges outside saturation of the amplifier circuit (210).

2. A demodulation circuit (406, 606) comprising an amplification circuit according to claim 1.

3. Amplification circuit according to claim 1 or demodulation circuit according to claim 2, wherein the resistance value of the feedback loop (214) of the amplifier circuit (210) takes a first value when said level is greater than a first threshold (VREFP1) or when said level is less than a second threshold (VREFN1) less than the first threshold (VREFP1).

4. Amplification circuit or demodulation circuit according to claim 3, in which the resistance value of the feedback loop (214) of the amplifier circuit (210) takes a second value when said level is between the first (VREFP1) and the second threshold (VREFN1).

5. Amplification circuit or demodulation circuit according to claim 4, in which the resistance value of the feedback loop (214) of the amplifier circuit (210) takes a third value when said level is greater than a third threshold (VREFP2) greater than the first threshold (VREFP1) or when said level is less than a fourth threshold (VREFN2) less than the second threshold (VREFN1).

6. Amplification circuit according to one of claims 1 or 3 to 5, or demodulation circuit according to one of claims 2 to 5, in which the operational amplifier (212) comprises an inverting input connected: - to an input node (NVIN) of the amplifier circuit (210), and - to the output node (NVAOP) of the amplifier circuit (210) via the feedback loop (214).

7. Amplification circuit or demodulation circuit according to claim- dication 6 in its dependence on claim 3, wherein said feedback loop (214) comprises: - a first branch connecting the inverting input of the operational amplifier (212) to the output node (NVAOP) and formed of a resistive element (R2) having the first resistance value; - N additional branches, in parallel with the first branch, each formed of a resistive element in series with a switch controlled by a respective control signal, said respective control signal being dependent on a comparison between the level of the output node (NVAOP) of said amplifier circuit (210) with respect to a respective operating range among N operating ranges without saturation of the amplifier circuit (210), each operating range being defined by thresholds, N being a positive integer;and - N comparison circuits configured to generate the respective control signal of each of the N additional branches so as to make the respective switch: - passing when the level of the output node (NVAOP) of the amplifier circuit (210) is included in the respective operating range; and - not passing when the level of the output node (NVAOP) of the amplifier circuit is outside said respective operating range.;

8. Amplification circuit or demodulation circuit according to claim 7 in its dependence on claim 3, in which: - the operating range without saturation of rank N=1 is defined between the first threshold (VREFP1) and the second threshold (VREFN1); and - the branch of rank N=1 is formed of a resistive element (R2b) having a fourth resistance value.

9. Amplification circuit or demodulation circuit according to claim 8 in its dependence on claim 5, in which: - the non-saturation operating range of rank N=2 is defined between the third and fourth thresholds (VREFP2, VREFN2); and - the branch of rank N=2 is formed of a resistive element (R2c) having a fifth resistance value.

10. A demodulation circuit according to claim 8 or 9, wherein a first comparison circuit (250) among the N comparison circuits comprises: - a first comparison branch (220) comprising a comparator circuit (222) having a non-inverting input connected to the output node (NVAOP) and an inverting input connected to a node (NVREFP1) configured to receive a voltage representing the first threshold (VREFP1); - a second comparison branch comprising a comparator circuit (230), having a non-inverting input connected to the output node (NVAOP) and an inverting input connected to a node (NVREFN1) configured to receive a voltage representing the second threshold (VREFN1), in series with an inverter circuit (240); and - a logic block (280) configured to perform an OR function from a signal present on an output node (N2) of the comparator circuit (222) of the first branch (220) of the first comparison circuit (250) and another signal present on an output node (N3) of the inverter circuit (240) of the second branch (230) of the first comparison circuit (250); an output of the logic block (280) being the control signal (GainCtrll) of the switch (216) of the branch of the feedback loop (214) of rank N=1.

11. Amplification circuit or demodulation circuit according to claim 10 in dependence on claim 5, in which a second comparison circuit (650) among the N comparison circuits comprises: - a third comparison branch (620) comprising a comparator circuit (622) having a non-inverting input connected to the output node (NVAOP) and an inverting input connected to a node (NVREFP2) configured to receive a voltage representing the third threshold (VREFP2); - a fourth comparison branch (630) comprising a comparator circuit (632), having a non-inverting input connected to the output node (NVAOP) and an inverting input connected to a node (NVREFN2) configured to receive a voltage representing the fourth threshold (VREFN2), in series with another inverting circuit (640); and - another logic block (680) configured to perform an OR function from a signal present on an output node of the comparator circuit (622) of the third branch (620) of the second comparison circuit (650) and another signal present at the output of the inverting circuit (640) of the fourth branch (630) of the second comparison circuit (650); an output of said logic block (680) being the control signal (GainCtrl2) of the switch (616) of the branch of the feedback loop (214) of rank N=2.

12. Amplification circuit or demodulation circuit according to claim 10 or 11, further comprising a flip-flop (260) of which: - an initialization input (S) is connected to the output node (N2) of the comparator circuit (222) of the first branch of the first comparison circuit; - a reset input (R) is connected to the output node (N3) of the inverter circuit (240) of the second branch of the first comparison circuit; and - an output (Q) is connected to an output node (NVOUT) of the amplification circuit via an inverter circuit (270).

13. Amplification circuit or demodulation circuit according to any one of claims 6 to 12, wherein the inverting input of the operational amplifier (212) is connected to the input node (NVIN) of the amplifier circuit (210) via a capacitor (Cl) in series with an input resistance (RI).

14. Demodulation circuit according to any one of claims 2 to 13 in which the demodulation circuit is of the NFC type.

15. A near field communication device comprising the demodulation circuit according to any one of claims 2 to 14.

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