Correction circuit for bandgap circuit

Abstract

Correction circuit for bandgap circuit The present description relates to a correction circuit (CORR) for a bandgap circuit (1) comprising a first bipolar transistor (Q1) and a second bipolar transistor (Q1, Q2), the bandgap circuit being configured to provide a continuous and temperature-stable voltage (Vref) from the first and second bipolar transistors (Q1, Q2), the correction circuit being configured to generate a correction current (Icorr) equal to a base current difference (Ib1, Ib2) of said first and second transistors (Q1, Q2), and inject the correction current (Icorr) on the emitter of one of said first and second bipolar transistors (Q1) so as to correct an error on the temperature-stable voltage (Vref) resulting from a current gain difference between said first and second bipolar transistors (Q1, Q2). Figure for abstract: Fig. 3

Description

Title of the invention: Correction circuit for bandgap circuit Technical field

[0001] The present description relates generally to electronic circuits, for example integrated, and, more particularly, to bandgap electronic circuits and electronic devices comprising such bandgap electronic circuits for generating a temperature-stable DC voltage. Prior art

[0002] Known bandgap circuits comprise at least two bipolar transistors which receive equal currents on their respective collectors. The two bipolar transistors are of the same type, for example NPN, and have their bases interconnected with each other. Furthermore, one of the two bipolar transistors is P times larger than the other, P being a positive number and greater than 1, that is to say, for example, that the dimensions of the collector, emitter and base regions of this bipolar transistor are P times larger than those of the collector, emitter and base regions of the other bipolar transistor. For example, the transistor which is P times larger than the other corresponds to the paralleling of P transistors each identical to the transistor which is P times smaller than the other.

[0003] The difference between the base-emitter voltages of these two transistors, that is to say the voltage equal to the base-emitter voltage of the smaller of the two transistors minus the base-emitter voltage of the larger of these two transistors, is then of the PTAT type (from the English "Proportional To Absolute Temperature" - proportional to the absolute temperature).

[0004] Since the base-emitter voltage of a bipolar transistor is also of the CTAT type (from the English "Complementary To Absolute Temperature" - complementary to the absolute temperature), by suitably dimensioning the bandgap circuit, a temperature-stable voltage can be obtained from the difference in base-emitter voltage of the two bipolar transistors, and from the base-emitter voltage of one of these two bipolar transistors or of another bipolar transistor of the bandgap circuit.

[0005] However, known bandgap circuits have various drawbacks which it would be desirable to overcome. Summary of the invention

[0006] There is a need to overcome all or part of the disadvantages of electrical circuits- Known bandgap circuits, and known devices comprising known bandgap circuits for generating a temperature-stable voltage, or reference voltage.

[0007] For example, in bandgap circuits of the type described above, for example implemented in FinFet technology, the value of the temperature-stable voltage provided by the bandgap circuit may be different from a theoretical value for which the bandgap circuit has been sized.

[0008] One embodiment overcomes all or part of the drawbacks of known bandgap electronic circuits, and of known devices comprising known bandgap circuits for generating a temperature-stable voltage.

[0009] For example, one embodiment overcomes all or part of the drawbacks of known bandgap electronic circuits using the base-emitter voltage difference of bipolar transistors, for example of the NPN type, for example implemented in FinFet technology.

[0010] One embodiment provides a correction circuit for a bandgap circuit comprising a first bipolar transistor and a second bipolar transistor, the bandgap circuit being configured to provide a continuous and temperature-stable voltage from a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor, the correction circuit being configured to: generating a correction current equal to a difference between a base current of one of said first and second transistors and a base current of the other of said two transistors; and injecting the correction current into the emitter of one of said first and second bipolar transistors so as to correct an error on a temperature-stable voltage value resulting from a difference in current gain between said first and second bipolar transistors.

[0011] Another embodiment provides a device for generating a continuous and temperature-stable voltage, the device comprising: a bandgap circuit comprising a first bipolar transistor and a second bipolar transistor and being configured to provide a continuous and temperature-stable voltage from a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor; and the correction circuit as described above.

[0012] According to one embodiment: the first bipolar transistor has smaller dimensions than the second bipolar transistor; the first and second bipolar transistors have their bases connected to each other and their transmitters coupled to a first node for applying a reference potential; and the bandgap circuit includes: - a first MOS transistor having a source connected to a second node configured to receive a supply potential and a drain coupled, preferably connected, to the collector of the first bipolar transistor, and - a second MOS transistor identical to the first MOS transistor and having a source connected to the second node, a drain coupled, preferably connected, to the collector of the second bipolar transistor and a gate connected to the gate of the first MOS transistor, the first and second MOS transistors being configured to provide a first current to the first bipolar transistor and a second current equal to the first current to the second bipolar transistor.

[0013] According to one embodiment, the bandgap circuit comprises: a first resistor connected between the emitter of the first bipolar transistor and the emitter of the second bipolar transistor; and a second resistor connected between the emitter of the first bipolar transistor and the first node.

[0014] According to one embodiment, the bandgap circuit comprises: a first resistor connected between the emitter of the first bipolar transistor and the first node; a second resistor connected between the emitter of the second bipolar transistor and the first node; an additional bipolar transistor having its collector connected to the second node; an additional MOS transistor having its drain connected to the base of the additional bipolar transistor and coupled to the second node by a current source, its gate connected to the collector of the second bipolar transistor and its source connected to the first node; a capacitor coupling the drain and gate of the additional MOS transistor; and a third resistor connected between the emitter of the second bipolar transistor and the emitter of the additional bipolar transistor.

[0015] According to one embodiment, the correction circuit is configured to inject the correction current into the connection node of the first resistor to the first bipolar transistor.

[0016] According to one embodiment, the correction circuit comprises: a third MOS transistor and third bipolar transistor in series between the first and second nodes; a fourth MOS transistor and fourth bipolar transistor in series between the first and second nodes; a sixth MOS transistor having its gate connected to the connection node of the third MOS transistor to the third bipolar transistor, its source connected to the base of the third bipolar transistor and its drain connected to a third node; a seventh MOS transistor having its gate connected to the connection node of the fourth MOS transistor to the fourth bipolar transistor, its source connected to the base of the fourth bipolar transistor and its drain connected to a fourth node; a MOS transistor current mirror coupling the third and fourth nodes; and a voltage source coupling the third or fourth node to an output of the correction circuit configured to provide the correction current.

[0017] According to one embodiment: the third MOS transistor is identical to the first MOS transistor; the third bipolar transistor is identical to the first bipolar transistor; the fourth MOS transistor is identical to the second MOS transistor; the fourth bipolar transistor is identical to the second bipolar transistor; and a current ratio of the current mirror is equal to 1.

[0018] According to one embodiment: the third MOS transistor is identical to the first MOS transistor; the third bipolar transistor is identical to the first bipolar transistor; the fourth MOS transistor is N times smaller than the second MOS transistor, with N a number strictly greater than 1, for example equal to 2; the fourth bipolar transistor is N times smaller than the second bipolar transistor; and the current mirror comprises two MOS transistors having an aspect ratio N between them.

[0019] According to one embodiment: the voltage source couples the third node to the output; and the current mirror is configured to supply the third node with a current determined by the base current of the fourth bipolar transistor.

[0020] According to one embodiment, the output of the correction circuit is connected to the emitter of the first bipolar transistor.

[0021] According to one embodiment, the first and second bipolar transistors are of the NPN type.

[0022] According to one embodiment, the transistors are implemented in FinFet technology. Brief description of the drawings

[0023] These and other features and advantages will be set forth in detail in the following description of particular embodiments made without limitation in relation to the attached figures among which:

[0024] [Fig.l] illustrates an example of a bandgap circuit;

[0025] [Fig.2] illustrates another example of a bandgap circuit;

[0026] [Fig.3] represents an embodiment of an electronic device comprising the bandgap circuit of [Fig.l] and an embodiment of a correction circuit;

[0027] [Fig.4] represents an embodiment of implementing the correction circuit of [Fig.3]; and

[0028] [Fig.5] represents an embodiment of an electronic device comprising the bandgap circuit of [Fig.2] and an embodiment of a correction circuit. Description of the embodiments

[0029] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the usual electronic applications and systems, for example an electronic power on reset (POR) system, in which a bandgap circuit or a reference voltage generation device comprising a bandgap circuit can be provided have not been detailed, these usual electronic applications and systems being compatible with the described embodiments and variants.

[0031] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0034] [Fig.l] illustrates an example of a bandgap circuit 1.

[0035] Circuit 1 comprises two bipolar transistors Q1 and Q2. Circuit 1 is configured to provide a temperature-stable DC voltage Vref, i.e. a voltage Vref having a constant value independent of temperature. More particularly, circuit 1 is configured to generate voltage Vref from a voltage difference DVbe between base-emitter voltages Vbel and Vbe2 of transistors Q1 and Q2. More particularly, voltage DVbe is equal to base-emitter voltage vbel of transistor Q1 minus base-emitter voltage Vbe2 of transistor Q2 (DVbe = Vbel - Vbe2).

[0036] Transistors Q1 and Q2 are for example of the NPN type. Transistor Q2 is P times larger than transistor Q1, for example 8 times larger, it being understood that the value of the number P can take other values ​​strictly greater than 1 than 8, these values ​​not necessarily being integers.

[0037] The transistors Q1 and Q2 have their bases connected to each other and their emitters each coupled to a node 100 for applying a reference potential GND, for example ground.

[0038] Furthermore, the circuit 1 is configured so that the transistor Ql receives a collector current Ici and the transistor Q2 receives a collector current Ic2 equal to the current Ici. Thus, the circuit 1 comprises a current mirror 102 configured to provide the currents Ici and Ic2. The current mirror 102 is connected to the collector of the transistor Ql, to the collector of the transistor Q2 and to a node 104 configured to receive a supply potential VDD, for example positive with respect to the reference potential GND.

[0039] The current mirror 102 is implemented with MOS (Metal Oxide Semiconductor) transistors. More particularly, the mirror 102 comprises a MOS transistor M1 having its source connected to node 104, and its drain coupled, preferably connected, to the collector of the transistor Q1, as well as a MOS transistor M2 having its source connected to node 104, and its drain coupled, preferably connected, to the collector of the transistor Q2. The gates of the transistors M1 and M2 are connected to each other. For example, the gate of the transistor M2 is connected to the drain of the transistor M2. For example, alternatively, the gate of the transistor M1 is connected to the drain of the transistor ML. The MOS transistors M1 and M2 are identical to each other, or, in other words, have the same dimensions. Thus, the dimension ratio between transistors M1 and M2 is equal to 1, or, in other words, the current ratio of current mirror 102 is equal to 1.Transistor Ml supplies current Ic to transistor Ql, transistor M2 supplies current Ic2 to transistor Q2.

[0040] Circuit 1 comprises a resistor RI connected between the emitter of transistor Q2 and the emitter of transistor Q1, and a resistor R2 connected between the emitter of transistor Q1 and node 100. In other words, resistor RI has one terminal coupled, preferably connected, to the collector of transistor Q2, and another terminal coupled, preferably connected, to the collector of transistor Q1, resistor R2 having one terminal coupled, preferably connected, to the collector of transistor Q2, and another terminal coupled, preferably connected, to node 100.

[0041] By way of example, a buffer circuit 106 is provided between the collector and the base of the transistor Q1. Although this is not illustrated in [Fig.1], this buffer circuit comprises, for example, a MOS transistor having its gate connected to the input of the buffer circuit 106 which is itself connected to the collector of the transistor Q1, a source connected to the output of the circuit 106 which is itself connected to the bases of the transistors Q1 and Q2, this MOS transistor being configured as a source follower, or, in other words, as a voltage follower.

[0042] As an alternative example, the buffer circuit can be replaced by a direct connection between the collector and the base of the transistor Q1. As another alternative example, rather than coupling the collector and the base of the transistor Q1 by the buffer circuit or a direct connection, the collector and the base of the transistor Q2 are coupled to each other, by a buffer circuit or by a direct connection, the base and the collector of the transistor Q1 then not being coupled to each other by a direct connection or a buffer circuit.

[0043] We call Ibl the base current of transistor Ql, and Ib2 the base current of transistor Q2. In addition, we call lel the emitter current of transistor Ql and Ie2 the emitter current of transistor Q2.

[0044] In circuit 1 of [Fig.l], a temperature-stable voltage Vref is available at the base of transistor Q2. Voltage Vref is equal to the sum of voltage Vbel and a voltage V2 across resistor R2. A current I2 equal to the sum of currents Ie1 and Ie2 flows through resistor R2. Thus: Vref = Vbel + V2 Vref = Vbel + I2*R2.

[0045] If the currents Ie1 and Ie2 are equal, then the current I2 in the resistor R2 is equal to twice the current Ie2, from which it follows that: Vref = Vbel + 2*Ie2*R2, Vref = Vbel + 2*(DVbe / Rl)*R2.

[0046] As DVbe is equal to (K*T*ln(P)) / q, with K the Boltzmann constant, q the charge of the electron in Coulomb and T the temperature in Kelvin, we obtain: Vref = Vbel + 2*(R2 / Rl)*(K*T / q)*ln(P).

[0047] The voltage Vref is then clearly dependent on the voltage Vbel which is of the CTAT type and on a PTAT term proportional to the temperature T, from which it follows that by correctly dimensioning the circuit 1, for example by the choice of the value of RI and / or of the value of R2 and / or the number P, it is possible to obtain a voltage Vref independent of the temperature.

[0048] [Fig.2] illustrates another example of a bandgap circuit 2.

[0049] Circuit 2 comprises, like circuit 1, the elements Ql, Ml, Q2, M2 and, in the example of [Fig.2], 106, the latter being connected to each other and to node 104 in the same way as in circuit 1. Thus, unless otherwise indicated, what has been described for these elements in relation to [Fig.l] applies in circuit 2 of [Fig.2].

[0050] On the other hand, circuit 2 does not include resistors RI and R2.

[0051] Circuit 2 comprises a resistor R3 connected between the emitter of transistor Ql and node 100. For example, resistor R3 has one terminal coupled, preferably connected, to the emitter of transistor Ql, and another terminal coupled, preferably connected, to node 100.

[0052] Circuit 2 includes a resistor R4 connected between the emitter of transistor Q2 and node 100. For example, resistor R4 has one terminal coupled, preferably connected, to the emitter of transistor Q2, and another terminal coupled, preferably connected, to node 100.

[0053] Circuit 2 comprises a bipolar transistor Q3. Transistor Q3 has its collector connected to node 104. Transistor Q3 is of the same type, for example NPN, as transistors Q1 and Q2.

[0054] Circuit 2 includes a resistor R5 connected between the emitter of transistor Q2 and the emitter of transistor Q3. For example, resistor R5 has one terminal coupled, preferably connected, to the emitter of transistor Q2, and another terminal coupled, preferably connected, to the emitter of transistor Q3.

[0055] Circuit 2 comprises a MOS transistor M3 having its drain connected to the base of transistor Q3, its source connected to node 100 and its gate connected to the collector of transistor Q2. Transistor M3 is, for example, N-channel in this example where transistors Q1, Q2 and Q3 are NPN bipolar transistors.

[0056] A capacitor C is connected between the gate and the drain of transistor M3. For example, capacitor C has one terminal connected to the drain of transistor M3 and another terminal connected to the gate of transistor M3.

[0057] Transistor M3 is biased by a current source connected between the drain of transistor M3 and node 104. The current source couples the drain of transistor M3 to node 104. For example, the bias current source of transistor M3 is implemented by a MOS transistor M4 having its source connected to node 104, its drain connected to the drain of transistor M3 and its gate connected to the gates of transistors M1 and M2 of current mirror 102.

[0058] As for circuit 1, the buffer circuit 106 of circuit 2 can be replaced by a direct connection.

[0059] A temperature-stable voltage Vref is available at the base of transistor Q3.

[0060] The voltage Vref is equal to the sum of a voltage V4 across the terminals of the resistor R4, of a voltage V5 across resistor R5 and the base-emitter voltage Vbe3 of transistor Q3. Thus, Vref = V4 + V5 + Vbe3.

[0061] In circuit 2, the voltage V5 is equal to the product of the resistor R5 by the current 15 which flows in the resistor R5. This current 15 is equal to the current 14 which flows in the resistor R4 minus the current Ie2, the current 14 in the resistor R4 being equal to the ratio of the voltage V4 by the resistor R4. Thus, V5 = R5*((V4 / R4) - Ie2), from which it follows that: Vref = V4 + R5*((V4 / R4) - Ie2) + Vbe3 Vref = V4*(l + (R5 / R4)) - R5*Ie2 + Vbe3.

[0062] In circuit 2, voltage V4 is equal to the sum of voltage DVbe and a voltage V3 across resistor 3, this voltage V3 being equal to the product of current lel by resistor R3. Thus, V4 = DVeb + R3*Iel. It follows that: Vref = DVbe*(l + (R5 / R4)) + Iel*R3*(l + (R5 / R4)) - R5*Ie2 + Vbe3.

[0063] If the currents lel and Ie2 are equal (lel = Ie2), and if the value of the resistor R3 is equal to the equivalent value of the two resistors R4 and R5 connected in parallel, then the terms lel* R3*(l + (R5 / R4)) and R5*Ie2 are equal and we obtain: Vref = Dvbe*(l + (R5 / R4)) + Vbe3, Vref = (1 + (R5 / R4))*(((K*T) / q)*ln(P)) + Vbe3.

[0064] The voltage Vref is then indeed dependent on the voltage Vbe3 which is of the CTAT type and on a PTAT term proportional to the temperature T, from which it follows that by correctly dimensioning the circuit 2, for example by the choice of the value of R4 and / or the value of R5 and / or the number P, it is possible to obtain a voltage Vref independent of the temperature.

[0065] Many other examples of bandgap circuits exist, in which a temperature-stable reference voltage is generated from a difference Dvbe between the base-emitter voltages of the bipolar transistors Q1 and Q2 as described in connection with Figures 1 and 2.

[0066] However, in these circuits, the value of the temperature-stable voltage Vref may not be the one expected, i.e. the value of the voltage Vref actually obtained is different from the theoretical value of the voltage Vref for which the circuit was sized.

[0067] This results in particular from the fact that, even when the two transistors Q1 and Q2 receive equal currents Ic1 and Ic2, if the current gain [31 of the transistor Q1 is not equal to the current gain [32 of the transistor Q2, then the currents Ie1 and Ie2 are not equal.

[0068] Indeed, lel = Ici + Ibl and Ie2 = Ic2 + Ib2, from which it follows that lel = Ici + lel / [31 and Ie2 = Ic2 + Ic2 / [32. If the gain [31 is different from the gain [32 and the currents Ici and Ic2 are equal, then the currents lel and Ie2 are different.

[0069] More particularly, when the currents Ici and Ic2 are equal but the gains [31 and [32 are different, then the currents Ibl and Ib2 are different and lel = Ie2 + Ib 1 -Ib2, or, in other words Ie2 = lel + Ib2 - Ibl. The difference between the currents Ibl and Ib2 introduces an error between the currents lel and Ie2 which are no longer equal, therefore an error on the value of the voltage Vref obtained.

[0070] For example, transistors Q1 and Q2 have different gains [31 and

[32] when the bandgap circuits, for example circuits 1 and 2, are implemented in FinFet technology. Indeed, in this technology, the inventors have found that the current gain [3] of a bipolar transistor depends on the collector current density of this transistor. However, in bandgap circuits comprising two transistors Q1 and Q2 as described above, the collector current density of the two transistors Q1 and Q2 is not the same.

[0071] It is proposed here to correct the error on the equality of the currents lel and Ie2, by generating a correction current Icorr equal to the difference between the currents Ibl and Ib2, and by injecting this correction current on the emitter of one of the transistors Q1 and Q2 so as to make the currents lel and Ie2 equal, or, in other words, so as to correct an error on the value of the voltage Vref which results from a difference in current gain between the transistors Q1 and Q2.

[0072] According to one embodiment, a correction circuit CORR is proposed, configured to generate the correction current Icorr, and to inject it into the emitter of one of the two transistors Q1 and Q2.

[0073] According to one embodiment, there is provided a device comprising a bandgap circuit comprising two transistors Q1 and Q2 as described, the bandgap circuit being configured to generate a temperature-stable voltage, the device further comprising a circuit as defined above.

[0074] [Fig. 3] represents an embodiment of an electronic device 3 comprising the bandgap circuit 1 of [Fig. 1] and a correction circuit CORR according to one embodiment.

[0075] The device 3 is configured to provide the temperature-stable voltage Vref, this voltage Vref being provided by the circuit 1 of the device 3.

[0076] The CORR circuit is configured to provide the current Icorr. For example, the CORR circuit includes an output 304 configured to provide the current Icorr. In this embodiment, the CORR circuit is configured to provide the current Icorr equal to the current Ib2 minus the current Ibl, or, in other words, Icorr = Ib2 - Ibl.

[0077] Furthermore, the CORR circuit is configured to inject the current Icorr onto the emitter of one of the transistors Q1 and Q2 of the circuit 1. In this embodiment, as Icorr = Ib2 - Ibl, the current Icorr is injected into the emitter of transistor Ql, or, in other words, into the connection node of the emitter of transistor Ql to resistor R2. In other words, the output 304 of the CORR circuit is connected to the emitter of transistor Ql. Indeed, as indicated previously, when the gains [31 and [32 are not equal, then lel = Ie2 + Ibl - Ib2. By injecting the current Icorr into the emitter of transistor Ql, that is to say by adding the current Icorr to the current lel, a corrected emitter current lel' equal to lel + Icorr is supplied to the interconnection node of resistors RI and R2 between them. It follows that: lel' = lel + Icorr, lel' = Ie2 + Ibl - Ib2 + Ib2 - Ibl, lel' = Ie2.

[0078] By repeating the calculations described in relation to [Fig.l]: Vref = Vbel + I2*R2, Vref = Vbel + (lel' + Ie2)*R2, Vref = Vebl + 2*Ie2*R2, although the currents lel and Ie2 are not equal.

[0079] For example, the CORR circuit is powered by the voltage VDD. The CORR circuit then comprises a terminal 300 connected to the node 100 and a terminal 302 connected to the node 104.

[0080] As an example, the CORR circuit has a terminal 306 connected to the current mirror 102, for example to the gates of the transistors M1 and M2 of the mirror 102. In this way, by using MOS transistors mounted as a current mirror with the transistors M1 and M2, the CORR circuit can generate two currents determined by the currents Ic1 and Ic2, and supply these two currents respectively to two bipolar transistors so that a first of these two bipolar transistors has a base current determined by the current Ibl, and the other of these two bipolar transistors has a base current determined by the current Ib2. These two image currents of the currents Ibl and Ib2 are then supplied to a current summing node coupled to the output 304 of the CORR circuit so that the current Icorr is equal to the difference of the currents Ibl and Ib2.For example, of the two image currents, one is supplied to the summing node by a current mirror, so that the resulting current Icorr is equal to the difference of the currents Ibl and Ib2.

[0081] An embodiment has been described in relation to [Fig.3] in which the CORR circuit provides a current Icorr equal to Ib2 - Ibl, and this current is therefore injected into the emitter of the transistor Ql.

[0082] In another embodiment, the current Icorr is equal to Ibl - Ib2. In this other embodiment, the current Icorr is then injected into the emitter of the transistor Q2. In this other embodiment, the current flowing in the resistor RI is then a current Ie2' equal to the sum of the currents Ie2 and Icorr. This results in: Ie2' = Ie2 + Icorr, Ie2' = lel + Ib2 - Ib 1 + Ib 1 - Ib2, Ie2' = Iel.

[0083] By repeating the calculations described in relation to [Fig.l]: Vref = Vbel + I2*R2, Vref = Vbel + (lel + Ie2')*R2, Vref = Vbel + 2*Ie2'*R2, although the currents lel and Ie2 are not equal.

[0084] By replacing Ie2' with Dvbe / Rl, we find: Vref = Vbel + 2*(R2 / Rl)*DVbe, Vref = Vbel + 2*(R2 / Rl)*(K*T / q)*ln(P) although the currents lel and Ie2 are different.

[0085] [Fig.4] represents an embodiment of the correction circuit of [Fig.3].

[0086] In this embodiment, the CORR circuit comprises the terminal 306 connected to the current mirror 102 (not shown in [Fig.4]), for example to the gates of the transistors M1 and M2 of the mirror 102. The CORR circuit further comprises a MOS transistor M1' and a bipolar transistor Q1' connected in series between the terminals 302 and 300 of the circuit, i.e. between the nodes 104 (VDD) and 102 (GND), these nodes 104 and 102 not being shown in [Fig.4]. The CORR circuit further comprises a MOS transistor M2' and a bipolar transistor Q2' connected in series between the terminals 302 and 300 of the circuit. Transistors Ml' and Ql', respectively M2' and Q2', are configured so that the base current Ibl' of transistor Ql', respectively the base current Ib2' of transistor Q2', is an image current of current Ibl of transistor Ql, respectively of current Ib2 of transistor Q2.

[0087] Transistors Ml' and M2' are mounted in current mirror with transistors Ml and M2, so that transistor Ml' provides a current Ici' image of current Ici and transistor M2' provides a current Ic2' image of current Ic2. Transistors Ml' and M2' have channels of the same N or P type as those of transistors Ml and M2. For example, transistor Ml' has its source connected to terminal 302 and its gate connected to the gate of transistors Ml and M2, transistor M2' having its source connected to terminal 302 and its gate connected to the gate of transistors Ml and M2.

[0088] Transistors Ql' and Q2' are of the same NPN or PNP type as transistors Ql and Q2. Transistor Ql' is connected to transistor Ml'. More particularly, transistor Ql' has its collector connected to the drain of transistor Ml' so as to receive current Ic'. Symmetrically, transistor Q2' is connected to transistor M2'. More particularly, transistor Q2' has its collector connected to the drain of transistor M2' so as to receive current Ic2'. Thus, current Ibl', respectively Ib2', is an image current of current Ibl, respectively Ib2.

[0089] The emitters of transistors Q1' and Q2' are each coupled, preferably connected, to terminal 300.

[0090] According to one embodiment, the transistors Ml and Ml' are identical, the transistors M2 and M2' are identical, the transistors Ql and Ql' are identical and the transistors Q2 and Q2' are identical, from which it follows that the currents Ibl' and Ib2' are equal to the respective currents Ibl and Ib2.

[0091] The CORR circuit further comprises a transistor M5, for example with a channel of the type opposite to that of the channel of the transistor M1', and a transistor M6, for example with a channel of the type opposite to that of the transistor M2'.

[0092] Transistor M5 has its gate connected to the collector of transistor Ql', and its source connected to the base of transistor Ql'. Symmetrically, transistor M6 has its gate connected to the collector of transistor Q2', and its source connected to the base of transistor Q2'.

[0093] The CORR circuit comprises a current mirror 400 with MOS transistors coupling the drains of the transistors M5 and M6. The drain of one of the transistors M5 and M6 has the function of current summing node and is coupled to the output 304. The current mirror 400 is configured so that the current Icorr supplied by the output 304, i.e. the current Icorr supplied by the summing node, is equal to the difference of the currents Ibl and Ib2.

[0094] More particularly, in this embodiment where the current Icorr = Ib2 - Ibl, the summing node coupled to the output 304 is the drain of the transistor M5. The current mirror 400 is then configured to provide a current Ib2" to the summing node (drain of the transistor M5) so that the current Icorr is equal to Ib2" - Ibl', and that Ib2" - Ibl' is equal to Ib2 - Ibl.

[0095] According to one embodiment, when the transistors Ml', M2', Ql' and Q2' are identical to the respective transistors Ml, M2, Ql and Q2, and the currents Ibl' and Ib2' are then equal to the respective currents Ibl and Ib2, the current mirror 400 has a unit current ratio. In the example of [Fig.4], this means that the current Ib2" is equal to the current Ib2'.

[0096] By way of example, the current mirror 400 comprises two MOS transistors M7 and M8, for example with a channel of the same type as that of the channels of the transistors M1' and M2', having their gates connected to each other, and their sources connected to the terminal 302. The drain of the transistor M7 is connected to the drain of the transistor M5, the drain of the transistor M8 being connected to the drain of the transistor M6. In this example, the drain of the transistor M8 is connected to the gate of the transistor M8.

[0097] In order to bias the summing node to a voltage suitable for the operation of the MOS transistor current mirror 400, the CORR circuit comprises a voltage source 402 connected between the summing node and the output 304. For example, the voltage source 402 has one terminal connected to the summing node and another terminal connected to the output terminal 304.

[0098] As an example, this voltage source 402 is implemented by a channel MOS transistor of the same type as that of the channels of transistors M7 and M8 having its source connected to the summing node, its drain connected to output 304 and its gate connected to the source of transistor M5 or M6 which is not connected to the summing node.

[0099] An embodiment has been described above in which the CORR circuit provides the current Icorr = Ib2 - Ib 1. In another embodiment, where the CORR circuit provides the current Icorr = Ib 1 - Ib2, the summing node is then the drain of the transistor M6 and the voltage source 402 couples the drain of the transistor M6 to the output 304. Furthermore, the current mirror 400 is then configured to provide a current Ibl" which is the image of the current Ibl' to the summing node, such that the current Icorr is equal to Ibl"-Ib2' and that Ibl" - Ib2' = Ibl - Ib2. In this other embodiment, when the transistors M1', M2', Q1' and Q2' are identical to the respective transistors M1, M2, Q1 and Q2, and the currents Ibl' and Ib2' are then equal to the respective currents Ibl and Ib2, the current mirror 400 has a unit current ratio, so that Ibl" is equal to Ibl'.

[0100] Embodiments in which the transistors Ml', M2', Ql' and Q2' are identical to the respective transistors Ml, M2, Ql and Q2, such that the currents Ibl' and Ib2' are equal to the respective currents Ibl and Ib2 have been described.

[0101] In other embodiments, to reduce the dimensions of transistor Q2' relative to those of transistor Q2, transistor Q2' is not identical to transistor Q2, and is N times smaller than transistor Q2, with N a number or factor strictly greater than 1, for example equal to 2. In these other embodiments, transistor M2' is then N times smaller than transistor M1', and transistors M7 and M8 have a dimension ratio equal to N, i.e. transistor M7 is N times larger than transistor M8. Transistors M1' and Q1' remain identical to the respective transistors M1 and Q1.

[0102] As an example, we then have Ici' = Ici and Ic2' = (1 / N)*lc2, from which it follows that Ibl' = Ibl and Ib2' = (1 / N)*lb2. As M7 is N times larger than M8, or, in other words, the current mirror 400 has a current ratio equal to N when the summing node is the drain of transistor M5, and to 1 / N when the summing node is the drain of transistor M6. Thus, in the example of [Fig.4], Ib2" = N*Ib2' = N*(l / N)*Ib2, from which it follows that Icorr = Ib2" - Ibl' = Ib2 - Ibl.

[0103] Although an embodiment of a device 3 in which the CORR circuit is connected to the circuit 1 has been described in relation to [Fig. 3], the CORR circuit can be used with other bandgap circuits, for example with the circuit 2 of the [Fig.2].

[0104] [Fig.5] represents an embodiment of an electronic device 5 comprising the bandgap circuit 2 of [Fig.2] and the CORR circuit of [Fig.3], for example implemented in the manner described in relation to [Fig.4].

[0105] The device 5 is configured to provide the temperature-stable voltage Vref, this voltage Vref being provided by the circuit 2 of the device 5.

[0106] The CORR circuit is configured to provide the current Icorr. For example, the CORR circuit includes an output 304 configured to provide the current Icorr. In this embodiment, the CORR circuit is configured to provide the current Icorr equal to the current Ib2 minus the current Ib 1, or, in other words, Icorr = Ib2 — Ib 1.

[0107] Furthermore, the CORR circuit is configured to inject the current Icorr into the emitter of one of the transistors Q1 and Q2 of the circuit 1. In this embodiment, since Icorr = Ib2 - Ib 1, the current Icorr is injected into the emitter of the transistor Ql, or, in other words, into the connection node of the emitter of the transistor Ql to the resistor R3. In other words, the output 304 of the CORR circuit is connected to the emitter of the transistor QL. By injecting the current Icorr into the emitter of the transistor Ql, i.e. by adding the current Icorr to the current lel, a corrected emitter current lel' equal to lel + Icorr flows in the resistor R3. This results in: lel' = lel + Icorr, lel' = Ie2 + Ib 1 - Ib2 + Ib2 - Ib 1, Iel' = Ie2.

[0108] By repeating the calculations described in relation to [Fig.2]: Vref = DVbe*(l + (R5 / R4)) + Iel'*R3*(l + (R5 / R4)) - R5*Ie2 + Vbe3, from which it follows that: Vref = Vref = DVbe*(l + (R5 / R4)) + Ie2*(R3*(l + (R5 / R4)) - R5) + Vbe3. By setting the value of resistor R3 equal to the equivalent value of resistors R4 and R5 connected in parallel, the terms R3*(l + (R5 / R4)) and -R5 cancel out and we obtain: Vref = (1 + (R5 / R4))*(K*T / q)*ln(P) + Vbe3 although the currents lel and Ie2 are different.

[0109] In another embodiment, the current Icorr is equal to Ibl - Ib2. In this other embodiment, the current Icorr is then injected onto the emitter of the transistor Q2, i.e. onto the connection node of the resistor R4 to the resistor R5. In this other embodiment, the current I2 which flows in the resistor R4 is then the sum of a current Ie2' and the current I5, with: Ie2' = Ie2 + Icorr, Ie2' = lel + Ib2 - Ibl + Ibl - Ib2, Ie2' = Iel.

[0110] By repeating the calculations described in relation to [Fig.2]: Vref = DVbe*(l + (R5 / R4)) + Iel*R3*(l + (R5 / R4)) - R5*Ie2' + Vbe3, from which it follows that: Vref = Vref = DVbe*(l + (R5 / R4)) + Iel*(R3*(l + (R5 / R4)) - R5) + Vbe3. By setting the value of resistor R3 equal to the equivalent value of resistors R4 and R5 connected in parallel, the terms R3*(l + (R5 / R4)) and -R5 cancel out and we obtain: Vref = (1 + (R5 / R4))*(K*T / q)*ln(P) + Vbe3 although the currents lel and Ie2 are different.

[0111] Embodiments of devices 3 and 5 comprising the CORR circuit and bandgap circuits 1 and 2 respectively have been described. However, the person skilled in the art is able to provide other devices for generating a temperature-stable reference voltage Vref comprising: a bandgap circuit configured to provide the voltage Vref from a difference between the base-emitter voltage Vbel of a first bipolar transistor Q1 and the base-emitter voltage Vbe2 of a second bipolar transistor Q2, for example biased by a current mirror 102 as in circuits 1 and 2, and the CORR correction circuit configured for: - generate the correction current Icorr equal to the difference between a base current of one of the transistors Q1 and Q2 and a base current of the other of the transistors Q1 and Q2; and - injecting the current Icorr into the emitter of one of the bipolar transistors Q1 and Q2 so as to correct an error in a value of the voltage Vref resulting from a difference between the current gains [31 and [32 of the transistors Q1 and Q2, or, in other words, so as to correct an error in the equality of the emitter currents lel and Ie2 of the transistors Q1 and Q2 which results from the difference between the current gains [31 and [32 of the transistors Q1 and Q2.

[0112] As previously indicated, the difference between the current gains [31 and [32 results for example from a variation of the current gain [3 of a bipolar transistor with its collector current density.

[0113] For example, bipolar transistors implemented in FinFet technology exhibit a variation in their current gain [3 with the collector current density. Thus, according to one embodiment, the bipolar and MOS transistors of a device for generating a temperature-stable voltage Vref which comprises a bandgap circuit and the CORR circuit, are all implemented in FinFet technology.

[0114] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. job.

[0115] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the person skilled in the art is able to size the bandgap circuits configured to generate the voltage Vref.

Claims

Claims

1. Correction circuit (CORR) for a bandgap circuit (1; 2) comprising a first bipolar transistor (Ql) and a second bipolar transistor (Ql, Q2), the bandgap circuit being configured to provide a continuous and temperature-stable voltage (Vref) from a difference (Dvbe) between a base-emitter voltage (Vbel) of the first bipolar transistor (Ql) and a base-emitter voltage (Vbe2) of the second bipolar transistor (Q2), the correction circuit being configured to: generate a correction current (Icorr) equal to a difference between a base current (Ib2) of one of said first and second transistors (Q2) and a base current of the other of said two transistors (Ql);and injecting the correction current (Icorr) into the emitter of one of said first and second bipolar transistors (Ql) so as to correct an error in a temperature-stable voltage value (Vref) resulting from a difference in current gain between said first and second bipolar transistors (Ql, Q2).;

2. Device (3, 5) for generating a continuous and temperature-stable voltage (Vref), the device comprising: a bandgap circuit (1; 2) comprising a first bipolar transistor (Ql) and a second bipolar transistor (Ql) and being configured to provide a continuous and temperature-stable voltage (Vref) from a difference (Dvbe) between a base-emitter voltage (Vbel) of the first bipolar transistor (Ql) and a base-emitter voltage (Vbe2) of the second bipolar transistor (Q2); and a correction circuit (CORR) according to claim 1.

3. Device according to claim 2, wherein: the first bipolar transistor (Ql) has smaller dimensions than the second bipolar transistor (Q2); the first and second bipolar transistors (Ql, Q2) have their bases connected to each other and their emitters coupled to a first node (100) for applying a reference potential (GND); and the bandgap circuit (1; 2) comprises: - a first MOS transistor (Ml) having a source connected to a second node (104) configured to receive a supply potential (VDD) and a drain coupled, preferably connected, to the collector of the first bipolar transistor (Ql), and - a second MOS transistor (M2) identical to the first MOS transistor (Ml) and having a source connected to the second node (104), a drain coupled, preferably connected, to the collector of the second bipolar transistor (Q2) and a gate connected to the gate of the first MOS transistor (Ml), the first and second MOS transistors (Ml, M2) being configured to supply a first current (Ici) to the first bipolar transistor (Ql) and a second current (Ic2) equal to the first current to the second bipolar transistor (Q2).

4. A device according to claim 3, wherein the bandgap circuit (1) comprises: a first resistor (RI) connected between the emitter of the first bipolar transistor (Ql) and the emitter of the second bipolar transistor (Q2); and a second resistor (R2) connected between the emitter of the first bipolar transistor (Ql) and the first node (100).

5. The device of claim 3, wherein the bandgap circuit (2) comprises: a first resistor (R3) connected between the emitter of the first bipolar transistor (Q1) and the first node (100); a second resistor (R4) connected between the emitter of the second bipolar transistor (Q2) and the first node (100); an additional bipolar transistor (Q3) having its collector connected to the second node (104); an additional MOS transistor (M3) having its drain connected to the base of the additional bipolar transistor (Q3) and coupled to the second node (104) by a current source (M4), its gate connected to the collector of the second bipolar transistor (Q2) and its source connected to the first node (100); a capacitor (C) coupling the drain and the gate of the additional MOS transistor (M3); and a third resistor (R5) connected between the emitter of the second bipolar transistor (Q2) and the emitter of the additional bipolar transistor (Q3).

6. Device according to claim 4 or 5, in which the correction circuit (CORR) is configured to inject the correction current (Icorr) on the connection node of the first resistor (RI; R3) to the first bipolar transistor (Ql).

7. A device according to any one of claims 3 to 5, wherein the correction circuit (CORR) includes: a third MOS transistor (Ml1) and third bipolar transistor (Ql') in series between the first and second nodes (100, 104); a fourth MOS transistor (M21) and fourth bipolar transistor (Q21) in series between the first and second nodes (100, 104); a sixth MOS transistor (M5) having its gate connected to the connection node of the third MOS transistor (Ml1) to the third bipolar transistor (Ql1), its source connected to the base of the third bipolar transistor (Ql1) and its drain connected to a third node; a seventh MOS transistor (M6) having its gate connected to the connection node of the fourth MOS transistor (M21) to the fourth bipolar transistor (Q21), its source connected to the base of the fourth bipolar transistor (Q21) and its drain connected to a fourth node; a current mirror (400) with MOS transistors (M7, M8) coupling the third and fourth nodes; and a voltage source (402) coupling the third or fourth node to an output (304) of the correction circuit (CORR) configured to provide the correction current (Icorr).

8. Device according to claim 7, wherein: the third MOS transistor (Ml1) is identical to the first MOS transistor (Ml); the third bipolar transistor (Ql1) is identical to the first bipolar transistor (Ql); the fourth MOS transistor (M21) is identical to the second MOS transistor (M2); the fourth bipolar transistor (Q21) is identical to the second bipolar transistor (Q2); and a current ratio of the current mirror (400) is equal to 1.

9. Device according to claim 7, wherein: the third MOS transistor (Ml1) is identical to the first MOS transistor (Ml); the third bipolar transistor (Ql1) is identical to the first bipolar transistor (Ql); the fourth MOS transistor (M21) is N times smaller than the second MOS transistor (M2), with N a number strictly greater than 1, for example equal to 2; the fourth bipolar transistor (Q21) is N times smaller than the second bipolar transistor (Q2); and the current mirror comprises two MOS transistors (M7, M8) having a dimension ratio N between them.

10. A device according to any one of claims 7 to 9, wherein: the voltage source (402) couples the third node to the output; and the current mirror (400) is configured to provide the third node with a current (Ib2") determined by the base current (Ib2) of the fourth bipolar transistor (Q21).

11. Device according to claim 10, wherein the output (304) of the correction circuit (CORR) is connected to the emitter of the first bipolar transistor (Ql).

12. Device according to any one of claims 2 to 11, in which the first and second bipolar transistors (Q1, Q2) are of the NPN type.

13. Device according to any one of claims 2 to 12, wherein the transistors (Ql, Q2, Ml, M2, Ql', Q2', Ml', M2') are implemented in FinFet technology.

Images