SILICON CARBIDE-BASED SEMICONDUCTOR STRUCTURE FOR POWER APPLICATIONS AND ASSOCIATED MANUFACTURING METHOD

Abstract

The present invention relates to a semiconductor structure based on silicon carbide comprising: - a useful layer of monocrystalline silicon carbide having a first uniform dopant concentration over its thickness, - a support substrate of polycrystalline silicon carbide having a second uniform dopant concentration over its thickness and a resistivity less than or equal to 10 mohm.cm, the second concentration being linked to the first concentration by the following relationship: C2 > N2 x exp(-C1 / N1) with C1 the first concentration, C2 the second concentration, N1 = 2.85.1018 cm-3 and N2 = 5.40.1020 cm-3, - an interface zone, between the support substrate and the useful layer, comprising nodules and regions of direct contact between the useful layer and the support substrate, the nodules comprising a metallic or semiconducting material distinct from silicon carbide, the interface zone having an average resistivity less than or equal to 0.01 mohm.cm2, a dopant concentration profile according to a thickness of the semiconductor structure: - in the form of a step, and - being devoid of a doping peak in the interface zone, or - having a doping peak in the interface zone, the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration at plus or minus 10%. The invention also relates to a method for manufacturing such a semiconductor structure. No figure.

Description

Title of the invention: SILICON CARBIDE-BASED SEMICONDUCTOR STRUCTURE FOR POWER APPLICATIONS AND ASSOCIATED MANUFACTURING METHOD FIELD OF THE INVENTION

[0001] The present invention relates to the field of microelectronics and more particularly to power electronics. It relates in particular to a structure comprising a high-quality monocrystalline semiconductor layer of silicon carbide and a support substrate of polycrystalline silicon carbide, assembled at an electrically conductive interface zone. The invention also relates to a method for manufacturing such a structure.

[0002] TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] It is usual to form a semiconductor structure by transferring a useful semiconductor layer, of low thickness and high crystalline quality, onto a semiconductor support substrate of lower crystalline quality. A well-known thin layer transfer solution is the Smart Cut™ process, based on an implantation of light ions into a donor substrate and on an assembly by direct bonding at a bonding interface between said donor substrate and a support substrate; a separation takes place along a buried fragile plane defined by the implantation, leading to the transfer of a useful layer from the donor substrate onto the support substrate. In addition to the economic advantages linked to the rationalization of the high-quality material of the useful layer, the semiconductor structure can also provide advantageous properties, for example linked to the thermal, electrical conductivity or the mechanical compatibility of the support substrate.

[0004] In the field of power electronics, for example, it is advantageous to establish electrical conduction between the useful layer and the support substrate, so as to form vertical components. For example, in the case of a structure comprising a useful layer of monocrystalline silicon carbide (SiC) and a support substrate of lower quality silicon carbide (SiC) (monocrystalline or polycrystalline), the bonding interface must have an electrical resistivity as low as possible, less than 0.1 mohm.cm2, or even preferably less than 0.01 mohm.cm2.

[0005] Some state-of-the-art solutions propose to carry out direct semiconductor-to-semiconductor bonding, between the useful layer and the support substrate, to establish vertical electrical conduction. It is nevertheless difficult to obtain good interface quality via such bonding.

[0006] F. Mu et al (ECS Transactions, 86 (5) 3-21, 2018) implements direct bonding, after activation of the surfaces to be assembled by argon bombardment (SAB for "Surface Activation Bonding"): such a treatment prior to bonding generates a very high density of dangling bonds, which promote the formation of covalent bonds at the assembly interface, and therefore a high bonding energy. This method nevertheless has the disadvantage of generating an amorphous layer, at the level of the assembled surfaces, which adversely impacts the vertical electrical conduction between the thin layer and the support substrate. To overcome this problem, strong doping of said surfaces, by shallow implantation, is proposed in particular in document EP3168862.Besides the fact that shallow implantation doses cannot increase indefinitely, large introductions of dopant atoms tend to damage the crystalline quality of the useful layer and / or decrease the bonding energy of the structure.

[0007] Other state-of-the-art solutions propose producing conductive bonding starting from different types of layers deposited on the surfaces to be assembled, to avoid massive implantation of dopants before assembly.

[0008] Document WO2022 / 008809 proposes forming an interface zone from a very thin layer of a metallic material, for example tungsten, in a SiC / SiC semiconductor structure. Considering a useful layer and a support substrate made of monocrystalline SiC with a resistivity of 20 mohm.cm, and a layer of 1 nm to 3 nm of tungsten (W) sandwiched between the useful layer and the support substrate, it is possible to obtain a resistivity of the interface zone less than or equal to 0.1 mohm.cm2, after applying an adequate heat treatment and formation of very fine nodules largely made of metal (W), responsible for the good vertical conduction of the interface zone.

[0009] Document WO2022 / 129726 proposes to form an interface zone, in a SiC / SiC semiconductor structure, comprising regions of direct contact between the useful layer and the support substrate, and agglomerates comprising a semiconductor material different from that or those of the useful layer and the support substrate, and having a thickness less than or equal to 250 nm. The semiconductor material is chosen for its particular affinity with oxygen. Thus, the agglomerates are capable of effectively trapping any oxygen possibly present at the bonding interface; the regions of direct contact between the useful layer and the support substrate, devoid of native oxide residues in particular, allow efficient and good quality electrical conduction and / or vertical semiconductor / semiconductor contact. Considering a useful layer with a resistivity of 20 mohm.cm, a support substrate with a resistivity of 20 mohm.cm and a silicon semiconductor material, it is possible to obtain a resistivity of the interface zone less than or equal to 0.1 mohm.cm2, for example. 0.032 mohm.cm2 (after annealing the structure at 1370°C) or 0.0076 mohm.cm2 (after annealing at very high temperature, namely 1900°C).

[0010] SUBJECT OF THE INVENTION

[0011] The present invention proposes a solution meeting the mentioned needs of very low resistivity (less than or equal to 0.01 mohm.cm2) of the interface zone of a semiconductor structure based on silicon carbide, and simplifying the development of the structure. It relates to a semiconductor structure and a method of manufacturing such a structure.

[0012] BRIEF DESCRIPTION OF THE INVENTION

[0013] The present invention relates to a silicon carbide-based semiconductor structure comprising:

[0014] - a useful layer of monocrystalline silicon carbide having a first uniform dopant concentration over its thickness,

[0015] - a polycrystalline silicon carbide support substrate having a second uniform dopant concentration over its thickness, the second concentration being linked to the first concentration by the following relation:

[0016] C2 > N2 x exp(-Ci / Ni) with

[0017] Ci the first concentration, C2 the second concentration, Ni = 2.85.1018 cm 3 and N2 = 5.40.1020 cm 3,

[0018] - an interface zone, between the support substrate and the useful layer, comprising nodules and regions of direct contact between the useful layer and the support substrate, the nodules comprising a metallic or semiconducting material distinct from silicon carbide, the interface zone having an average resistivity less than or equal to 0.01 mohm.cm2.

[0019] The dopant concentration profile according to a thickness of the semiconductor structure:

[0020] - is presented in the form of a step, and

[0021] - is devoid of doping peak in the interface zone, or

[0022] - has a doping peak in the interface zone, the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration plus or minus 10%.

[0023] According to advantageous characteristics of the invention, taken alone or in any feasible combination: • the resistivity of the support substrate is less than or equal to 10 mohm.cm, 5 mohm.cm, or even 3 mohm.cm, or even 2 mohm.cm; • the interface zone has a thickness less than or equal to 200 nm; • the metallic material of the nodules is chosen from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper, or the semiconductor material of the nodules is selected from silicon, germanium, carbon, III-V compounds such as gallium nitride or other compounds formed from these materials.

[0024] The invention also relates to a method for manufacturing a silicon carbide-based semiconductor structure comprising the following steps:

[0025] a) providing a useful layer of monocrystalline silicon carbide having a free face to be assembled and a first uniform dopant concentration over its thickness,

[0026] b) providing a polycrystalline silicon carbide support substrate having a free face to be assembled, a second concentration of dopants uniform over its thickness, the second concentration being linked to the first concentration by the following relationship:

[0027] C2 > N2 x exp(-Ci / Ni) with

[0028] Ci the first concentration, C2 the second concentration, Ni = 2.85.1018 cm 3 and N2 = 5.40.1020 cm 3,

[0029] c) the deposition of a film of a metallic or semiconducting material other than silicon carbide having a thickness less than or equal to 20 nm, on the free face to be assembled of the useful layer and / or on the free face to be assembled of the support substrate,

[0030] d) the formation of an intermediate structure, comprising a direct assembly of the free faces to be assembled respectively of the useful layer and of the support substrate, the intermediate structure including an encapsulated film resulting from the film(s) deposited during step c),

[0031] e) annealing the intermediate structure at a temperature between 1200°C and 2000°C, to form the semiconductor structure comprising an interface zone which includes nodules resulting from the segmentation of the encapsulated film and regions of direct contact between the thin layer and the support substrate.

[0032] The interface zone has an average resistivity less than or equal to 0.01 mohm.cm2; the dopant concentration profile according to a thickness of the semiconductor structure is in the form of a step, and is devoid of a doping peak in the interface zone or has a doping peak in the interface zone, the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration at plus or minus 10%.

[0033] According to advantageous characteristics of the invention, taken alone or in any feasible combination: • step a) comprises an implantation of light species in a monocrystalline silicon carbide donor substrate, to form a buried fragile plane which delimits, with a front face of the donor substrate, the useful layer;

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[0046] • step d) comprises, after direct assembly giving rise to a bonded assembly comprising the donor substrate and the support substrate, a separation at the level of the buried fragile plane, to form on the one hand the intermediate structure comprising the useful layer, the encapsulated film and the support substrate, and on the other hand, the remainder of the donor substrate; • before step c), the free face to be assembled of the thin layer has a monocrystalline surface, devoid of amorphous zones or zones damaged by doping or activation by bombardment, and the free face to be assembled of the support substrate has a polycrystalline surface, devoid of amorphous zones or zones modified by doping or activation by bombardment; • the method comprises a step of epitaxial growth of an additional layer of monocrystalline silicon carbide on the useful layer of the semiconductor structure. Brief description of the drawings Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which: [Fig.l] [Fig.l] shows a semiconductor structure according to the present invention; [Fig.2a] [Fig.2b] [Fig.2c] [Fig.2d] [Fig.2e] Figures 2a to 2e show steps of a manufacturing method according to the present invention; [Fig.3a] [Fig.3b] [Fig.3c] [Fig.3d] Figures 3a to 3d show steps of a manufacturing method according to the present invention; [Fig.4] [Fig.4] shows a dopant concentration profile (A) along the thickness of a semiconductor structure according to the present invention, among other dopant concentration profiles (B, C, D) of structures of the state of the art [Fig.5] [Fig.5] shows a curve translating the relationship linking the second concentration C2 to the first concentration Ch so as to obtain an average resistivity of the interface zone (noted pint in the figure), less than or equal to 0.01 mohm.cm2; the first concentration Ci and the second concentration C2 being respectively the dopant concentration of the useful layer of monocrystalline silicon carbide and the dopant concentration of the support substrate in a semiconductor structure according to the invention.

[0047] Certain figures are schematic representations which, for the sake of readability, are not to scale. In particular, the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes. The same references in the figures may be used for elements of the same nature. DETAILED DESCRIPTION OF THE INVENTION

[0048] The invention relates to a semiconductor structure 100 comprising a useful layer 10 made of monocrystalline silicon carbide, typically of polytype 4H, a support substrate 30 made of polycrystalline silicon carbide, typically of polytype 3C, and an interface zone 20 between the useful layer 10 and the support substrate 30 ([Fig. 1]). Like the useful layer 10, the interface zone 20 extends parallel to the main plane (x,y).

[0049] Advantageously, and as is usually the case in the field of microelectronics, the semiconductor structure 100 is in the form of a circular wafer with a diameter of between 100 mm and 450 mm. It is understood that, in this case, the support substrate 30 and the useful layer 10 also have such a circular shape. The front 100a and rear 100b (circular) faces of the wafer extend parallel to the main plane (x,y).

[0050] The semiconductor structure 100 has a total thickness typically between 300 micrometers and 1000 micrometers. The thickness of the support substrate 30 forms the major part of this total thickness, the useful layer 10 having a thickness typically less than a few micrometers, or even less than 1 μm.

[0051] According to the invention, the support substrate 30 has a dopant concentration (hereinafter called second concentration C2), uniform over its thickness. By uniform, we mean a dopant concentration constant over the thickness to within + / - 10%. For N-type doping, nitrogen, phosphorus or arsenic atoms will be present in the polycrystalline matrix of the support substrate 30, whereas these will be boron or aluminum atoms for P-type doping.

[0052] Advantageously, the resistivity of the support substrate 30 is less than or equal to 10 mohm.cm (i.e. a dopant concentration typically greater than or equal to 1.1020 cm 3), to 5 mohm.cm (i.e. a dopant concentration typically greater than or equal to 2.1020 cm 3), or even to 3 mohm.cm, or even to 2 mohm.cm (i.e. a dopant concentration greater than or equal to 4.1020 cm3).

[0053] The useful layer 10 also has a concentration of dopants (called first concentration Ci) uniform over its thickness (to within + / - 10%). The type of doping of the useful layer 10 is usually the same as that of the support substrate 30.

[0054] Furthermore, the second concentration C2 is related to the first concentration Ci by the following relation: C2 > N2 x exp(-Ci / Ni) with Ni = 2.85.1018 cm 3 and N2 = 5.40.1020 cm 3 , as illustrated in [Fig.5]. Note that this curve is defined for a useful monocrystalline layer 10 in 4H-SiC, doped with N type and a polycrystalline support substrate 30 in 3C-SiC, doped with N type.

[0055] The domain of the first Ci and C2 second concentrations according to the invention is therefore located above the curve of [Fig.5], said curve reflecting an average resistivity pint of the interface zone 20 equal to 0.01 mohm.cm2, and lower than this value when moving above the curve.

[0056] A wide range of resistivity can thus be used for the useful layer 10, in the semiconductor structure 100 according to the invention: a resistivity for example between a few ohms and 10 mohm.cm (i.e. typically a first concentration Ci in dopants between a few 1.1017 cm 3 and 1.1019 cm 3) can be implemented. By choosing the second concentration C2 of the support substrate 30 in the defined range (above the pint curve), excellent electrical conduction between the useful layer 10 and the support substrate 30 will be obtained via the interface zone 20.

[0057] The interface zone 20 comprises nodules 21 and direct contact regions 22 between the useful layer 10 and the support substrate 30. The nodules 21 are composed of a metallic or semiconducting material other than silicon carbide. Without this being limiting, the metallic material of the nodules 21 may be chosen from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper; the semiconducting material of the nodules 21 may be chosen from silicon, germanium, carbon, IILV compounds such as gallium nitride, or other compounds formed from these materials (SiGe, SiGeC, etc.).

[0058] The interface zone 20 has a thickness, along a z axis normal to the main plane (x,y), typically less than or equal to 200 nm, or even less than or equal to 100 nm. Its maximum thickness is in particular defined by the maximum thickness of the nodules 21. The nodules 21, distributed in the interface zone 20, are disjointed or joined; the disjointed nodules are mainly separated from each other by the direct contact regions 22 in which the useful layer 10 is directly in contact with the support substrate 30, in other words, in which there is a direct bond between the monocrystalline silicon carbide of the useful layer 10 and the polycrystalline silicon carbide of the support substrate 30.

[0059] By placing oneself in a median plane P of the interface zone 20, the rate of coverage of the direct contact regions 22 is typically between 30% and 80%.

[0060] In certain cases of semiconductor structure 100, there may possibly exist cavities of nanometric thickness in these direct contact regions 22, but said cavities typically occupy less than 10%, or even less than 5% of the surface area along the main plane (x,y) occupied by the direct contact regions 22. Their thickness is also less than that of the nodules 21.

[0061] According to the present invention, the interface zone 20 has an average resistivity less than or equal to 0.01 mohm.cm2. This refers to a “surface” resistivity in ohm.cm2 for the interface zone 20 due to its very small thickness. By average resistivity is meant the resistivity of the interface zone 20 as a whole, that is to say by integrating its different regions, namely the direct contact regions 22, the nodules 21 and the cavities (if they are present). Indeed, the resistivity of the interface zone 20 is obtained from a measurement of I(V) (current as a function of voltage) made at two electrodes formed on the structure 100, between which the current path passes through the interface zone 20, due to the presence of trenches 40 crossing said zone 20, between said electrodes. The resistive contributions of the other layers and interfaces involved in the current path are of course taken into account.

[0062] As is apparent from [Fig. 4], a dopant concentration profile A, along a thickness of the semiconductor structure 100, is in the form of a step, between the useful layer 10 and the support substrate 30. In other words, starting from the free face of the useful layer 10, crossing the interface zone 20 and penetrating into the support substrate 30 to a depth greater than 1 pm (parallel to the z axis), the dopant concentration profile defines a clear step between the thin layer 10, less doped than the support substrate 30, and the latter whose doping level is higher (in particular, of the order of 5.1018 cm3 for the first concentration Ci and of the order of 5.1020 cm3 for the second concentration C2, in the example of [Fig. 4]). There is no dopant diffusion profile increasing or modifying the uniform doping level of the thin layer 10 near the interface zone 20.

[0063] In addition, the interface zone 20 has an average doping level, identical to or very close to that of the support substrate 30. The interface zone 20 is devoid of a doping peak associated with an extrinsic introduction of dopants on the side of the useful layer 10 or of the support substrate 30 (for example by implantation); said interface zone 20 has a dopant concentration identical to plus or minus 10% to the second concentration.

[0064] Optionally, the interface zone 20 may have a doping peak, but the extremum of which corresponds to a concentration of dopants (called the third concentration) slightly higher or lower than the second concentration: the third dopant concentration is equal to the second dopant concentration C2 at plus or minus 10%. This doping peak is therefore also much lower than a peak associated with an extrinsic introduction of dopants as is visible on profiles B, C and D of [Fig.4], from state-of-the-art structures.

[0065] The semiconductor structure 100 thus guarantees excellent electrical conductivity between the useful layer 10 and the support substrate 30, via its interface zone 20. In particular, the direct contact regions 22 benefit from a high concentration of dopants, similar to that of the support substrate 30, due to the diffusion and trapping of the dopants of the support substrate 30 at the interface between the useful layer 10 and the support substrate 30. The nodules 21 can also participate in the vertical electrical conduction; the presence of a large quantity of dopants at the interface between the nodules 21 and the very heavily doped support substrate 30 is favorable to this electrical conduction.

[0066] The interface zone 20, with a resistivity less than or equal to 0.01 mohm.cm2, can be considered as “transparent” in the semiconductor structure 100, not providing any parasitic increase in resistance in the vertical electrical conduction.

[0067] In addition to its excellent electrical conduction, the interface zone 20 ensures physical continuity between the useful layer 10 and the support substrate 30, and provides excellent mechanical strength of the semiconductor structure 100. The quality of the useful layer 10 is therefore not affected by any holes or interface defects; note that the aforementioned cavities, when they are present, have dimensions and a density which do not negatively impact the quality and mechanical strength of the useful layer 10.

[0068] Power components may be produced on and / or in the useful layer 10 of a semiconductor structure 100 according to the invention. It is not required to thin the support substrate 30 to thicknesses less than 200 qm, or even less than 150 qm, because the high doping of the support substrate 30 ensures excellent vertical electrical conductivity. It is usually necessary to thicken the useful layer 10, for example by forming an additional layer by epitaxy, to produce the power components.

[0069] These components may in particular comprise at least one electrical contact on and / or in the support substrate 30, at the level of a rear face 100b of the semiconductor structure 100. By way of non-limiting examples, these power components may comprise transistors, diodes, thyristors or passive components (capacitors, inductors, etc.), etc.

[0070] The invention also relates to a method of manufacturing a semi- conductive 100 as previously described.

[0071] The manufacturing method firstly comprises a step a) of providing the useful layer 10 made of monocrystalline silicon carbide ([Fig.2a]). In this step a), the useful layer 10 has a free face 10a intended to be assembled during a subsequent step of the method, also called front face 10a; it also has a rear face 10b opposite its front face 10a. The thin layer 10 has a dopant concentration (first concentration Ci) uniform over its thickness. As mentioned previously, a resistivity for example between a few ohms and 10 mohm.cm (i.e. a first dopant concentration Ci between a few 1.1017 cm 3 and 1.1019 cm 3) may be implemented.

[0072] According to an advantageous embodiment, the useful layer 10 results from the transfer of a surface layer of a donor substrate 1, in particular a layer transfer based on the Smart Cut™ process.

[0073] Step a) can thus comprise an implantation of light species, for example hydrogen, helium or a combination of these two species, in a donor substrate 1 (typically 4H-SiC), to form a buried fragile plane 11 which delimits, with the front face 10a of the donor substrate 1, the useful layer 10 ([Fig.3a]).

[0074] According to a variant of this embodiment, step a) comprises the formation of the donor substrate 1 by epitaxy of a donor layer 1' on an initial substrate, prior to the implantation of the light species ([Fig.3b]). This variant makes it possible to form a donor layer 1' having the structural and electrical characteristics required for the intended application. In particular, excellent crystalline quality can be obtained by epitaxy, and in situ doping of the donor layer 1' can be precisely controlled. The implantation of light species to form the buried fragile plane 11 is then carried out in the donor layer 1'.

[0075] Alternatively, the useful layer 10 provided in step a) can of course be formed from other known thin layer transfer techniques.

[0076] The manufacturing method according to the invention then comprises a step b) of providing a support substrate 30 made of polycrystalline silicon carbide (typically 3C-SiC) ([Fig.2b]). The support substrate 30 has a free face 30a intended to be assembled during a subsequent step of the method, also called front face 30a; it also has a rear face 30b.

[0077] According to the invention, the dopant concentration (second concentration C2) of the support substrate 30 is uniform over its thickness and is linked to the first concentration Ci by the following relationship:

[0078] C2 > N2 x exp(-Ci / Ni) with Ni = 2.85.1018 cm 3 and N2 = 5.40.1020 cm 3, in particular in the case of N-type doping for the useful layer 10 and for the support substrate 30.

[0079] Advantageously, the resistivity of the support substrate 30 is less than or equal to 10 mohm.cm, or even 5 mohm.cm, 3 mohm.cm or even 2 mohm.cm.

[0080] The manufacturing method then comprises a step c) of depositing a film 2 made of a metallic or semiconducting material other than silicon carbide, on the free face to be assembled 10a of the useful layer 10 or on the free face to be assembled 30a of the support substrate 30 or, as illustrated in [Fig.2c] on the two free faces to be assembled 10a, 30a.

[0081] Note that the free face 10a of the useful layer 10 has a perfectly monocrystalline surface; no doping by implantation or activation by bombardment has deteriorated or amorphized its crystalline quality. Similarly, the free face 30a of the support substrate 30 has a polycrystalline surface, not modified or amorphized by any doping by implantation or activation by atomic bombardment.

[0082] The metallic material may be chosen from the following non-limiting list of materials: tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, copper; the semiconductor material may be chosen from the following non-limiting list: silicon, germanium, carbon, IILV compounds such as gallium nitride, or other compounds formed from these materials (SiGe, SiGeC, etc.).

[0083] The film 2 has a thickness less than or equal to 20 nm, preferably less than or equal to 10 nm, or even less than or equal to 5 nm. For example, the deposited film 2 may have a thickness of the order of 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 10 nm or 15 nm.

[0084] Note that when a film 2 is deposited on the two free faces 10a, 30a, the total thickness deposited, that is to say the sum of the thicknesses of film 2 deposited on both free faces 10a, 30a is preferably less than or equal to 20 nm, or even less than or equal to 10 nm. The total thickness of film 2 deposited must be kept low, so as to allow segmentation of the film in the form of nodules 21, at a later stage of the method.

[0085] The deposition of film 2 is carried out in a controlled, non-oxidizing atmosphere. It is important that film 2 does not undergo oxidation or is not degraded by pollution from the surrounding atmosphere. Typically, the deposition of step c) is carried out under a high vacuum, of the order of 106 Pa or less.

[0086] Depending on the nature of the film 2 deposited, step c) is carried out at room temperature or at low temperature, advantageously by a sputtering deposition technique using, to bombard the metal target, a neutral element or one whose residual presence in the deposited metal is not troublesome (Ar, Si, N, etc.).

[0087] According to a particular embodiment, the manufacturing method according to the invention comprises, prior to step c) of deposition, a step c') of deoxidation of the free face to be assembled 10a of the useful layer 10 and / or of the free face to be assembled 30a of the support substrate 30. Such a step makes it possible to remove the native oxide potential present on the surface of the useful layer 10 and / or of the support substrate 30. The deoxidation can be carried out by wet chemical treatment (removal by HF attack for example) or dry (dry etching or annealing in a reducing atmosphere).

[0088] The manufacturing method then comprises a step d) of forming an intermediate structure 150, which step comprises a direct assembly of the free faces to be assembled 10a, 30a respectively of the useful layer 10 and of the support substrate 30, at an assembly interface 15 ([Fig.2d]).

[0089] This direct assembly is preferably carried out by molecular adhesion bonding, consisting of bringing the faces to be assembled 10a, 30a into contact, under a controlled non-oxidizing atmosphere. This may involve direct bonding between the useful layer 10 and the film 2, when the latter has been deposited solely on the support substrate 30, or direct bonding between the support substrate 30 and the film 2, when the latter has been deposited solely on the useful layer 10, or even direct bonding between two films 2, when they have been deposited on the useful layer 10 and on the support substrate 30.

[0090] Direct assembly is preferably carried out under a high vacuum, of the order of 106 Pa or less.

[0091] Advantageously, the deposition of step c) and the direct assembly of step d) are chained together without breaking the vacuum, in situ or in multi-chamber equipment. Mention will be made, for example, of the atomic diffusion bonding equipment BV7000 from the company Canon, in which it is possible to successively carry out the deposition of the film 2 and the direct bonding, while maintaining a controlled atmosphere.

[0092] With reference to the advantageous embodiment illustrated in Figures 3a to 3d, step d) comprising the direct assembly of the free face to be assembled 10a of the useful layer 10 on the free face to be assembled 30a of the support substrate 30, gives rise to a bonded assembly 200 including the donor substrate 1, the support substrate 30, and the assembly interface 15 ([Fig.3c]). Step d) further comprises a separation at the buried fragile plane 11, to form on the one hand the intermediate structure 150 comprising the useful layer 10, the film(s) 2 and the support substrate 30, and on the other hand, the remainder of the donor substrate 1” ([Fig.3d]). Such a separation can be carried out during a heat treatment capable of causing cavities and microcracks, induced by the implanted species, to grow in the buried fragile plane 11.Separation can also be achieved by applying mechanical stress, or by combining thermal and mechanical stresses, as is well known with reference to the Smart Cut™ process.

[0093] Sequences of cleaning, smoothing, polishing or engraving the separated face 10b of the useful layer 10 and / or of the separated face 1”a from the rest of the donor substrate 1” may be carried out so as to restore good surface quality, particularly in terms of roughness, defects and other contamination.

[0094] Whatever the mode of implementation of the method, at the end of step d), the intermediate structure 150 has a front face 10b on the side of the useful layer 10, a rear face 30b on the side of the support substrate 30, and an encapsulated film 2' between the useful layer 10 and the support substrate 30. Note that the encapsulated film 2' corresponds to the film 2 when the latter has only been deposited on one of the free faces to be assembled 10a, 30a, or corresponds to the two films 2 deposited respectively on the useful layer 10 and on the support substrate 30.

[0095] The manufacturing method according to the invention then comprises a step e) of annealing the intermediate structure 150 at a temperature between 1200°C and 2000°C, preferably around 1700°C, so as to cause the segmentation of the encapsulated film 2' in the form of nodules 21 and the diffusion of the dopants of the support substrate 30 (very heavily doped) in the direct contact regions 22 and possibly in the nodules 21. Step e) results in the formation of the semiconductor structure 100 with its interface zone 20 between the support substrate 30 and the useful layer 10, said interface zone 20 including said nodules 21 and said direct contact regions 22 ([Fig.2e]).

[0096] The annealing temperature of step e) is chosen such that the system, including the encapsulated film 2' and the semiconductor surfaces of the useful layer 10 and the support substrate 30 in contact with said film 2', will optimize its surface energy by agglomerating the encapsulated film 2' in the form of nodules 21 and by creating direct contact regions 22 between the semiconductor surfaces respectively of the useful layer 10 and the support substrate 30. This temperature is also defined to allow the closure of a bonding interface in the direct contact regions 22, between the monocrystalline silicon carbide of the useful layer 10 and the polycrystalline silicon carbide of the support substrate 30. In addition, the annealing temperature is capable of diffusing the dopants of the support substrate 30 into the direct contact regions 22 and potentially into the nodules 21 (in particular when these are made of material semiconductor).

[0097] Given the steep gradient of dopant concentration between the useful layer 10 and the support substrate 30 (which results from the relationship linking the first Ci and second C2 concentrations, illustrated on the curve of [Fig.5]), the dopants diffuse very efficiently in the direction of the useful layer 10 and a segregation phenomenon occurs at the interfaces present in the interface zone 20, namely the interface between the monocrystalline SiC and the polycrystalline SiC, at each direct contact region 22, and the interface between the material of the nodules 21 and the polycrystalline SiC. The quantity of dopants capable of segregating at these interfaces is much greater than the quantity of dopants likely to diffuse into the useful layer (linked to the solubility of the dopant in the monocrystalline SiC). In particular, the interface between mono-SiC and poly-SiC in the direct contact regions 22 can be considered as a very extensive grain boundary on which the dopants are concentrated, preferentially to the volume of the SiC. This interface having a certain roughness (linked in particular to the presence of the poly-SiC grains), we see a distribution of the dopants over a thickness of up to 5 nm on either side of the mono-SiC / poly-SiC interface.

[0098] The material composing the nodules 21 may also have a solubility of the dopants greater than their solubility in the SiC; this is for example the case when the material is silicon, for temperatures higher than its melting temperature.

[0099] A dopant concentration profile along a thickness of the semiconductor structure 100 can be measured by a known technique, for example by SIMS (secondary ion mass spectrometry). The measurement point, in the plane of the interface zone 20, is sufficiently large to integrate and average the profile measurement over the different elements constituting the interface zone 20 (namely, mainly the nodules 21 and the direct contact regions 22).

[0100] The dopant concentration profile of the semiconductor structure 100 is in the form of an abrupt step, the transition of which coincides with the interface zone 20. The abrupt nature reflects the fact that there is no significant diffusion of dopants from the support substrate 30 into the useful layer 10, which is very advantageous in terms of the properties and stability of said layer 10. The profile is furthermore devoid of a doping peak in the interface zone 20 or has a doping peak in the interface zone 20, the extremum of which corresponds to a third dopant concentration, equal to the second dopant concentration at plus or minus 10%.

[0101] The direct contact regions 22 are doped to a level similar to that of the support substrate 30 and have a resistivity less than or equal to 0.01 mohm.cm2, generally giving the interface zone a similar average resistivity.

[0102] The manufacturing method as described therefore makes it possible to obtain a semiconductor structure 100 providing excellent vertical electrical conduction between the useful layer 10 and the support substrate 30, via an interface zone 20 mainly composed of nodules 21 and direct contact regions 22. The diffusion of the dopants of the support substrate 30 (due to the strong gradient of dopant concentrations between the useful layer 10 and the support substrate 30) and their segregation at the level of the different interfaces of the interface zone 20 give the latter a very low resistivity.

[0103] Example of implementation:

[0104] The donor substrate 1 is made of high quality monocrystalline 4H SiC and has a diameter of 150 mm. The donor substrate 1 is N-doped, with a resistivity of the order of 20 mohm.cm (first concentration of Ci dopants: 4.1018 cm 3). It is implanted through its front face, the “C” type face, with hydrogen ions at a dose of 5.1016 cm 2 and an energy of 95 keV. Around the implantation depth, a buried fragile plane 11 is thus defined, delimiting with the front face 10a of the donor substrate 1, the useful layer 10.

[0105] The support substrate 30 is made of polycrystalline SiC 3C, of ​​the same diameter as the donor substrate 1. It is N-doped, with a resistivity of the order of 3 mohm.cm (i.e. a second concentration of C2 dopants of 5.1020 cm 3).

[0106] The two substrates 1, 30 undergo cleaning sequences to remove particles and other surface contamination. The sequences are preferably chosen so that the surfaces of the substrates 1, 30 do not undergo oxidation (absence of native oxide).

[0107] The substrates 1, 30 are introduced into a first deposition chamber, integrated into direct bonding equipment. A silicon film 2 with a thickness of 10 nm is deposited on each of the front faces 10a, 30a (free faces to be assembled) of the substrates 1, 30, under vacuum, at 106 Pa and room temperature, by sputtering. The substrates 1, 30 are then introduced into a second bonding chamber, to be assembled at their front faces 10a, 30a, by bringing the films 2 deposited respectively onto the donor substrate 1 and onto the support substrate 30 into direct contact. The atmosphere in the bonding chamber is the same as that in the deposition chamber, which avoids any oxidation or passivation of the surface of the films 2.

[0108] After assembly, the bonded assembly 200 comprises the donor substrate 1 bonded to the support substrate 30 via a bonding interface 15, and the encapsulated film 2' formed from the two films 2 deposited and buried between the two substrates 1, 30. The encapsulated film 2' has a thickness of the order of 20 nm.

[0109] The bonded assembly 200 is subjected to a heat treatment to cause separation at the buried fragile plane 11, at a temperature between 800°C and 1000°C for a few minutes to a few hours. The intermediate structure 150 is then obtained, including a useful layer 10 having a thickness of 500 nm, arranged on the encapsulated film 2', itself arranged on the support substrate 30. Cleaning and polishing sequences are applied so as to restore the correct level of defectivity and roughness to the surface 10b of the useful layer 10.

[0110] Finally, an annealing at 1700°C for 30 min is applied to the intermediate structure 150, previously provided with a protective layer on its front face 10b (also free face 10b of the useful layer 10 in the intermediate structure 150). At the end of this annealing, the structure 100 according to the invention is obtained: the interface zone 20 formed of silicon nodules 21 and direct contact regions 22, between useful layer 10 and support substrate 30, gives the structure 100 excellent vertical electrical conductivity (average resistivity of the interface zone of the order of 0.01 mohm.cm2) due to the segregation of dopants from the support substrate 30 to the different interfaces of the interface zone 20.

[0111] The nodules 21 in this structure 100 have a thickness of the order of 200 nm and an average diameter of the order of 100 nm to 1 pm. The coverage rate of the direct contact regions 22, in a median plane of the interface zone 20 is of the order of 80%. The dopant concentration profile according to the thickness of the semiconductor structure 100 is in the form of an abrupt step, without significant modification of the uniform concentration profile of the useful layer 10.

[0112] The invention is not limited to the embodiments described and variant embodiments may be made without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Semiconductor structure (100) based on silicon carbide comprising: - a useful layer (10) of monocrystalline silicon carbide having a first concentration (Ci) of dopants uniform over its thickness, - a support substrate (30) of polycrystalline silicon carbide having a second concentration (C2) of dopants uniform over its thickness, the second concentration (C2) being linked to the first concentration (Ci) by the following relationship: C2 > N2 x exp(-Ci / Ni) with Ni = 2.85.1018 cm 3 and N2 = 5.40.1020 cm 3, - an interface zone (20), between the support substrate (30) and the useful layer (10), comprising nodules (21) and direct contact regions (22) between the useful layer (10) and the support substrate (30), the nodules (21) comprising a metallic or semiconductor material distinct from silicon carbide, the interface zone (20) having an average resistivity less than or equal to 0.01 mohm.cm2, a dopant concentration profile according to a thickness of the semiconductor structure (100): - appearing in the form of a step, and - being devoid of a doping peak in the interface zone (20), or - having a doping peak in the interface zone (20), the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration at plus or minus 10%.

2. Semiconductor structure (100) according to one of the preceding claims, in which the resistivity of the support substrate is less than or equal to 10 mohm.cm, 5 mohm.cm, or even 3 mohm.cm, or even 2 mohm.cm.

3. Semiconductor structure (100) according to one of the preceding claims, in which the interface zone has a thickness less than or equal to 200 nm.

4. Semiconductor structure (100) according to one of the preceding claims, in which: - the metallic material of the nodules (21) is chosen from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper, or - the semiconductor material of the nodules (21) is chosen from silicon, germanium, carbon, III-V compounds such as gallium nitride or other compounds formed from these materials.

5. Method for manufacturing a semiconductor structure (100) based on silicon carbide comprising the following steps: a) providing a useful layer (10) of monocrystalline silicon carbide having a free face to be assembled and a first dopant concentration (Ci) uniform over its thickness, b) providing a support substrate (30) of polycrystalline silicon carbide having a free face to be assembled, a second dopant concentration (C2) uniform over its thickness, the second concentration (C2) being linked to the first concentration (Ci) by the following relationship: C2 > N2 x exp(-Ci / Ni) with Ni = 2.85.1018 cm 3 and N2 = 5.40.1020 cm3, c) depositing a film (2) of a metallic or semiconductor material distinct from the silicon carbide having a thickness less than or equal to 20 nm, on the free face to be assembled of the layer useful (10) and / or on the free face to be assembled of the support substrate (30),d) forming an intermediate structure (150), comprising direct assembly of the free faces to be assembled respectively of the useful layer (10) and the support substrate (30), the intermediate structure (150) including an encapsulated film (2') derived from the film(s) (2) deposited during step c), e) annealing the intermediate structure (150) at a temperature between 1200°C and 2000°C, to form the semiconductor structure (100) comprising an interface zone (20) which includes nodules (21) resulting from the segmentation of the encapsulated film (2') and direct contact regions (22) between the thin layer (10) and the support substrate (30), - the interface zone (20) having an average resistivity less than or equal to 0.01 mohm.cm2, - a dopant concentration profile according to a thickness of the semiconductor structure (100) in the form of a step,and being devoid of a doping peak in the interface zone (20) or having a doping peak in the interface zone (20), the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration (C2) at plus or minus 10%.,

6. Manufacturing method according to claim 5, wherein step a) comprises an implantation of light species in a donor substrate (1) made of monocrystalline silicon carbide, to form a fragile plane buried (11) which delimits, with a front face of the donor substrate (1), the useful layer (10).

7. Manufacturing method according to one of claims 5 and 6, in which step d) comprises, after the direct assembly giving rise to a bonded assembly (200) comprising the donor substrate (1) and the support substrate (30), a separation at the level of the buried fragile plane (11), to form on the one hand the intermediate structure (150) comprising the useful layer (10), the encapsulated film (2') and the support substrate (30), and on the other hand, the remainder of the donor substrate (1”).

8. Manufacturing method according to one of claims 5 to 7, in which, before step c), the free face to be assembled of the thin layer (10) has a monocrystalline surface, free of amorphized zones or zones damaged by doping or activation by bombardment, and the free face to be assembled of the support substrate (30) has a polycrystalline surface, free of amorphized zones or zones modified by doping or activation by bombardment.

9. Manufacturing method according to one of claims 5 to 8, comprising a step of epitaxial growth of an additional layer of monocrystalline silicon carbide on the useful layer (10) of the semiconductor structure (100).

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