Frequency divider circuit

Abstract

Frequency Divider Circuit This description concerns a frequency divider circuit (200) comprising: - a first flip-flop (201); - a first output amplifier (202) having at least one input (+, -) connected to at least one output (Q+, Q-) of said first flip-flop (201); - a second flip-flop (203) having at least one input (D+, D-) connected to at least one output (OUT+, OUT-) of said first output amplifier (202); - a second output amplifier (204) having at least one input (+, -) connected to at least one output (Q+, Q-) of said second flip-flop (203), and having at least one output (OUT+, OUT-) connected to an input (D+, D-) of said first flip-flop (201). Figure for the abbreviation: Fig. 2

Description

Title of the invention: Frequency divider circuit technical field

[0001] This description relates generally to electronic circuits and devices, and more particularly to circuits and devices adapted for processing radio frequency signals. This description relates more specifically to a frequency divider circuit. Previous technique

[0002] Radio frequency signals have a multitude of uses today such as radiocommunication, systems for detecting the presence and / or speed of objects, certain medical devices, household appliances, etc.

[0003] For this purpose, it may be useful to perform operations on these radio frequency signals, such as, for example, operations concerning the frequency of a radio frequency signal.

[0004] It would be desirable to be able to improve, at least in part, certain aspects of known electronic systems adapted to apply operations to one or more radio frequency signals. Summary of the invention

[0005] There is a need for electronic systems and devices adapted to apply operations to radio frequency signals more efficiently.

[0006] There is a need for more efficient frequency divider circuits receiving radio frequency signals.

[0007] There is a need for frequency divider circuits receiving radio frequency signals having a better output amplitude.

[0008] There is a need for frequency divider circuits receiving radio frequency signals having attenuated phase noise.

[0009] An embodiment overcomes all or part of the disadvantages of known electronic devices adapted to apply operations to radio frequency signals.

[0010] An embodiment overcomes all or part of the disadvantages of known frequency divider circuits receiving radio frequency signals.

[0011] One embodiment provides a frequency divider circuit comprising: - a first shift; - a first output amplifier having at least one input connected to at least one output of said first flip-flop; - a second flip-flop having at least one input connected to at least one output of said first output amplifier; - a second output amplifier having at least one input connected to at least one output of said second flip-flop, and having at least one output connected to an input of said first flip-flop.

[0012] According to one embodiment, the circuit further comprises a first capacitor, one terminal of which is connected to at least one output of said first output amplifier.

[0013] According to one embodiment, the circuit further comprises a second capacitor, one terminal of which is connected to at least one output of said second output amplifier.

[0014] According to one embodiment, the circuit is adapted to receive a first signal.

[0015] According to one embodiment, said first flip-flop comprises at least one terminal of a clock adapted to receive said first signal.

[0016] According to one embodiment, said second flip-flop includes at least one clock terminal adapted to receive said first signal.

[0017] According to one embodiment, the first signal is a radio frequency signal.

[0018] According to one embodiment, the circuit is adapted to divide the frequency of said first signal in pairs.

[0019] According to one embodiment, said first flip-flop, said second flip-flop, said first output amplifier, and said second output amplifier are powered by the same supply voltage.

[0020] According to one embodiment, said first flip-flop, said second flip-flop, said first output amplifier, and said second output amplifier receive the same reference voltage.

[0021] According to one embodiment, the reference voltage is ground. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] [Fig.1] represents, very schematically and in block form, an embodiment of a frequency divider circuit;

[0024] [Fig.2] represents, partially in block form, an electrical diagram of the embodiment of a frequency divider circuit of [Fig.1];

[0025] [Fig.3] represents an electrical diagram of a flip-flop of the embodiment of [Fig.2];

[0026] [Fig.4] represents an electrical diagram of an output amplifier of the embodiment of [Fig.2];

[0027] [Fig. 5] represents, partially in block form, an electrical diagram of a variant of the embodiment of a frequency divider circuit of [Fig. 2]; and

[0028] [Fig.6] represents an electrical diagram of a flip-flop of the embodiment of [Fig.5]. Description of the implementation methods

[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0034] In the following description, a radio frequency signal, or RF signal, is a periodic electromagnetic signal whose frequency is between 3 kHz and 300 GHz.

[0035] The embodiments described below relate to a circuit adapted for processing radio frequency signals, and in particular a frequency divider circuit adapted to receive a radio frequency signal as input and to provide, as output, two radio frequency signals whose frequency is equal to a fraction of the frequency of the input signal. The case studied here is more precisely a frequency divider circuit adapted to divide the frequency of an input signal by two.

[0036] A frequency divider circuit is generally associated with output amplifiers to amplify the output signals. However, these combinations often exhibit output amplitudes that are too low, impacting the phase noise of circuits downstream of the frequency divider. The embodiments described below aim to improve the output amplitudes and reduce the phase noise of the output signals.

[0037] For this purpose, the embodiments described below relate to a divider circuit of frequency at which the output amplifiers are directly integrated. Two embodiments of such circuits are described in relation to figures 1, 2 and 5.

[0038] Fig. 1 represents, very schematically and in block form, an embodiment of a frequency divider circuit 100 (f / 2).

[0039] As described previously, the frequency divider circuit 100 consists of the elements of a frequency divider circuit and two output amplifiers. Two detailed examples of the circuit 100 are described with reference to Figures 2 and 5.

[0040] The circuit 100 comprises two input terminals IN+ and IN- between which an input signal is applied. More particularly, the two input terminals IN+ and IN- are connected to input nodes IN100+ and IN100- adapted to receive an input radio frequency signal of frequency f.

[0041] The circuit 100 further comprises four output terminals I+, I-, Q+ and Q- providing the quadrature phase (I, Q) output signals of the circuit 100. More specifically, the two output terminals I+ and I- are connected to output nodes OUT100-I+ and OUT100-L adapted to provide a radio frequency output signal with a frequency of f / 2. The two output terminals Q+ and Q- are connected to output nodes OUT100-Q+ and OUT100-Q- adapted to provide a radio frequency output signal with a frequency of f / 2 corresponding to the quadrature input signal.

[0042] Output loads are represented in [Fig. 1] by parallel RC circuits, that is, circuits comprising a resistor connected in parallel with a capacitor. More specifically, the output load at the output nodes OUT100-1+ and OUT100-1- comprises a resistor RI connected between the nodes OUT100-1+ and OUT100-1-, and a capacitor CI connected between the nodes OUT100-1+ and OUT100-1-. Similarly, the output load at the output nodes OUT100-Q+ and OUT100-Q- comprises a resistor RQ connected between the nodes OUT100-Q+ and OUT100-Q-, and a capacitor CQ connected between the nodes OUT100-Q+ and OUT100-Q-.

[0043] The circuit 100 further includes two supply terminals, VDD and GND. The VDD supply terminal is adapted to receive a VDD supply voltage. The GND supply terminal is adapted to receive a GND reference voltage, for example, ground.

[0044] The circuit 100 further comprises terminals receiving bias currents and voltages. These bias currents and voltages are described in more detail in relation to [Fig.2].

[0045] [Fig.2] represents, partially in block form, an embodiment of a frequency divider circuit 200 of the type of the circuit 100 described in relation to [Fig.1].

[0046] As described previously, the frequency divider circuit 200 comprises two The IN200+ and IN200- input terminals are designed to receive a SigRF200 radio frequency input signal. Circuit 200 also includes two output terminals, OUT200-I+ and OUT200-I-, designed to provide a first SigRF200-I output signal with a frequency equal to half the frequency of the SigRF200 input signal. Circuit 200 further includes two output terminals, OUT200-Q+ and OUT200-Q-, designed to provide a second SigRF200-Q output signal in quadrature phase with the first SigRF200-I output signal. Circuit 200 also receives the supply voltage VDD and the reference voltage GND.

[0047] The frequency divider circuit 200 comprises: - a 201 toggle (CML LATCH); - an output amplifier 202 (BUFFER I); - a 203 toggle switch (CML LATCH); and - a 204 output amplifier (BUFFER Q).

[0048] Flip-flops 201 and 203 are CML (Current Mode Logic) flip-flops. A detailed example of flip-flops 201 and 203 is described in relation to [Fig. 3]. Flip-flops 201 and 203 each have the following terminals: - two input terminals D+ and D-; - two output terminals Q+ and Q-; - two clock terminals Clk+ and Clk-; - a bias terminal; and - two power supply terminals VDD and GND.

[0049] The clock terminals Clk+ and Clk- of flip-flops 201 and 203 receive the SigRF200 input radio frequency signal.

[0050] The bias terminal Bias of the flip-flop 201 receives a bias voltage Vbias201. The bias terminal Bias of the flip-flop 203 receives a bias voltage Vbias203. According to one example, the bias voltages Vbias201 and Vbias203 are identical and are provided by a current mirror not shown in [Fig.2].

[0051] The VDD supply terminals of flip-flops 201 and 203 both receive the VDD supply voltage. Similarly, the GND supply terminals of flip-flops 201 and 203 both receive the GND reference voltage.

[0052] Output amplifiers 202 and 204 each have the following terminals: - two input terminals + and - ; - two output terminals OUT+ and OUT-; - a bias terminal; and - two power supply terminals VDD and GND.

[0053] A detailed example of amplifiers 202 and 204 is described in relation to the [Fig.4].

[0054] The bias terminal Bias of the amplifier 202 receives a bias current Ibias202. The bias terminal Bias of the amplifier 204 receives a bias current Ibias204. In one example, the bias currents Ibias202 and Ibias204 are identical.

[0055] The VDD supply terminals of amplifiers 202 and 204 both receive the VDD supply voltage. Similarly, the GND supply terminals of amplifiers 202 and 204 both receive the GND reference voltage.

[0056] According to one embodiment, the output terminals Q+ and Q- of the flip-flop 201 are connected, preferably connected, to the input terminals + and - of the output amplifier 202. In other words, the output terminal Q+ of the flip-flop 201 is connected, preferably connected, to the input terminal + of the output amplifier 202, and the output terminal Q- of the flip-flop 201 is connected, preferably connected, to the input terminal - of the output amplifier 202.

[0057] According to one embodiment, the output terminals OUT+ and OUT- of the output amplifier 202 provide the first output signal SigRF200-I, but are also connected, preferably connected, to the input terminals D+ and D- of the flip-flop 203. In other words, the output terminal OUT+ of the amplifier 202 is connected, preferably connected, to the input terminal D+ of the flip-flop 203, the output terminal OUT- of the amplifier 202 is connected, preferably connected, to the input terminal D- of the flip-flop 203.

[0058] According to one embodiment, the output terminals Q+ and Q- of the flip-flop 203 are connected, preferably connected, to the input terminals + and - of the output amplifier 204. In other words, the output terminal Q+ of the flip-flop 203 is connected, preferably connected, to the input terminal + of the output amplifier 204, and the output terminal Q- of the flip-flop 203 is connected, preferably connected, to the input terminal - of the output amplifier 204.

[0059] According to one embodiment, the output terminals OUT+ and OUT- of the output amplifier 204 provide the second output signal SigRF200-Q, but are also connected, preferably connected, to the input terminals D+ and D- of the flip-flop 201. In other words, the output terminal OUT+ of the amplifier 204 is connected, preferably connected, to the input terminal D+ of the flip-flop 201, the output terminal OUT- of the amplifier 204 is connected, preferably connected, to the input terminal D- of the flip-flop 201.

[0060] One advantage of this embodiment is that by integrating the output amplifiers 202 and 204 into the loop formed by the flip-flops 201 and 204, the circuit 200 exhibits a lower output impedance. In other words, the output signals SigRF200-I and SigRF200-Q have a higher amplitude, which reduces phase noise in circuits downstream of the 200 circuit.

[0061] Fig. 3 represents a practical example of a flip-flop 300 of the type of flip-flops 201 and 203 described in relation to Fig. 2.

[0062] For example, flip-flop 300 consists of metal-oxide-semiconductor field-effect transistors (MOSFETs). Furthermore, flip-flop 300 consists of N-channel MOS transistors. A person skilled in the art would be able to adapt the circuits forming flip-flop 300 without difficulty to use P-channel MOS transistors.

[0063] Like flip-flops 201 and 203, flip-flop 300 includes the following terminals: - two input terminals D+ and D-; - two output terminals Q+ and Q-; - two clock terminals Clk+ and Clk-; and - two power supply terminals VDD and GND.

[0064] The flip-flop 300 comprises two NMOS transistors T301 and T302 whose gates are connected to the input terminals D+ and D- of the flip-flop 300. More specifically, the gate of transistor T301 is connected, preferably connected, to the input terminal D+, and the gate of transistor T302 is connected, preferably connected, to the input terminal D-. The sources of transistors T301 and T302 are connected, preferably connected, together and to a node A301. The drain of transistor T301 is connected, preferably connected, to the output terminal Q+ of the flip-flop 300. The drain of transistor T302 is connected, preferably connected, to the output terminal Q- of the flip-flop 300.

[0065] The flip-flop 300 further includes two resistors R301 and R302 connecting the output terminals Q+ and Q- to the supply terminal VDD. More specifically, one terminal of resistor R301 is connected, preferably connected, to the output terminal Q+, and a second terminal of resistor R301 is connected, preferably connected, to the supply terminal VDD. Similarly, one terminal of resistor R302 is connected, preferably connected, to the output terminal Q-, and a second terminal of resistor R302 is connected, preferably connected, to the supply terminal VDD.

[0066] The flip-flop 300 further comprises two NMOS transistors T303 and T304 whose drains and gates are connected to the output terminals Q+ and Q-. More specifically, the drain of transistor T303 and the gate of transistor T304 are connected, preferably connected, together and to the output terminal Q+. The drain of transistor T304 and the gate of transistor T303 are connected, preferably connected, together and to the output terminal Q-. In addition, the sources of transistors T303 and T304 are connected, preferably connected, together and to a node B301.

[0067] The flip-flop 300 further comprises an NMOS transistor T305 and a capacitor C301 connected to the clock terminal Clk+. More specifically, one terminal of capacitor C301 is connected, preferably connected, to the clock terminal Clk+, and a second terminal of capacitor C301 is connected, preferably connected, to the gate of transistor T305. The drain of transistor T305 is connected, preferably connected, to node A301, and the source of transistor T305 is connected, preferably connected, to the power supply terminal GND.

[0068] The flip-flop 300 further includes a resistor R303 connecting the gate of the transistor T305 to a node providing a bias voltage Vbias300. More particularly, a first terminal of the resistor R303 is connected, preferably connected, to the gate terminal of the transistor T305, and a second terminal of the resistor R303 is connected, preferably connected, to the node providing the bias voltage Vbias300.

[0069] The flip-flop 300 further comprises an NMOS transistor T306 and a capacitor C302 connected to the clock terminal Clk-. More specifically, one terminal of capacitor C302 is connected, preferably connected, to the clock terminal Clk-, and a second terminal of capacitor C302 is connected, preferably connected, to the gate of transistor T306. The drain of transistor T306 is connected, preferably connected, to node B301, and the source of transistor T306 is connected, preferably connected, to the power supply terminal GND.

[0070] The flip-flop 300 further includes a resistor R304 connecting the gate of the transistor T306 to a node providing the bias voltage Vbias300. More particularly, a first terminal of the resistor R304 is connected, preferably connected, to the gate terminal of the transistor T306, and a second terminal of the resistor R304 is connected, preferably connected, to the node providing the bias voltage Vbias300.

[0071] Fig. 4 represents a practical example of an output amplifier 400 of the type of output amplifiers 202 and 204 described in relation to Fig. 2.

[0072] As an example, amplifier 400 consists of MOS transistors, and more specifically NMOS transistors. A person skilled in the art would be able to adapt the circuits forming amplifier 400 to use PMOS transistors without difficulty.

[0073] Like amplifiers 202 and 204, amplifier 400 includes the following terminals: - two input terminals + and - ; - two output terminals OUT+ and OUT-; - a bias terminal; and - two power supply terminals VDD and GND.

[0074] The output amplifier 400 comprises two NMOS transistors T401 and T402 of which The gates are connected to the + and - input terminals of amplifier 400. More specifically, the gate of transistor T401 is connected, preferably connected, to the + input terminal, and the gate of transistor T402 is connected, preferably connected, to the input terminal. The drains of transistors T401 and T402 are connected, preferably connected, together and to the VDD supply terminal. The source of transistor T401 is connected, preferably connected, to the OUT+ output terminal of amplifier 400. The source of transistor T402 is connected, preferably connected, to the OUT- output terminal of amplifier 400.

[0075] The amplifier 400 further includes a capacitor C401 connecting the gate terminal of transistor T401 to a node A401. More particularly, a first terminal of capacitor C401 is connected, preferably connected, to the gate terminal of transistor T401, i.e. to the input terminal +, and a second terminal of capacitor C401 is connected, preferably connected, to node A401.

[0076] The amplifier 400 further includes a capacitor C402 connecting the gate terminal of transistor T401 to a node B401. More particularly, a first terminal of capacitor C402 is connected, preferably connected, to the gate terminal of transistor T402, i.e. to the input terminal, and a second terminal of capacitor C402 is connected, preferably connected, to node B401.

[0077] The amplifier 400 further comprises NMOS transistors T408 and T409 forming a current mirror that constitutes a current source for the amplifier 400. The drain of transistor T408 is connected, preferably connected, to the output terminal OUT+, and the source of transistor T408 is connected, preferably connected, to the GND terminal. The drain of transistor T409 is connected, preferably connected, to the output terminal OUT-, and the source of transistor T409 is connected, preferably connected, to the GND terminal. The gate of transistor T408 is connected, preferably connected, to node B401. The gate of transistor T409 is connected, preferably connected, to node A401.

[0078] The amplifier 400 further comprises two resistors R401 and R402 connected in series between nodes B401 and A401. More specifically, one terminal of resistor R401 is connected, preferably connected, to node B401, and a second terminal of resistor R401 is connected, preferably connected, to node D401. One terminal of resistor R402 is connected, preferably connected, to node D401, and a second terminal of resistor R402 is connected, preferably connected, to node A401.

[0079] The amplifier 400 further comprises a capacitor C403 and a transistor T411. The capacitor C403 connects node D401 to the GND terminal. One terminal of capacitor C403 is connected, preferably connected, to node D401, and a second terminal of capacitor C403 is connected, preferably connected, to the GND terminal. The drain and gate of transistor T411 are connected, preferably connected, together and to the Bias terminal and to node D401, and the source of transistor T411 is connected, preferably connected, to the GND terminal.

[0080] Fig. 5 represents, partially in block form, another embodiment of a frequency divider circuit 500 of the type of circuit 100 described in relation to Fig. 1.

[0081] The frequency divider circuit 500 is similar to the frequency divider circuit 200 described in relation to [Fig. 2]. The elements common to circuits 200 and 500 are not described again in detail here, and only the differences between circuits 200 and 500 are highlighted.

[0082] Thus, like circuit 200, circuit 500 comprises flip-flops 501 and 503 and output amplifiers 202 and 204 assembled as described in relation to [Fig. 2]. Flip-flops 501 and 503 are very similar to flip-flops 201 and 203 described in relation to [Fig. 2], and include, in particular, the same connection terminals. Flip-flops 501 and 503 differ from flip-flops 201 and 203 in that they also include a Bias2 terminal for applying a second bias voltage. A detailed example of flip-flops 501 and 503 is described in relation to [Fig. 6].

[0083] The circuit 500 further includes capacitive output connections. For this purpose, the circuit 500 includes capacitors C501, C502, C503 and C504 arranged at the outputs of the output amplifiers 202 and 204.

[0084] More specifically, the circuit 500 further comprises capacitors C501 and C502 connecting the output terminals OUT+ and OUT- of the output amplifier 202 to the output nodes OUT500-I+ and OUT500-L of circuit 500. In other words, a first terminal of capacitor C501 is connected, preferably connected, to the OUT+ terminal of the amplifier 202, and a second terminal of capacitor C501 is connected, preferably connected, to the OUT500-I+ node and to the D+ terminal of the flip-flop 503. Similarly, a first terminal of capacitor C502 is connected, preferably connected, to the OUT- terminal of the amplifier 202, and a second terminal of capacitor C502 is connected, preferably connected, to the OUT500-L node and to the D+ terminal of the flip-flop 503.

[0085] Similarly, the circuit 500 further includes capacitors C503 and C504 connecting the output terminals OUT+ and OUT- of the output amplifier 202 to the output nodes OUT500-Q+ and OUT500-Q- of circuit 500. In other words, one terminal of capacitor C503 is connected, preferably connected, to the OUT+ terminal of the amplifier 202, and a second terminal of capacitor C503 is connected, preferably connected, to the OUT500-Q+ node and to the D+ terminal of the flip-flop 501. Similarly, one terminal of capacitor C504 is connected, preferably connected, to the OUT- terminal of the amplifier 202, and a second terminal of the capacitor C504 is connected, preferably connected, to the OUT500-Q- node and to the D- terminal of the 501 flip-flop.

[0086] Fig. 6 represents a practical example of a 600 flip-flop of the type of flip-flops 501 and 503 described in relation to Fig. 2.

[0087] The 600 flip-flop is similar to the 300 flip-flop described in relation to [Fig. 3]. The elements common to the 300 and 600 circuits are not described again in detail here, and only the differences between the 300 and 600 circuits are highlighted.

[0088] Thus, like the 300 flip-flop, the 600 flip-flop includes transistors T301 to T306, resistors R301 to R304 and capacitors C301 and C302 arranged as described in relation to [Fig.3].

[0089] The flip-flop 600 further comprises biasing resistors R601 and R602 for biasing the gates of transistors T301 and T302. More specifically, resistor R301 comprises a first terminal connected, preferably connected, to the gate terminal of transistor T301 and a second terminal connected, preferably connected, to a node providing a bias voltage VbiasôOO. Resistor R302 comprises a first terminal connected, preferably connected, to the gate terminal of transistor T302 and a second terminal connected, preferably connected, to the node providing the bias voltage VbiasôOO. In one example, the bias voltage VbiasôOO is different from the bias voltage Vbias300. According to one example, the bias voltage VbiasôOO is controlled by a control loop (not shown in [Fig.6]) used to control the voltages applied at the D- and D+ terminals.

[0090] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0091] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. Frequency divider circuit (100; 200; 500) comprising: - a first flip-flop (201; 501); - a first output amplifier (202) having at least one input (+, -) connected to at least one output (Q+, Q-) of said first flip-flop (201; 501); - a second flip-flop (203; 503) having at least one input (D+, D-) connected to at least one output (OUT+, OUT-) of said first output amplifier (202); - a second output amplifier (204) having at least one input (+, -) connected to at least one output (Q+, Q-) of said second flip-flop (203; 503), and having at least one output (OUT+, OUT-) connected to an input (D+, D-) of said first flip-flop (201; 501).

2. A circuit according to claim 1, further comprising a first capacitor (C501, C502) one terminal of which is connected to at least one output (OUT+, OUT-) of said first output amplifier (202).

3. A circuit according to claim 1 or 2, further comprising a second capacitor (C503, C504) one terminal of which is connected to at least one output (OUT+, OUT-) of said second output amplifier (204).

4. Circuit according to any one of claims 1 to 3, adapted to receive a first signal (SigRF200).

5. Circuit according to claim 4, wherein said first flip-flop (201; 501) comprises at least one clock terminal (Clk+, Clk-) adapted to receive said first signal (SigRF200).

6. Circuit according to claim 4 or 5, wherein said second flip-flop (203; 503) comprises at least one clock terminal (Clk+, Clk-) adapted to receive said first signal (SigRF200).

7. A circuit according to any one of claims 4 to 6, wherein the first signal (SigRF200) is a radio frequency signal.

8. Circuit according to any one of claims 4 to 7, being adapted to divide the frequency of said first signal (SigRF200) by two.

9. Circuit according to any one of claims 1 to 8, wherein said first flip-flop (201; 501), said second flip-flop (203; 503), said first output amplifier (202), and said second output amplifier (204) are supplied by the same supply voltage (VDD).

10. Circuit according to any one of claims 1 to 9, wherein said first flip-flop (201; 501), said second flip-flop (203; 503), said first output amplifier (202), and said second output amplifier (204) receive the same reference voltage (GND).

11. A circuit according to claim 10, wherein the reference voltage (GND) is ground.

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