System-on-a-chip with fragmentable chips integrated into a land motor vehicle – Graphics chip

Abstract

The invention relates to a system-on-chip configured for the centralized processing of operating data of a motor vehicle, the system-on-chip being referred to as the centralized system (F2; F3), the centralized system being capable of receiving a plurality of fragmentable chips and at least one basic chip and one graphics chip. FIG. 3

Description

Title of the invention: System-on-chip with fragmentable chips integrated in a land motor vehicle - Graphics chip

[0001] The present invention belongs to the field of electronics on board a motor land vehicle. It relates in particular to a system on chip comprising at least one fragmentable chip, the system being integrated on a motor land vehicle.

[0002] "Land motor vehicle" means any type of vehicle such as a motor vehicle, a moped, an airplane, a train, a motorcycle, a storage robot in a warehouse, etc.

[0003] The term "system on chip" means any complete system embedded on a single integrated circuit. A system on chip forms a complete computer system and comprises substantially all the sub-components necessary for the execution of a given general function, without the system on chip needing to resort to other external components. In one embodiment, a system on chip comprises all the sub-components necessary for the execution of a given general function with the exception of the power supply (battery). In another embodiment, the system on chip comprises exactly all the sub-components necessary for the execution of a given general function. The dimensions of a system on chip are naturally very small compared to a nesting of conventional electronic components, and do not exceed 5 cm in length and / or width. In English, a system on chip is translated as "system on chip", frequently abbreviated to SoC.

[0004] A "fragmentable chip" is an electronic subcomponent integrated on a system on chip and dedicated to a more specific function than the general function provided by a system on chip. In English, a fragmentable chip is translated as "chiplet".

[0005] A fragmentable chip comprises a die, which is an English term that can be translated as elementary component in French, and which is a small rectangular piece resulting from the cutting of a slice of semiconductor material, called a wafer in English, on which an integrated circuit has been manufactured. By extension, "die" designates the integrated circuit itself without its package.

[0006] Historically, the introduction of electronic components into motorized land vehicles has been done by stacking independent electronic systems. Stacking these systems could generate many difficulties, mainly because the data from one system was not understandable to another system of the vehicle.

[0007] To solve this difficulty, it has been proposed to integrate a central high-performance computer grouping together as many computer operations carried out on the vehicle as possible. The electronic circuits of such computers generally include systems on a chip.

[0008] Various functions are performed by a vehicle's high-performance computer, including: - A set of basic functions including, for example, the processing, at the application level, of data exchanged with devices external to the vehicle using different networks (5G for example). - A set of functions related to autonomous driving. "Autonomous driving" of an "autonomous vehicle" means any process capable of assisting the driving of the vehicle. The process may consist of partially or totally steering the vehicle or providing any type of assistance to a natural person driving the vehicle. The process thus covers all autonomous driving, from level 0 to level 5 in the OICA scale, for International Organization of Motor Vehicle Manufacturers. - A set of functions related to infotainment, consisting for example of broadcasting different media (audio, video for example) in the vehicle.

[0009] Depending on the range level and the options chosen in a vehicle, the desired performance for the above-mentioned functions varies. The performance level of the systems on chip integrated in high-performance computers is adapted to the desired performance level for these functions according to a so-called "monolithic" approach.

[0010] The monolithic approach consists of designing a specific system-on-chip for each desired maximum performance level for a function. Thus, for example, designing a system-on-chip for entry-level functions is completely different from designing a system-on-chip for advanced autonomous driving functions.

[0011] The monolithic realization of systems on chip in the field of land motor vehicles, and in particular in the automotive field, poses several problems: - A cost problem: the explosion in computing needs requires either systems-on-chip with large die areas (>300mm2), or a set of systems-on-chip to address the needs. These two options are incompatible with the profitability sought in the automotive sector. - An integration problem: the multiplicity of systems on a chip necessary to address the computational needs requires a multiplicity of high-performance computers to house them, or high-performance computers

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[0017] complex to cool which induce integration problems within the vehicle (for example, currently it is necessary to provide three high-performance computers with five systems on chip for an L3 autonomy level). - A design problem, or scalability: it is necessary to design a system on chip by need (range level / desired function), without possible design synergy between the different systems on chips. - A validation problem: some critical functions such as autonomous driving require high levels of safety, both at the software and hardware levels. However, with the monolithic approach, it is necessary to validate the safety of each system-on-chip (and there are many different ones depending on the desired range / function levels), without the validation work carried out for one of the systems-on-chip being able to be reused by another system-on-chip. The present invention improves the situation. To this end, a first aspect of the invention relates to a system on chip configured for the centralized processing of operating data of a land motor vehicle, the system on chip being hereinafter referred to as a centralized system, the centralized system comprising a basic fragmentable chip and a graphic fragmentable chip, the basic chip comprising: - at least two processors configured to operate in a blocked-step mode, in which each processor executes the same operation at the same time in order to identify an error; - a communication port between fragmentable chips, the port being configured for the transmission and reception of at least one signal between the base chip and the graphics chip, the signal comprising useful data and being configured to be transmitted over a distance of at most 30 millimeters; the graphics chip including: - a generic calculator on a graphics processor capable of performing at least 1.5 Tera floating point operations per second; - a communication port between fragmentable chips, the port being configured for the transmission and reception of the signal between the base chip and the graphics chip, the system further comprising a physical connection of a length less than 30 millimeters between the base chip port and the graphics chip port. The chosen architecture offers the best cost-performance ratio. On the one hand, the basic chip contains the components required to achieve sufficient safety levels. Thus, an ASIL D level can be achieved thanks to the presence of processors configured to operate in locked-step mode. Automotive Safety Integrity Level (ASIL) is a risk classification system defined by ISO 26262 - Functional safety of road vehicles.

[0018] On the other hand, the graphics chip includes the components required to achieve high levels of graphics performance, with the generic calculator on the graphics processor, at lower costs (for example, it is not necessary to make the generic calculator on the graphics processor redundant).

[0019] The design, development and their associated costs of such an improved system-on-chip are thus very largely optimized. Compared to a conventional system where conventional electronic components are not grouped into a component with reduced dimensions (the system-on-chip), the system-on-chip according to the invention greatly simplifies the physical integration within the vehicle.

[0020] In addition, the basic chip provides the basic software functions of the vehicle at a low cost with the right level of security while leaving open the possibility of easily extending the performance of the system on chip. The presence of the very short-range port allows the addition of other fragmentable chips within the system on chip without compromising on performance. Indeed, the short-range ports are optimized to operate at very high speeds with limited consumption.

[0021] In one embodiment, the base chip comprises at least two short-range ports.

[0022] The presence of at least two short-range ports on the base chip presents the best performance-cost compromise. Indeed, the presence of a single port on the base chip would limit the improvements of the system-on-chip to the addition of a single direct connection between a new fragmentable chip and the base chip.

[0023] In one embodiment, the base chip has exactly two fragmentable inter-chip communication ports.

[0024] In one embodiment, the graphics chip further comprises an artificial intelligence accelerator configured to process between 30 and 60 Tera operations per second.

[0025] In one embodiment, the graphics chip further comprises a memory interface configured to receive a double data rate synchronous dynamic random access memory.

[0026] In one embodiment, the memory interface is dedicated to storing graphic data generated by the generic calculator on a graphics processor.

[0027] A second aspect of the invention relates to an electronic circuit comprising the centralized system according to one of the embodiments of the first aspect of the invention.

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[0037] A third aspect of the invention relates to a motor land vehicle comprising the electronic circuit according to the second aspect of the invention. A fourth aspect of the invention relates to a method for centralized processing of operating data of a land motor vehicle, the method being implemented by a system on chip, hereinafter referred to as a centralized system, for the centralized processing of operating data of the vehicle, comprising a basic fragmentable chip and a graphic fragmentable chip, the basic chip comprising: - at least two processors configured to operate in a blocked-step mode, in which each processor executes the same operation at the same time in order to identify an error; - a communication port between fragmentable chips, the port being configured for the transmission and reception of at least one signal between the base chip and the graphics chip, the signal comprising useful data and being configured to be transmitted over a distance of at most 30 millimeters; the graphics chip including: - a generic calculator on a graphics processor capable of performing at least 1.5 Tera floating point operations per second; - a communication port between fragmentable chips, the port being configured for the transmission and reception of the signal between the base chip and the graphics chip, the system further comprising a physical connection between the base chip port and the graphics chip port, the method comprising a step of transmitting the useful data from the base chip to the graphics chip. A fifth aspect of the invention comprises a computer program comprising instructions for implementing the method according to the fourth aspect of the invention, when these instructions are executed by a processor. Other characteristics and advantages of the invention will appear on examining the detailed description below, and the appended drawings in which: [Fig.l] is a diagram illustrating the industrial constraints linked to the development of high-performance computers within a motorized land vehicle according to several embodiments of the invention; [Fig.2] is an overall diagram illustrating electronic architectures of high-performance computers within a motorized land vehicle according to several embodiments of the invention; [Fig.3] is a summary diagram illustrating electronic architectures of high-performance computers within a motorized land vehicle according to several embodiments of the invention;

[0038] [Fig.4] is a schematic diagram illustrating a basic fragmentable chip of a system-on-chip configured for the centralized processing of operating data of a land motor vehicle, according to one embodiment of the invention;

[0039] [Fig.5] is a diagram illustrating a system-on-chip configured for autonomous driving of a land motor vehicle, according to one embodiment of the invention

[0040] [Fig.6] is a diagram illustrating a graphic fragmentable chip of a system on chip, according to an embodiment of the invention;

[0041] [Fig.7] is a diagram illustrating the steps of a method according to a mode of rea lization of the invention.

[0042] The invention is described below in its non-limiting application to the case of a motor vehicle. Other applications, for example on a truck or a moped, are conceivable.

[0043] [Fig.l] is a diagram illustrating the industrial constraints linked to the development of high-performance computers within a land motor vehicle according to several embodiments of the invention.

[0044] The x-axis represents the level of performance required for autonomous driving. The performance required for autonomous driving increases as one moves to the right of the axis.

[0045] "Autonomous driving" of an "autonomous vehicle" means any method capable of assisting the driving of the vehicle. The method may thus consist of partially or totally steering the vehicle or providing any type of assistance to a natural person driving the vehicle. The method thus covers all autonomous driving, from level 0 to level 5 in the OICA scale, for International Organization of Motor Vehicle Manufacturers. An acronym commonly used to designate autonomous driving is AD AS, for advanced driver-assistance Systems in English, or advanced driving assistance system in French.

[0046] The y-axis represents the required performance level for infotainment functions. The required performance for infotainment increases as one moves up the axis. "Infotainment" means any function related to the entertainment of at least one occupant of the vehicle, such as the broadcasting of audio, video or olfactory media. An acronym used to designate infotainment is IVI, for in-vehicle infotainment in English.

[0047] Three performance levels, NTRY, entry-level, HGH, mid-range and PREM for high-end are present. Level L3 / L4 corresponds to level 3 or 4 autonomous driving.

[0048] The diagram shown in [Fig.l] illustrates the relevant combinations of needs IVI and AD AS.

[0049] The foundations of the heart of a centralized architecture, for example with the use of one or more high-performance computers (HPCs), are mainly dictated by the processing / computation needs in AD AS and IVI. Some combinations make little sense (for example, blocks 1 where one function is high-end and the other low-end).

[0050] It is necessary to find the best partitioning of electronic components that meets the needs, and in particular the IVI and AD AS needs. The boundary between the HGH level and L3 / L4 of the AD AS needs is notable and chosen in the following manner: it is defined where the AD AS system needs redundancy with a primary channel and an independent secondary channel (block 5 where operational safety is key).

[0051] The volume aspect of the levels is an essential point for the optimization of this partitioning. Thus the L3 / L4 AD AS and PREM IVI levels, blocks 11, 13 and 15, are not very voluminous while the 9 NTRY / NTRY combination constitutes the bulk of the volume (block 3). Blocks 7, 17 and 19 represent moderate needs.

[0052] [Fig.2] is an overall diagram illustrating electronic architectures high-performance computers within a motorized land vehicle according to several embodiments of the invention.

[0053] [Fig.2] illustrates the different possible electronic configurations of at least an electronic circuit, also called a high-performance computer or HPC, included in the motor vehicle. The details of said circuits are then given with reference to [Fig.3].

[0054] In some configurations, the vehicle comprises only one electronic circuit, for example for electronic circuits 9, 7, 19, 17 or 11. In other configurations, such as configurations 13 and 15, the vehicle comprises several electronic circuits. In configuration 13, the vehicle comprises electronic circuits 23 and 21. In configuration 15, the vehicle comprises electronic circuits 21.

[0055] Each of the electronic circuits comprises in one embodiment at least one memory 27 with double data rate, or DDR for double data rate in English.

[0056] [Fig. 3] is a summary diagram illustrating electronic architectures of high-performance computers within a motorized land vehicle according to several embodiments of the invention.

[0057] In all embodiments of the invention, the vehicle comprises at least one electronic circuit. The electronic circuit comprises at least one system-on-chip configured for the centralized processing of vehicle operating data, said system-on-chip being hereinafter referred to as a centralized system. The centralized system is capable of receiving a plurality of fragmentable chips, and comprises at least one basic fragmentable chip 32 and at least one graphics chip 35 also described with reference to [Fig.4] below.

[0058] Different embodiments corresponding to different possible electronic architectures are described below.

[0059] The electronic circuit 9, for example referenced HPC 0, comprises a system on chip F1 configured for the centralized processing of vehicle operating data, which comprises the chip 32. In one embodiment, F1 only comprises a basic fragmentable chip, the chip 32.

[0060] The electronic circuit 7, for example referenced HPC D, comprises a system on chip F2 configured for centralized processing of vehicle operating data, which comprises chip 32 and a graphic fragmentable chip 35, hereinafter described with reference to [Fig.6].

[0061] The electronic circuit 19, for example referenced HPC E, comprises the system on chip F1 comprising the chip 32, and a system on chip Al configured for autonomous driving of the land motor vehicle. The system Al comprises a fragmentable chip 37 for autonomous driving.

[0062] The electronic circuit 17, for example referenced HPC A, comprises the system on chip F2 comprising the base chip 32 and the graphics chip 35, and the system on chip Al for autonomous driving comprising the chip 37.

[0063] The electronic circuit 21, for example referenced HPC B, comprises the system on chip F2 comprising the chip 32 and the graphics chip 35, and a system on chip A2 configured for autonomous driving. The system A2 comprises four fragmentable chips 37 for autonomous driving.

[0064] The electronic circuit 23, for example referenced HPC C, comprises a system on chip F3 comprising the chip 32 and two graphics chips 35. The circuit 23 further comprises the system on chip A2 configured for autonomous driving and comprises four chips 37 for autonomous driving.

[0065] Thus, depending on the embodiments, the centralized system may or may not include another fragmentable chip than the base chip 32. In all embodiments, the chip 32 includes at least one communication port between fragmentable chips. In an embodiment described below, the base chip includes two communication ports between fragmentable chips. In some of these embodiments, one or both communication ports between fragmentable chips are not connected to other fragmentable chips of the centralized system.

[0066] Each communication port between fragmentable chips is configured for the transmission and reception of at least one signal between the base chip 32 and another fragmentable chip of the centralized system (actually present on the system centralized or not), the signal comprising useful data and being configured to be transmitted over a distance of at most 30 millimeters.

[0067] Signals configured to be transmitted over a distance of at most 30 millimeters can be transmitted with high performance levels and low required energy. The configuration of signals configured to be transmitted over a distance of at most 30 millimeters is known to those skilled in the art and is for example detailed in the UCIe standard: “Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0” and in particular in point 5.0.

[0068] In [Fig. 3], connections between communication ports between fragmentable chips are shown in solid lines (Chplt Com line) and connections between communication ports between systems on chip are shown in dotted lines (SoC Com line). The connections between communication ports between fragmentable chips are therefore not greater than a distance of 30 millimeters.

[0069] “Useful data” means any type of data containing information used by a vehicle functionality.

[0070] In one embodiment, the communication ports between fragmentable chips are UCIe ports, registered trademark, for Universal Chiplet Interconnect Express in English and universal express interconnection for fragmentable chip in French, at least compatible with the UCIe standard: “Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0”.

[0071] In one embodiment, the communication ports between systems on a chip are PCIe ports, registered trademark, for Peripheral Component Interconnect Express in English and express interconnection for peripheral component in French, at least compatible with the PCIe standard: “PCI Express® Base Specification Revision 6.1”.

[0072] In one embodiment, the ports are configured so that the physical interconnection between the base chip and the other fragmentable chip of the centralized system comprises a two-dimensional organic substrate. In one embodiment, each port comprises at least 16 pins for the physical interconnection.

[0073] The foundation of the proposed architecture is based on an HPC with a monolithic fusion system-on-chip (single die) that addresses the NTRE / NTRY level to optimize the cost of this high-volume level. This system-on-chip is built around a "base" die that will be reused in a chiplet approach on subsequent versions. Thus, this "base" die will benefit from additional volume that a monolithic approach per level would not have allowed.

[0074] In addition to the "base" die, the higher levels are covered by the addition of "adas" and "ivi" chiplet(s) to cover the additional adas and infotainment needs respectively. Thus the transition from the entry level to high ne- will require the addition of an additional “adas” or “ivi” chiplet.

[0075] Similarly, the transition from the NTRY / HGH or HGH / NTRY level to HGH / HGH requires the addition of the necessary ivi or adas chiplet.

[0076] Also, PREM / HGH level coverage is made possible by the addition of an additional ivi chiplet, i.e. a combination of a “base” die, an “adas” die and 2 “ivi” dies.

[0077] The transition to the L3 / L4 level requires a significant addition of computing resources to the system, which must be separated into two independent subsystems for safety reasons. This dual need is covered by two HPCs, each offering the combination of four ADAS chiplets, one IVI chiplet and one base chiplet distributed across two SoCs. The advantage of grouping the ADAS chiplets within a single SoC is that it offers a dual advantage: on the one hand, it offers the distribution of the power to be dissipated across two SoCs, but it also allows the range of ADAS SoCs to be developed independently of the rest of the system.

[0078] Other advantages appear in this partitioning of SoCs and HPCs. - Reuse of the HPC housing - Reuse of the database which allows to minimize validation across levels. - Ability to upgrade ADA SoCs faster than the rest of the system

[0079] The size of the 3 chiplets used in this partitioning remains on an optimal yield surface (<200mm2 at 5nm to obtain good yield). In this exercise the target sizes remain below 100mm2.

[0080] [Fig.4] illustrates the basic fragmentable chip 32, according to an embodiment of the invention.

[0081] The chip 32 comprises at least two processors configured to operate in a simultaneous redundancy mode, in which each processor executes the same operation at the same time in order to identify an error.

[0082] This document refers to two processors operating in a simultaneous redundancy mode. This terminology (two processors) is equivalent to a terminology in which a single processor is referred to where the execution cores operate in a locked phase in which each core executes the same operation at the same time in order to identify an error.

[0083] Such simultaneous redundancy processors, also called lockstep mode in English, make ASIL D validation possible, shown in bold in [Fig.4] at block 69. In one embodiment, the simultaneous redundancy mode further comprises physical or software isolation of the clock systems and / or the power supply or even compatibility with a fast wake-up mode.

[0084] Chip 32 includes: - A central processing unit (CPU) block 72 configured to perform a wide variety of operations. In one embodiment, the block 72 comprises a cache memory greater than 12 megabits and / or computing performance between 50 and 500 kdmips, preferably 118 kdmips. The dmips is a unit of measurement of processor performance relating to one million operations per second of the dhrystone type. - A block 74 of a neural processing unit (NPU), comprising an artificial intelligence accelerator configured to process between 10 and 100 Tera operations (Tops) relating to the execution of neural networks dedicated to image recognition per second, preferably 50 Tops. In one embodiment, the NPU comprises a cache memory greater than 15 megabits. - A block 76 of a GPU graphical processing unit, comprising a generic calculator on a graphics processor capable of performing between 100 and 500 billion floating point operations per second (Gflops), preferably 300 Gflops. In one embodiment, the GPU is configured to be compatible with a virtualization mode, that is to say that it can be operated in several independent virtual instances.

[0085] Several embodiments are possible with regard to the integration of the simultaneous redundancy processors. In a preferred embodiment, the chip 32 further comprises a safety block (not shown) comprising the simultaneous redundancy processors which are in charge of operations critical to operational safety (typically the decisions at the origin of the autonomous driving instructions or operations linked to the fusion of data from the sensors for autonomous driving). In one embodiment, the two processors are included in at least one of the components or component blocks 72, 74 and / or 76.

[0086] The chip 32 further comprises at least the two ports 61 and 63 for communication between fragmentable chips. Each communication port between fragmentable chips is configured for the transmission and reception of at least one signal comprising the useful data and configured to be transmitted over a distance of at most 30 millimeters.

[0087] In one embodiment, the chip 32 further comprises at least the two ports 65 and 67 for communication between systems on a chip. In one embodiment, the port 65 is configured for data exchange at a rate of between 8 and 32 GBps and the port 67 for a rate of between 1 and 8 GBps.

[0088] In one embodiment, the base chip 32 further comprises at least one low-speed port 71 for connection with a serial system bus. The serial system bus is for example, CAN type for controller area network. In one embodiment, port 71 has three sub-ports of CAN-FD type, registered trademark, for Controller Area Network Flexible Data-Rate.

[0089] Chip 32 is the most complete of the fragmentable chips presented here because it addresses the AD AS and infotainment domains for the NTRY levels. In one embodiment, chip 32 also includes gateway functions for the vehicle's internal communication networks. In one embodiment, chip 32 also provides the necessary connectivity (I / O) for the NTRY level but also the following ones.

[0090] The chip 32 also provides the high-speed interconnection necessary for the expansion of the system through the ports between systems on chip, for example of the PCIe type, for an interSoC expansion and the two ports 61 and 62 for a multiDie expansion. This interconnection is not necessary at the NTRY level but required for the expansion of the system on the higher levels. This surplus Silicon (and therefore additional cost) is largely offset by the volume effect provided by the higher levels.

[0091] [Fig.5] illustrates the fragmentable chip 37 for autonomous driving, according to one embodiment of the invention.

[0092] The chip 37 comprises at least two processors configured to operate in simultaneous redundancy mode.

[0093] This document refers to two processors operating in a simultaneous redundancy mode. This terminology (two processors) is equivalent to a terminology in which a single processor is referred to where the execution cores operate in a locked phase in which each core executes the same operation at the same time in order to identify an error.

[0094] As for the base chip 32, such simultaneous redundancy processors make possible the ASIL D validation, represented in bold in [Fig.5] at block 84. In one embodiment, the simultaneous redundancy mode further comprises isolation, physical or software, of the clock systems and / or the power supply or even compatibility with a fast wake-up mode.

[0095] Chip 37 includes: - A central processing unit (CPU) block 86 configured to perform a wide variety of operations. In one embodiment, the block 72 comprises a cache memory greater than 6 megabits and / or computing performance between 10 and 200 kdmips, preferably 63 kdmips. - A block 88 of neural processing unit NPU, for neural processing unit in English, comprising an artificial intelligence accelerator configured for process between 50 and 500 tera operations relating to the execution of neural networks dedicated to image recognition per second, preferably 79 tera operations relating to the execution of neural networks dedicated to image recognition per second. In one embodiment, the NPU comprises a cache memory greater than 33 megabits.

[0096] Several embodiments are possible with regard to the integration of the processors with simultaneous redundancy. In a preferred embodiment, the chip 37 further comprises a safety block (not shown) comprising the processors with simultaneous redundancy which are in charge of operations critical with regard to operational safety (typically the decisions at the origin of the autonomous driving instructions or operations linked to the fusion of data from the sensors for autonomous driving). In one embodiment, the two processors are included in at least one of the components or blocks of components 86 and / or 88.

[0097] The chip 37 further comprises at least the two ports 78 and 80 for communication between fragmentable chips. Each communication port between fragmentable chips is configured for the transmission and reception of at least one signal comprising the useful data and configured to be transmitted over a distance of at most 30 millimeters.

[0098] In one embodiment, the chip 32 further comprises a port 82 for communication between systems on a chip.

[0099] Chip 37 provides a set of extensions dedicated to the execution of autonomous driving systems: - Mainly massively parallel computing resources (NPU 74) - High-performance processors (CPU 86) with a good level of security - Means related to vision (not shown, for example with a processor for image signal processing (ISP, for Image Signal Processor in English) - A local DDR memory interface (not shown) to relieve the centralized system of the numerous memory-processor round trips linked to this AD AS activity.

[0100] [Fig.6] illustrates the fragmentable graphics chip 35, according to one embodiment of the invention.

[0101] The chip 35 comprises at least one processor configured to ensure an ASIL B safety level (block 92). Such a safety level involves verification processes of a significant level, but less than for the ASIL D level of the chips 32 and 37. Thus, it is conceivable for an ASIL B level to have error verification processes, or redundancy introduction processes, solely in software. For example, an ASIL B level does not involve specific hardware such as two processors configured to operate in the simultaneous redundancy mode.

[0102] Chip 35 comprises: - A central processing unit (CPU) block 94 configured to perform a wide variety of operations. In one embodiment, block 94 includes a cache memory greater than 19 megabits and / or computing performance between 50 and 500 kdmips, preferably 185 kdmips. - A block 98 of a neural processing unit (NPU), comprising an artificial intelligence accelerator configured to process between 10 and 100 Tera operations (Tops) relating to the execution of neural networks dedicated to image recognition per second, preferably 54 Tera operations relating to the execution of neural networks dedicated to image recognition per second. In one embodiment, the NPU comprises a cache memory greater than 22 megabits. - A GPU block 96, for graphical processing unit in English, comprising a generic calculator on a graphics processor capable of performing between 1 and 5 terabytes of floating point operations per second (Tflops), preferably greater than 1.5 Tflops. In one embodiment, the GPU is configured to be compatible with a virtualization mode, that is to say that it can be operated in several independent virtual instances.

[0103] Several embodiments are possible with regard to the integration of the processor having ASIL B security. In a preferred embodiment, the chip 35 further comprises a security block (not shown) comprising the processor having ASIL B security (typically the operations critical from the cybersecurity point of view). In one embodiment, the ASIL B processor is included in at least one of the components or component blocks 94, 96 and / or 98.

[0104] In one embodiment, the graphics chip further comprises a memory interface configured to receive a double data rate synchronous dynamic random access memory which, in one embodiment, is dedicated to storing graphics data generated by the generic calculator on graphics processor.

[0105] The chip 35 further comprises at least one port 90 for communication between fragmentable chips. The port 90 for communication between fragmentable chips is configured for the transmission and reception of at least one signal comprising the useful data and configured to be transmitted over a distance of at most 30 millimeters.

[0106] Chip 35 thus provides a set of extensions dedicated to the execution of cockpit / infotainment oriented tasks: Mainly graphics processing units (GPUs) Performance processors (CPU performance) and safety (ASIL B). - An NPU for supporting dedicated cockpit artificial intelligence functions. - A local DDR memory interface to offload the centralized system from movements related to the graphic part.

[0107] [Fig.7] is a diagram illustrating the steps of a method according to one embodiment of the invention.

[0108] In the embodiment described here in [Fig.7], a data item Data is transmitted from the basic fragmentable chip 32 to the graphic fragmentable chip 35.

[0109] The method starts at 200 then the data Data is transmitted at a step 202 by 32 to be received at a step 204 by 35. The method then ends at a step 206.

[0110] In one embodiment, the symmetric method, from the graphics fragmentable chip to the base chip, is implemented.

[0111] The present invention is not limited to the embodiments described above as examples; it extends to other variants.

[0112] Thus, an embodiment has been described in which the invention was implemented for a motor vehicle. The invention can however be implemented with any type of land motor vehicle such as a scooter, a train or a motorized wheelbarrow.

[0113] Furthermore, this document refers to two processors operating in a simultaneous redundancy mode. This terminology (two processors) is equivalent to a terminology in which a single processor is referred to where the execution cores operate in a locked phase in which each core executes the same operation at the same time in order to identify an error.

[0114] Furthermore, an embodiment has been described in which the invention is implemented with two fragmentable inter-chip communication ports on the base chip. The invention can, however, be implemented with a single fragmentable inter-chip communication port on the base chip, said port connecting the base chip and the graphics chip.

Claims

Claims

1. System on chip (F2; F3) configured for the centralized processing of operating data of a land motor vehicle, the system on chip being hereinafter referred to as a centralized system, the centralized system comprising a basic fragmentable chip (32) and a graphic fragmentable chip (35), the basic chip comprising: - at least two processors configured to operate in a blocked-step mode, in which each processor executes the same operation at the same time in order to identify an error; - a communication port (61) between fragmentable chips, the port being configured for the transmission and reception of at least one signal between the basic chip and the graphic chip, the signal comprising a useful data item and being configured to be transmitted over a distance of at most 30 millimeters;the graphics chip comprising: - a generic calculator on a graphics processor (GPU) capable of performing at least 1.5 Tera floating point operations per second; - a communication port (90) between fragmentable chips, the port being configured for the transmission and reception of the signal between the base chip and the graphics chip, the system further comprising a physical connection of a length less than 30 millimeters between the port of the base chip and the port of the graphics chip.;

2. A system-on-chip according to claim 1, wherein the base chip comprises exactly two fragmentable inter-chip communication ports (61; 63).

3. A system-on-chip according to one of the preceding claims, wherein the graphics chip further comprises an artificial intelligence accelerator (98) configured to process between 30 and 60 Tera operations per second.

4. System on chip according to one of the preceding claims, in which the graphics chip further comprises a memory interface

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6.

7.

8. configured to receive double data rate synchronous dynamic random access memory. System on chip according to claim 4, wherein the memory interface is dedicated to the storage of graphics data generated by the generic calculator on graphics processor. Electronic circuit (17; 7; 21; 11; 23) comprising the system on chip according to one of the preceding claims. Motor land vehicle comprising the electronic circuit according to claim 6. Method for centralized processing of operating data of a land motor vehicle, the method being implemented by a system on chip, hereinafter referred to as a centralized system, for the centralized processing of operating data of the vehicle, comprising a basic fragmentable chip and a graphic fragmentable chip, the basic chip comprising: at least two processors configured to operate in a locked-step mode, in which each processor performs the same operation at the same time in order to identify an error; a communication port between fragmentable chips, the port being configured for the transmission and reception of at least one signal between the base chip and the graphics chip, the signal comprising useful data and being configured to be transmitted over a distance of at most 30 millimeters; the graphics chip including: - a generic calculator on a graphics processor capable of performing at least 1.5 Tera floating point operations per second; - a communication port between fragmentable chips, the port being configured for the transmission and reception of the signal between the base chip and the graphics chip, the system further comprising a physical connection between the base chip port and the graphics chip port, the method comprising a step of transmitting (202) the data

9. useful from the base chip to the graphics chip. Computer program comprising instructions for implementing the method according to claim 8, when these instructions are executed by a processor (69; 84; 92).

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