Electronic device with cryogenic component and its manufacturing process

Abstract

Title: Electronic Device with Cryogenic Component and Method of Fabrication The invention relates to an electronic device comprising: - a functional zone (C1) comprising a cryogenic component configured to operate at a temperature below 10 K, - a control zone (C2) comprising an electronic control component configured to control the cryogenic component, - a routing zone (C3) comprising a passive structure (22) electrically connected to the cryogenic component and the electronic control component, the passive structure (22) being based on a superconducting material and integrated into a dielectric matrix (13). Advantageously, the dielectric matrix (13) comprises a cavity (52) around the passive structure (22), such that the passive structure (22) is partially suspended in said cavity (52). Figure for the abstract: Fig. 11

Description

Title of the invention: Electronic device with cryogenic component and its manufacturing process technical field

[0001] The present invention relates to the field of cryogenic components and devices, particularly for quantum electronics. Its particularly advantageous application lies in the fabrication of devices comprising functional zones including cryogenic components and control zones including control components linked to the cryogenic components via a routing zone. STATE OF THE ART

[0002] In the field of cryogenic components, operating temperatures are on the order of a few Kelvin (K) or even a few mK. To obtain these operating temperatures, the components are generally placed in dilution or pulsed gas tube cryostats.

[0003] The cooling power of these dilution cryostats is limited by the volume to be cooled. The volume to be cooled is necessarily reduced to obtain sufficient cooling power.

[0004] The compactness of cryogenic devices and / or microsystems integrating cryogenic components is therefore an important issue. The co-integration of cryogenic components (for example, quantum bit components) and control components (for example, CMOS complementary metal-oxide-semiconductor transistors) on the same chip or structure is therefore particularly advantageous for the compactness of the cryogenic device.

[0005] In this context, integrating passive structures into a routing zone interposed between the functional zone containing the cryogenic components and the control zone containing the control components makes it possible to obtain a compact device. These passive structures can be simple routing traces, or passive components designed to improve control and / or readout within the device. One issue related to this arrangement concerns thermal management within the device, between the cryogenic components and the control components. The control components, which for example form a CMOS readout circuit for cryogenic quantum-bit components, heat up during operation.

[0006] The use of passive structures based on one or more superconducting materials makes it possible to eliminate the Joule effect and limit heat transport via the passive structures. The cryogenic components and the control components are thus thermally insulated from each other. The use of passive structures based on superconducting materials also improves the electrical performance of the passive structures and reduces the power consumption of the device.

[0007] Document FR3114443 discloses a solution consisting of mixing, in the routing area, conductive routing traces that provide both thermal and electrical functions with superconducting routing traces that provide only an electrical function. This improves the thermalization of cryogenic components while ensuring good thermal insulation between the cryogenic and control components. However, it has been observed that parasitic thermal conduction between the cryogenic and control components persists. Losses in radio frequency (RF) signals transmitted between the cryogenic and control components have also been observed.

[0008] One object of the present invention is to overcome at least some of these drawbacks.

[0009] In particular, one object of the present invention is to provide a compact cryogenic device that improves thermal insulation between cryogenic components and control components, and / or limits RF losses. Another object of the present invention is to provide a method for manufacturing such a cryogenic device.

[0010] The other objects, features and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0011] To achieve this objective, according to one embodiment, an electronic device is provided comprising at least: - a first so-called functional zone comprising at least one so-called cryogenic component configured to operate at a temperature below 10 K, preferably below 4 K, - a second so-called control zone comprising at least one electronic control component configured to control or interact with at least one cryogenic component, - a third zone, called the routing zone, interposed between the functional zone and the control zone, comprising at least one passive structure electrically connected to at least one cryogenic component on the one hand and / or electrically connected to at least one electronic control component on the other hand, - a dielectric matrix included at least partially within the routing zone.

[0012] As in known solutions, at least one passive structure is based on a or several superconducting materials and is integrated into the dielectric matrix.

[0013] Advantageously, and unlike known solutions, the dielectric matrix comprises at least one cavity around at least one passive structure, such that at least one passive structure is at least partially suspended in said cavity.

[0014] In the course of developing the present invention, it was determined that parasitic thermal conductions and RF losses were partly due to the presence of a dielectric matrix around the passive structures.

[0015] For a given design, creating a cavity in the dielectric matrix around the passive structures advantageously breaks the dielectric continuity. Parasitic thermal conductivity through the dielectric matrix is ​​reduced or even eliminated. RF losses are also reduced or even eliminated.

[0016] The improved thermal and RF insulation also makes it possible to increase the bandwidth of the routing area and the resonant frequencies of the passive structures. This also allows for a relaxation of the constraints on the dimensional design rules of the passive structures. Thanks to the cavity, it is possible, for example, to consider wider superconducting routing traces, which are therefore easier to manufacture using technological processes. Furthermore, the thermal and RF insulation is effective in all spatial directions. This allows for different arrangements of the functional and control areas relative to the routing area, while in all cases benefiting from improved thermal and RF insulation.

[0017] According to one aspect of the invention, a method for making such a device is provided, comprising at least the following steps: - Provide the functional area and the control area, - Form the routing zone by performing at least the following steps: • Form a stack comprising, along a z-direction, a first encapsulation layer, a first sacrificial layer, at least one passive structure based on a superconducting material, a second sacrificial layer forming with the first sacrificial layer a sacrificial layer, a second encapsulation layer, • Form at least one opening in the second encapsulation layer leading into the sacrificial layer, • Remove at least part of the sacrificial layer through said at least one opening, by selectively etching the sacrificial layer with respect to the first and second encapsulation layers, so as to form at least one cavity around the at least one structure passive, - Electrically connect the functional area and / or the control area to at least one passive structure in the routing area.

[0018] The advantages of the device mentioned above apply mutatis mutandis to the method of making the device.

[0019] According to one aspect of the invention, a system is provided comprising the electronic device and a cooling means configured to maintain at least one cryogenic component of the device at a temperature below 10 K, preferably below 4 K. BRIEF DESCRIPTION OF THE FIGURES

[0020] The aims, objects, features and advantages of the invention will become clearer from the detailed description of embodiments thereof, which are illustrated by the following accompanying drawings in which:

[0021] [Fig.1]

[0022] [Fig.2]

[0023] [Fig.3]

[0024] [Fig.4]

[0025] [Fig.5]

[0026] [Fig.6]

[0027] [Fig.7]

[0028] [Fig. 8]

[0029] [Fig.9]

[0030] [Fig. 10]

[0031] [Fig. 11] Figures 1 to 11 schematically illustrate in cross-section the manufacturing steps of an electronic device according to an embodiment of the present invention. Figures 8, 9, and 10 show different manufacturing variants of the electronic device according to the invention.

[0032] [Fig.12A]

[0033] [Fig.12B] Figures 12A, 12B schematically illustrate in top view the formation of support pillars in the electronic device according to an embodiment of the present invention.

[0034] [Fig. 13] The [Fig. 13] schematically illustrates in top view the formation of support walls in the electronic device according to another embodiment of the present invention.

[0035] [Fig.l4A]

[0036] [Fig. 14B] Figures 14A and 14B schematically illustrate, from a top view, different arrangements of the functional, routing, and control areas of the device electronic, according to an embodiment of the present invention.

[0037] [Fig. 15] The [Fig. 15] schematically illustrates in top view an arrangement of the functional, routing and control areas of the electronic device, according to another embodiment of the present invention.

[0038] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, in the schematic diagrams, the dimensions of the various elements and layers are not necessarily representative of reality. DETAILED DESCRIPTION

[0039] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0040] According to one example, the suspended part of at least one passive structure is located on an electrical path between the cryogenic component and the control component.

[0041] According to one example, at least one cavity includes at least one support structure configured to support at least one passive structure within at least one cavity. This enhances the mechanical strength of the device.

[0042] According to one example, the at least one support structure is in the form of a pillar comprising a lower part located below the at least one passive structure and an upper part located on top of the at least one passive structure. This makes it possible to limit the size of the support structure within the cavity.

[0043] According to one example, at least one passive structure is in the form of one of the following: a metallic line, a superconducting line, a transmission line, a power supply line (DC), a connecting line, a resistor, a capacitor, an inductor.

[0044] According to one example, at least one cryogenic component of the functional area is a quantum bit component.

[0045] According to one example, at least one cavity is filled with a neutral gas

[0046] According to one example, at least one passive structure is in contact with the neutral gas.

[0047] According to one example, at least one cavity extends, in projection along a direction main extension of the passive structure, over a distance d greater than or equal to X% of the length L of the passive structure, the length L being taken along this same direction, with X> 30, preferably X> 50.

[0048] According to one example, the functional area is in the form of a first chip and the control area is in the form of a second chip, and the routing area is integrated on a substrate called an interposer, the first and second chips being mounted on the interposer and connected to the routing area respectively by first and second electrical links. This architecture typically corresponds to a heterogeneous integration of chips placed on a substrate integrating the connectors and passive structures, generally called an "interposer" in English.

[0049] According to one example, the routing zone comprises an upper metallic layer configured to be in direct contact with the first and second electrical bonds of the first and second chips, and at least one passive structure based on a superconducting material of the routing zone is located immediately below said upper metallic layer. The at least one passive structure is thus protected by the upper metallic layer. The arrangement of the routing zone immediately below said upper metallic layer further facilitates the practical realization of the cavity around the passive structure. In particular, this limits the number of layers that must be traversed to etch the sacrificial layer around the passive structure.

[0050] According to one example, the formation of at least one opening includes defining a plurality of openings distributed in a network over the routing area, outside of the at least one passive structure projected along the z-direction. This allows the routing area to be meshed around the passive structures, in order to more effectively remove the sacrificial layer. It also allows for the implementation of support structures in the form of pillars at the level of the passive structures.

[0051] According to one example, the selective etching of the sacrificial layer is configured to retain a portion of said sacrificial layer between adjacent openings in the plurality of openings, so as to form at least one support structure directly above at least one passive structure. Controlling the etching speed and / or etching time typically allows portions of the sacrificial layer, for example in the form of pillars, to be retained equidistant from the openings. It is thus possible to form a sub-array of pillars offset by half a grid spacing from the array of openings.

[0052] According to one example, the formation of at least one passive structure includes a definition of a plurality of passive structures forming a first network having a first step p, the plurality of openings forming a second network offset with respect to the first network, in projection along the direction z, and having a second step p2 multiple of the first step p, the offset between the first and second networks preferably corresponding to half of the first step, p / 2.

[0053] According to one example, at least one opening has a section, in a plane perpendicular to the direction z, that is round, square or rectangular.

[0054] According to one example, the sacrificial layer has a dielectric constant less than or equal to 12, preferably less than or equal to 6.

[0055] According to one example, the process further comprises, before the formation of at least one A cavity is formed by a wall with a closed contour around at least one opening in a plane perpendicular to the z-direction. This wall typically prevents lateral etching of the sacrificial layer. Control of the cavity dimensions, determined by the wall's contour, is facilitated. The overall mechanical strength is also improved.

[0056] According to one example, the method further comprises, before the formation of at least one cavity, the formation of at least one wall configured to circumscribe or delimit the at least one cavity within the routing zone. As above, the wall is chosen to exhibit high selectivity to the etching of the sacrificial layer. The wall is therefore not etched and stops the expansion of the cavity. The dimensions of the cavity are thus perfectly controlled.

[0057] According to one example, at least one wall extends in the z-direction from the first encapsulation layer to the second encapsulation layer. The wall may pass through the first encapsulation layer and / or the second encapsulation layer.

[0058] According to one example, said wall corresponds to an interconnection between a first level of electrical conduction, typically a first metallic level M1, located below at least one passive structure, and a second level of electrical conduction, typically a second metallic level M2, located above at least one passive structure. This makes it possible to limit the number of process steps by taking advantage of an advantageous design.

[0059] According to one example, the sacrificial layer is based on SiN produced with NH3 gas, the first and second encapsulation layers are based on SiN produced without NH3, and the selective etching is a wet etching based on dilute hydrofluoric acid.

[0060] According to another example, the sacrificial layer is based on SiN deposited at low temperature, typically at a temperature below 200°C, by plasma-enhanced chemical vapor deposition (PECVD), the first and second encapsulation layers are based on Tetraethyl Orthosilicate (TEOS) precursor silicon oxide deposited at 400°C by PECVD, and the selective etching is a wet etching based on hydrofluoric acid diluted to 1% by volume.

[0061] According to one example, the method further comprises, after the formation of at least one cavity, the formation of a sealing layer, for example polymer-based, configured to plug at least one opening. This prevents condensation and ice formation in the cavity when the device is operating at a cryogenic temperature. This makes it possible to obtain a hermetically sealed cavity, for example under vacuum.

[0062] According to one example, the formation of at least one opening is carried out by engraving anisotropic etching of the sacrificial layer along the z-direction, said method further comprising, before the formation of at least one aperture, the formation of at least one stop pad in the sacrificial layer, directly above the at least one aperture, configured to stop the anisotropic etching, such that the at least one aperture extends within the sacrificial layer up to the at least one stop pad. This facilitates the creation of the apertures. It allows the aperture to be stopped precisely within the sacrificial layer. The contact area between the sacrificial layer and the aperture is increased. The selective etching of the sacrificial layer is more efficient.

[0063] Except in cases of incompatibility, it is understood that all the above optional features can be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features of one aspect of the invention, for example the device or the method, can be adapted mutatis mutandis to the other aspect of the invention.

[0064] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0065] A layer may also be composed of several sub-layers of the same material or of different materials.

[0066] A substrate, stack, layer, "based" on a material A means a substrate, stack, layer comprising only that material A or that material A and possibly other materials, for example alloying elements and / or dopant elements.

[0067] The superconducting state appears when certain metals, such as niobium, or nitrides like niobium nitride or titanium nitride, or alloys like Nb3Ge, are cooled to very low temperatures, below the critical temperature (Te). For most so-called conventional superconducting materials, the critical temperature is between 1 and 33 kelvins. In the superconducting state, a material acquires the ability to conduct an electric current perfectly, without resistance, and therefore without energy loss.

[0068] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated otherwise, The adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.

[0069] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.

[0070] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions from the first step may be repeated later. Thus, the term "step" does not necessarily imply unitary actions that are inseparable in time and in the sequence of phases of the process.

[0071] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures. When only one coordinate system is shown on the same sheet of figures, this coordinate system applies to all the figures on that sheet.

[0072] The relative terms "on", "overcomes", "under", "underlying", "intercalated" refer to positions taken along the z direction.

[0073] Unless explicitly stated, thickness, height and depth are measured along z. The terms "vertical" and "vertically" refer to the z direction. The terms "lateral" and "laterally" refer to a direction in the xy plane.

[0074] An element located "in line with" or "directly above" another element means that these two elements are located on the same line oriented vertically on the cross-sectional figures.

[0075] In the context of the present invention, the adjective "cryogenic" refers to the temperature range of 10 K or below. In the case of a cryogenic component, it is designed or configured to operate at these temperatures. It generally does not function correctly at temperatures higher than 10 K.

[0076] By synecdoche, we call capacitance (respectively inductance) any electronic component designed by its construction to have a certain value (physical quantity) of capacitance (respectively inductance), just as we call resistors the components used for their electrical resistance.

[0077] A structure "suspended" in the cavity is understood to be a structure having at least one part not in contact with the surrounding matrix. This part is typically entirely surrounded by the medium filling the cavity. The medium filling the cavity is typically a dry gaseous medium with a relative humidity of less than 10%.

[0078] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting a speed of The selectivity of material A is the ratio of the etching speed of material A to the etching speed of material B. It is denoted SA:B. A selectivity SA:B of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.

[0079] An object of the invention is a routing zone allowing the functional zone and the control zone to be electrically connected and thermally isolated from each other.

[0080] Figures 1 to 11 schematically illustrate manufacturing steps for an electronic device according to an embodiment in which the functional area is formed separately on a first chip, the control area is formed separately on a second chip, and the routing area is formed separately in the form of an interposer configured to accommodate the first and second chips. Figures 1 to 10 illustrate the formation of this interposer.

[0081] As illustrated in [Fig. 1], the process is implemented on a substrate 10 comprising at least one metal layer M1 integrated into a dielectric-based matrix 11. The substrate 10 is typically a silicon-based substrate used as a support for creating metallic interconnections via "back end of line" (BEOL) processes. The matrix 11 may comprise one or more metal layers. In the example shown in [Fig. 1], only one metal layer M1 is represented for clarity. The metal layer M1 typically includes connection or transmission lines 21. These lines 21 may be conductive or superconducting, depending on the type of device envisaged.

[0082] A first encapsulation layer 12 is deposited on the metal level ML. The first encapsulation layer 12 typically has a thickness between 50 nm and 200 nm, for example on the order of 120 nm. A first portion of a sacrificial layer 13a is then deposited on the first encapsulation layer 12. The first portion of the sacrificial layer 13a typically has a thickness on the order of 500 nm.

[0083] The materials of the first encapsulation layer 12 and the first part of the sacrificial layer 13a are chosen to obtain a high etching selectivity between the first part of the sacrificial layer 13a and the first encapsulation layer 12. Preferably, the etching selectivity between the first part of the sacrificial layer 13a and the first encapsulation layer 12, denoted Si3:i2, is on the order of 10:1, more preferably on the order of 20:1 or higher. For example, a silicon oxide produced by PECVD at 400°C from the precursor TEOS and O2 could be chosen for the first encapsulation layer 12, and a silicon nitride SiN deposited by PECVD at low temperature, for example at 175°C, for the first Sacrificial layer portion 13a. For wet etching with 1% by volume hydrofluoric acid (HF), SiN deposited by PECVD at low temperature exhibits a high etching rate, while TEOS deposited by PECVD at 400°C exhibits a slow etching rate. Alternatively, for example, SiN prepared at 175°C without NH3 gas could be chosen for the first encapsulation layer 12, and SiN prepared at 175°C with NH3 gas for the first part of the sacrificial layer 13a. For wet etching with 1% by volume hydrofluoric acid (HF), SiN prepared at 175°C with NH3 gas exhibits a high etching rate, while SiN prepared at 175°C without NH3 gas exhibits a slow etching rate. Other material pairs and / or different selective etching chemistries are possible. The first encapsulation layer 12 can notably be based on Boron-doped SiC, SiCN, SiN.The first sacrificial layer 13a can notably be based on PSG silicon oxide (acronym for "Phosphosilicate Glass"). The first sacrificial layer 13a can also be based on silicon oxide produced from the TEOS precursor under different processing conditions than those of the first encapsulation layer 12, in order to obtain Si3:i2 etching selectivity.

[0084] As illustrated in [Fig. 2], interconnections 31 are formed in a known manner through the first sacrificial layer 13a and the first encapsulation layer 12, by etching through vias and metallization, for example, with tungsten W or TiN. The interconnections 31 can also be made from superconducting materials. The interconnections 31 electrically connect the metal lines 21 of the metal level ML. A superconducting material, for example Niobium, Niobium Nitride and / or Titanium Nitride, Tantalum Nitride, Tantalum, or Aluminum, is then deposited on the first part of the sacrificial layer 13a and on the interconnections 31. The Niobium and Niobium Nitride can advantageously be encapsulated in thin upper and lower layers of Titanium and / or Titanium Nitride. This prevents oxidation of these materials.The integration of these materials is thus facilitated. This layer of superconducting material typically has a thickness between 10 nm and 500 nm, for example, on the order of 200 nm. It is structured by lithography and etching to form the passive structures 22 of the superconducting level S2. The passive structures 22 may include connection or transmission lines, and / or passive components such as resistors, capacitors, and inductors. The passive structures 22 are electrically connected to the metallic lines 21 by the interconnections 31. In the case where the passive structures 22 are superconducting transmission lines, they preferably have a dimension along y between 250 nm and 100 pm. The inter- . Connections 31 may have a height dimension along z between 400 nm and 2 pm. Interconnections 31 may have a diameter in the xy plane between 200 nm and 10 pm.

[0085] As illustrated in [Fig. 3], a second sacrificial layer portion 13b is then deposited on the first sacrificial layer portion 13a and on the passive structures 22. The second sacrificial layer portion 13b typically has a thickness of approximately 1.5 pm. The first and second sacrificial layers 13a and 13b together form the sacrificial layer 13. The sacrificial layer 13 surrounds the passive structures 22. The sacrificial layer 13 is preferably in direct contact with the passive structures 22. The passive structures 22 are embedded within the sacrificial layer 13. The sacrificial layer 13 forms a dielectric matrix within which the passive structures 22 are embedded.

[0086] As illustrated in [Fig. 4], interconnections 32 are formed in a known manner through the second part of the sacrificial layer 13b, by etching through vias and metallization based, for example, on tungsten W or TiN. The interconnections 32 can also be made from superconducting materials. The interconnections 32 electrically connect the passive structures 22 of the superconducting level S2. A planarization step by chemical-mechanical polishing (CMP) is typically performed.

[0087] As illustrated in [Fig. 5], a second encapsulation layer 14 is deposited on the sacrificial layer 13 and on the interconnections 32. Then a dielectric layer 15a is deposited on the second encapsulation layer 14. A conventional Damascus process is carried out to form the lines 23 of the metal level M2. These lines 23 can be conductive or superconducting, metallic or non-metallic, depending on the type of device envisaged.

[0088] As illustrated in [Fig. 6], connecting pads 41 are formed in a known manner by an UBM (Under Bump Metallurgy) type process in the dielectric layer 15 and the SiN-based passivation layer 16. The connecting pads 41 electrically connect the metal lines 23 of the metal level M2.

[0089] As illustrated in [Fig. 7], openings 51 are then made through the layers 16, 15, 14 into the sacrificial layer 13. The openings 51 are typically formed by anisotropic dry etching along z. The openings 51 lead onto or into the sacrificial layer 13. They preferably extend within the sacrificial layer 13. The cessation of the etching can be time-controlled. Depending on one possibility, stop pads 50 for the etching may have been provided, for example, during the fabrication of the interconnections 31. The stop pads 50 may be made of the same material as the interconnections 31 and have the same height as the interconnections. connections 31. The stop pads 50 are located directly above the openings 51. This makes it easier to form the openings 51, by precisely controlling the depth of engraving of the openings 51. The openings 51 have dimensions in the xy plane between 100 nm and 100 pm, typically on the order of 2 pm to limit the form factor of the openings to be engraved.

[0090] As illustrated in [Fig. 8], cavities 52 are then formed within the sacrificial layer 13. These cavities 52 are formed by removing the sacrificial layer 13 through the openings 51. The removal of the sacrificial layer 13 is achieved by selectively etching the sacrificial layer 13 with respect to the first and second encapsulation layers 12, 14. The selective etching is typically isotropic. This selective etching can be carried out using aqueous or gaseous solutions based on HF, NH4F, or NH4F / HF mixtures at various concentrations. Isopropanol-type additives can be added to these mixtures. The cavities 52 are configured to surround the passive structures 22, at least partially. In particular, the passive structures 22 have at least one part completely free of the sacrificial layer 13, in direct contact with the gas filling the cavities 52.The passive structures 22 typically have a cross-section in an xz or yz plane completely surrounded by a cavity 52. ​​This allows for thermal insulation between the lines 23 of the metal level M2 of the routing zone. This also allows for thermal insulation between the lines 21 of the metal level M1 of the routing zone. In particular, thermal conduction leakage through the sacrificial layer 13 is reduced or eliminated.

[0091] According to one possibility, the cavities 52 are created by controlling the selective etching time. This determines the size of the cavities 52. The etching speed of the sacrificial layer 13 can vary between 10 nm / min and 1pm / min, and typically between 100 nm / min and 300 nm / min. The etching time can thus be between 5 min and 1 h, for example, about 30 min. According to an advantageous possibility, the position of the openings 51 and the size of the cavities 52 are such that support structures 53 are maintained between the first and second encapsulation layers 12, 14. These support structures 53 can be in the form of pillars made of the material of the sacrificial layer 53. The support structures 53 can advantageously be located under the partially suspended passive structures 22. In the example illustrated in [Fig.8], a support structure 53 in the form of a pillar is preserved around a passive structure 22.This pillar 53 comprises a lower part 53a under the passive structure 22, directly in contact with the passive structure 22, and an upper part 53b on the passive structure 22, directly in contact with the passive structure 22. This allows for the mechanical reinforcement of the routing area C3.

[0092] According to one possibility illustrated in [Fig.9], one or more walls configured to circumvent The walls of the cavity or cavities 52 may have been provided for, for example, during the fabrication of the interconnections 31, 32. These walls typically form a sealing ring around the openings 51, projecting in the xy plane, configured to stop the lateral expansion of the cavities 52 during selective etching. These walls are typically made of a material exhibiting high etching selectivity. The walls are thus only slightly or not at all etched during selective etching. According to an advantageous possibility illustrated in [Fig. 9], the walls 30 can be formed by certain interconnections 31, 32 alone or in combination. These interconnections 31, 32 typically form, possibly with a passive structure 22, a continuous wall along z preventing the propagation of the selective etching solution beyond this wall. The dimensions of the cavity 52 thus formed are precisely defined. Stopping the selective etching is less critical.

[0093] As illustrated in [Fig. 10], according to one possibility, a sealing layer 17, for example polymer-based, is formed on the passivation layer 16 and on the openings 51 so as to hermetically seal said openings. The cavity or cavities 52 are not in contact with the external environment. The cavity or cavities 52 are preferably filled with a dry gas. This can prevent condensation and ice formation inside the cavities 52 when the device is cooled to cryogenic temperatures.

[0094] As illustrated in [Fig. 11], after the routing area C3 is implemented as an interposer, the functional chip C1 is assembled to the routing area C3 via connection pads accommodating electrical connections 61, for example, by soldering. The control chip C2 is also assembled to the routing area C3 via connection pads accommodating electrical connections 62, for example, by soldering. The device thus comprises a functional chip C1 configured to operate at cryogenic temperatures, and a control chip C2 electrically connected to the functional chip C1 via the routing area C3. Advantageously, the functional chip C1 and the control chip C2 are thermally insulated from each other via the superconducting layer S2 and the cavities 52 of the routing area C3.According to one possibility, the electrically conductive elements of the C3 routing area, including all lines 21, 22, 23, interconnections 31, 32, connection pads 41 and electrical links 61, 62, are based on superconducting materials.

[0095] Figures 12A, 12B and 13 illustrate different possibilities for forming the openings 51.

[0096] Figure 12A illustrates, in top view, four regularly spaced openings 51, typically distributed in a grid with a pitch p1 along x and a pitch p2 along y. During isotropic selective etching, the cavities 52 extend in such a way circular around the apertures 51. Depending on the selective etching time, the cavities 52 can join laterally, along x and / or y. After isotropic selective etching, a pillar 53 based on the sacrificial layer can be retained, typically equidistant from the apertures 51. As an example, the array of apertures 51 is a square array with a pitch pl = p2 = 5 pm. The apertures 51 are round with a diameter of 1 pm. Isotropic selective etching has an etching speed on the order of 100 nm / min. By setting the selective etching time to 30 min, a lateral consumption of the sacrificial layer of approximately 3 pm is obtained. A pillar 53 with a characteristic dimension in the xy plane, for example a diameter or pseudodiameter, on the order of 1 pm is thus obtained.

[0097] Figure 12B illustrates the use of such an array of apertures 51 to form support pillars 53 under the passive structure lines 22. Typically, for passive structure lines 22 separated by a pitch or a distance p along y, the array of apertures 53 is a square array of the same pitch p, offset by p / 2 along y with respect to the passive structure lines 22. Support pillars 53 can thus be formed under the passive structure lines 22. Positioning the support pillars 53, made of dielectric material, under the passive structure lines 22 minimizes RF losses.

[0098] Figure 13 illustrates another distribution of openings 51 in the form of a grid. In this example, the openings 51 are in the form of rectangles of width 11 = 1pm. The y-length of the openings 51 can be fixed according to the spacing p separating the lines of passive structures 22, maintaining a spacing dl of approximately 1 pm along y between the ends of the openings 51 and the lines of passive structures 22. The spacing pl of the grid of openings 51 can be approximately 7 pm. Such a grid of openings 51 makes it possible to form cavities 52 separated by support structures 53 in the form of walls extending along y. The lines of passive structures 22 are here partially suspended in the cavities 52 and supported by the support walls 53.

[0099] Figures 14A, 14B and 15 schematically illustrate in top view different possible arrangements for the functional area Cl, the routing area C3 and the control area C2 of the electronic device.

[0100] Fig. 14A illustrates a routing area C3 integrated on an interposer substrate 10, between a functional chip location Cl and a control chip location C2. The passive structures 22 and the area comprising the cavities 52 are schematically represented.

[0101] Figure [14B] also illustrates a routing area C3 integrated on an interposer substrate 10, between a functional chip location C1 and a control chip location C2. The passive structures 22 and the area comprising the cavities 52 are schematically represented. In this example, the area containing the cavities 52 extends across the entire width along y of the interposer substrate 10. Thermal insulation is thus achieved through and through the interposer.

[0102] Figure 15 illustrates another arrangement in which the functional area Cl, the routing area C3, and the control area C2 are monolithically co-integrated within the same chip. The routing area C3 thermally separates and electrically connects the functional area Cl and the control area C2.

[0103] The functional region C1 may advantageously include cryogenic quantum bit (qubit) components. The control region C2 may advantageously include CMOS (or "cryoCMOS") control components.

[0104] The invention is not limited to the embodiments described above. Other architectures and / or other cryogenic components can be considered on the principle of a routing zone comprising a superconducting level partially suspended in cavities.

Claims

Claims

1. Electronic device comprising at least: - a first zone (Cl) called functional comprising at least one so-called cryogenic component configured to operate at a temperature below 10 K, preferably below 4 K, - a second zone (C2) called control comprising at least one electronic control component configured to control the at least one cryogenic component, - a third zone (C3) called routing, interposed between the functional zone (Cl) and the control zone (C2), comprising at least one passive structure (22) electrically connected to the at least one cryogenic component on the one hand and / or electrically connected to the at least one electronic control component on the other hand, - a dielectric matrix (13) included at least in part in the routing zone (C3), the at least one passive structure (22) being based on a superconducting material and being integrated in the dielectric matrix (13),the device being characterized in that the dielectric matrix (13) comprises at least one cavity (52) around the at least one passive structure (22), so that the at least one passive structure (22) is at least partly suspended in said cavity (52).,

2. Device according to the preceding claim wherein the at least one cavity (52) comprises at least one support structure (53) configured to support the at least one passive structure (22) within the at least one cavity (52).

3. Device according to the preceding claim in which the at least one support structure (53) is in the form of a pillar comprising a lower part (53a) located under the at least one passive structure (22) and an upper part (53b) located on the at least one passive structure (22).

4. Device according to any one of the preceding claims in which the at least one passive structure (22) is in the form of one of: a superconducting line, a resistor, a capacitor, an inductance.

5. Device according to any one of the preceding claims in which the at least one cavity (52) is filled with a neutral gas, and the at least one passive structure (22) is in contact with said neutral gas.

6. Device according to any one of the preceding claims in which the at least one cryogenic component of the functional zone (Cl) is a quantum bit component.

7. Device according to any one of the preceding claims in which the functional area (Cl) is in the form of a first chip and the control area (C2) is in the form of a second chip, and in which the routing area (C3) is integrated on a substrate (10) called an interposer, the first and second chips being mounted on the interposer and connected to the routing area (C3) respectively by first and second electrical connections (61, 62).

8. Device according to the preceding claim in which the routing zone (C3) comprises an upper electrical conduction level (M2) configured to be in direct contact with the first and second electrical connections (61, 62) of the first and second chips, and in which the at least one passive structure (22) based on a superconducting material of the routing zone (C3) is located immediately below said upper electrical conduction level (M2).

9. System comprising the electronic device according to any one of the preceding claims and a cooling means configured so as to maintain the at least one cryogenic component at a temperature below 10 K, preferably below 4 K.

10. Method for producing a device according to any one of the preceding claims comprising at least the following steps: - Providing the functional area (Cl) and the control area (C2), - Forming the routing area (C3) by carrying out at least the following steps: • Forming a stack comprising, in a z direction, a first encapsulation layer (12), a first sacrificial layer portion (13a), the at least one passive structure (22) based on a superconducting material, a second sacrificial layer portion (13b) forming with the first sacrificial layer portion (13a) a sacrificial layer (13), a second encapsulation layer (14), • Forming at least one opening (51) in the second encapsulation layer (14) opening into the sacrificial layer (13), • At least partially removing the sacrificial layer (13) through said at least one opening (51), by selective etching of the sacrificial layer (13) with respect to the first and second encapsulation layers (12, 14), so as to form at least one cavity (52) around the at least one passive structure (22), - Electrically connecting the functional area (Cl) and / or the control area (C2) to the at least one passive structure (22) of the routing area (C3).

11. Method according to the preceding claim in which the formation of the at least one opening (51) comprises a definition of a plurality of openings (51) distributed in an array on the routing zone (C3), outside the at least one passive structure (22) in projection in the z direction, and in which the removal by selective etching of the sacrificial layer (13) is configured to retain a portion of said sacrificial layer (13) between adjacent openings (51) of the plurality of openings, so as to form at least one support structure (53) directly above the at least one passive structure (22).

12. Method according to the preceding claim in which the formation of the at least one passive structure (22) comprises a definition of a plurality of passive structures forming a first network having a first pitch p, the plurality of openings (51) forming a second network offset with respect to the first network, in projection according to the z direction, and having a second pitch p2 multiple of the first pitch p, the offset between the first and second networks preferably corresponding to half of the first pitch, p / 2.

13. A method according to any one of claims 10 to 12, further comprising, before forming the at least one cavity (52), forming at least one wall (30) configured to circumscribe the at least one cavity (52) in the routing zone (C3).

14. Method according to the preceding claim in which said at least a wall (30) corresponds to an interconnection (31, 32) between a first level of electrical conduction (M1) located under the at least one passive structure (22) and a second level of electrical conduction (M2) located above the at least one passive structure (22).

15. Method according to any one of claims 10 to 14, wherein the sacrificial layer (13) is based on SiN produced with gaseous NH3, wherein the first and second encapsulation layers (12, 14) are based on SiN produced without NH3, and wherein the selective etching is a wet etching based on dilute hydrofluoric acid.

16. Method according to any one of claims 10 to 15, further comprising, after formation of the at least one cavity (52), formation of a sealing layer (17), for example based on polymer, configured to plug the at least one opening (51).

17. Method according to any one of claims 10 to 16, wherein the formation of the at least one opening (51) is carried out by anisotropic etching of the sacrificial layer (13), in the z direction, said method further comprising, before formation of the at least one opening (51), formation of at least one stop pad (50) in the sacrificial layer (13), directly above the at least one opening (51), configured to stop the anisotropic etching, so that the at least one opening (51) extends within the sacrificial layer (13) as far as the at least one stop pad (50).

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